Lines Matching +full:edma +full:- +full:err
1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
25 #include <linux/platform_data/edma.h>
28 #include "../virt-dma.h"
42 /* Offsets for EDMA CC global channel registers and their shadows */
66 /* Offsets for EDMA CC global registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
101 #define GET_NUM_QDMACH(x) ((x & 0x70) >> 4) /* bits 4-6 */
102 #define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
103 #define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
104 #define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
114 * fail. Today davinci-pcm is the only user of this driver and
121 #define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
122 #define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
129 * reg0: channel/event 0-31
130 * reg1: channel/event 32-63
133 * bit 0-4 (0x1f) is the bit offset within the register
183 * - processed_stat: the number of SG elements we have traversed
186 * refers to the number of pending transfer (programmed to EDMA
190 * - residue: The amount of bytes we have left to transfer for this desc
192 * - residue_stat: The residue in bytes of data we have covered
196 * - sg_len: Tracks the length of the current intermediate transfer,
286 .compatible = "ti,edma3-tpcc",
294 { .compatible = "ti,edma3-tptc", },
301 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
306 __raw_writel(val, ecc->base + offset); in edma_write()
391 struct edma_cc *ecc = echan->ecc; in edma_set_chmap()
392 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_set_chmap()
394 if (ecc->chmap_exist) { in edma_set_chmap()
402 struct edma_cc *ecc = echan->ecc; in edma_setup_interrupt()
403 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_setup_interrupt()
422 if (slot >= ecc->num_slots) in edma_write_slot()
424 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE); in edma_write_slot()
431 if (slot >= ecc->num_slots) in edma_read_slot()
432 return -EINVAL; in edma_read_slot()
433 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE); in edma_read_slot()
439 * edma_alloc_slot - allocate DMA parameter RAM
458 if (ecc->chmap_exist && slot < ecc->num_channels) in edma_alloc_slot()
463 if (ecc->chmap_exist) in edma_alloc_slot()
466 slot = ecc->num_channels; in edma_alloc_slot()
468 slot = find_next_zero_bit(ecc->slot_inuse, in edma_alloc_slot()
469 ecc->num_slots, in edma_alloc_slot()
471 if (slot == ecc->num_slots) in edma_alloc_slot()
472 return -ENOMEM; in edma_alloc_slot()
473 if (!test_and_set_bit(slot, ecc->slot_inuse)) in edma_alloc_slot()
476 } else if (slot >= ecc->num_slots) { in edma_alloc_slot()
477 return -EINVAL; in edma_alloc_slot()
478 } else if (test_and_set_bit(slot, ecc->slot_inuse)) { in edma_alloc_slot()
479 return -EBUSY; in edma_alloc_slot()
484 return EDMA_CTLR_CHAN(ecc->id, slot); in edma_alloc_slot()
490 if (slot >= ecc->num_slots) in edma_free_slot()
494 clear_bit(slot, ecc->slot_inuse); in edma_free_slot()
498 * edma_link - link one parameter RAM slot to another
508 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n"); in edma_link()
512 if (from >= ecc->num_slots || to >= ecc->num_slots) in edma_link()
520 * edma_get_position - returns the current transfer point
547 struct edma_cc *ecc = echan->ecc; in edma_start()
548 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_start()
552 if (!echan->hw_triggered) { in edma_start()
553 /* EDMA channels without event association */ in edma_start()
554 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_start()
558 /* EDMA channel with event association */ in edma_start()
559 dev_dbg(ecc->dev, "ER%d %08x\n", idx, in edma_start()
567 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_start()
574 struct edma_cc *ecc = echan->ecc; in edma_stop()
575 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_stop()
587 dev_dbg(ecc->dev, "EER%d %08x\n", idx, in edma_stop()
596 * Temporarily disable EDMA hardware events on the specified channel,
601 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_pause()
603 edma_shadow0_write_array(echan->ecc, SH_EECR, in edma_pause()
608 /* Re-enable EDMA hardware events on the specified channel. */
611 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_resume()
613 edma_shadow0_write_array(echan->ecc, SH_EESR, in edma_resume()
620 struct edma_cc *ecc = echan->ecc; in edma_trigger_channel()
621 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_trigger_channel()
627 dev_dbg(ecc->dev, "ESR%d %08x\n", idx, in edma_trigger_channel()
633 struct edma_cc *ecc = echan->ecc; in edma_clean_channel()
634 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_clean_channel()
638 dev_dbg(ecc->dev, "EMR%d %08x\n", idx, in edma_clean_channel()
652 struct edma_cc *ecc = echan->ecc; in edma_assign_channel_eventq()
653 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_assign_channel_eventq()
658 eventq_no = ecc->default_queue; in edma_assign_channel_eventq()
659 if (eventq_no >= ecc->num_tc) in edma_assign_channel_eventq()
670 struct edma_cc *ecc = echan->ecc; in edma_alloc_channel()
671 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_alloc_channel()
673 if (!test_bit(echan->ch_num, ecc->channels_mask)) { in edma_alloc_channel()
674 dev_err(ecc->dev, "Channel%d is reserved, can not be used!\n", in edma_alloc_channel()
675 echan->ch_num); in edma_alloc_channel()
676 return -EINVAL; in edma_alloc_channel()
719 struct edma_cc *ecc = echan->ecc; in edma_execute()
722 struct device *dev = echan->vchan.chan.device->dev; in edma_execute()
725 if (!echan->edesc) { in edma_execute()
727 vdesc = vchan_next_desc(&echan->vchan); in edma_execute()
730 list_del(&vdesc->node); in edma_execute()
731 echan->edesc = to_edma_desc(&vdesc->tx); in edma_execute()
734 edesc = echan->edesc; in edma_execute()
737 left = edesc->pset_nr - edesc->processed; in edma_execute()
739 edesc->sg_len = 0; in edma_execute()
743 j = i + edesc->processed; in edma_execute()
744 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param); in edma_execute()
745 edesc->sg_len += edesc->pset[j].len; in edma_execute()
758 j, echan->ch_num, echan->slot[i], in edma_execute()
759 edesc->pset[j].param.opt, in edma_execute()
760 edesc->pset[j].param.src, in edma_execute()
761 edesc->pset[j].param.dst, in edma_execute()
762 edesc->pset[j].param.a_b_cnt, in edma_execute()
763 edesc->pset[j].param.ccnt, in edma_execute()
764 edesc->pset[j].param.src_dst_bidx, in edma_execute()
765 edesc->pset[j].param.src_dst_cidx, in edma_execute()
766 edesc->pset[j].param.link_bcntrld); in edma_execute()
768 if (i != (nslots - 1)) in edma_execute()
769 edma_link(ecc, echan->slot[i], echan->slot[i + 1]); in edma_execute()
772 edesc->processed += nslots; in edma_execute()
775 * If this is either the last set in a set of SG-list transactions in edma_execute()
779 if (edesc->processed == edesc->pset_nr) { in edma_execute()
780 if (edesc->cyclic) in edma_execute()
781 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]); in edma_execute()
783 edma_link(ecc, echan->slot[nslots - 1], in edma_execute()
784 echan->ecc->dummy_slot); in edma_execute()
787 if (echan->missed) { in edma_execute()
793 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); in edma_execute()
798 echan->missed = 0; in edma_execute()
799 } else if (edesc->processed <= MAX_NR_SG) { in edma_execute()
801 echan->ch_num); in edma_execute()
805 echan->ch_num, edesc->processed); in edma_execute()
816 spin_lock_irqsave(&echan->vchan.lock, flags); in edma_terminate_all()
821 * echan->edesc is NULL and exit.) in edma_terminate_all()
823 if (echan->edesc) { in edma_terminate_all()
826 if (!echan->tc && echan->edesc->cyclic) in edma_terminate_all()
829 vchan_terminate_vdesc(&echan->edesc->vdesc); in edma_terminate_all()
830 echan->edesc = NULL; in edma_terminate_all()
833 vchan_get_all_descriptors(&echan->vchan, &head); in edma_terminate_all()
834 spin_unlock_irqrestore(&echan->vchan.lock, flags); in edma_terminate_all()
835 vchan_dma_desc_free_list(&echan->vchan, &head); in edma_terminate_all()
844 vchan_synchronize(&echan->vchan); in edma_synchronize()
852 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || in edma_slave_config()
853 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) in edma_slave_config()
854 return -EINVAL; in edma_slave_config()
856 if (cfg->src_maxburst > chan->device->max_burst || in edma_slave_config()
857 cfg->dst_maxburst > chan->device->max_burst) in edma_slave_config()
858 return -EINVAL; in edma_slave_config()
860 memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); in edma_slave_config()
869 if (!echan->edesc) in edma_dma_pause()
870 return -EINVAL; in edma_dma_pause()
901 struct device *dev = chan->device->dev; in edma_config_pset()
902 struct edmacc_param *param = &epset->param; in edma_config_pset()
912 * A-synced transfers. This allows for large contiguous in edma_config_pset()
917 * For the A-sync case, bcnt and ccnt are the remainder in edma_config_pset()
919 * (dma_length / acnt) by (SZ_64K -1). This is so in edma_config_pset()
921 * Note: In A-sync transfer only, bcntrld is used, but it in edma_config_pset()
923 * In this case, the best way adopted is- bccnt for the in edma_config_pset()
925 * every successive frame, bcnt will be SZ_64K-1. This in edma_config_pset()
929 ccnt = dma_length / acnt / (SZ_64K - 1); in edma_config_pset()
930 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1); in edma_config_pset()
932 * If bcnt is non-zero, we have a remainder and hence an in edma_config_pset()
938 bcnt = SZ_64K - 1; in edma_config_pset()
943 * use AB-synced transfers where A count is the fifo in edma_config_pset()
947 * to SZ_64K-1. This places an upper bound on the length in edma_config_pset()
953 if (ccnt > (SZ_64K - 1)) { in edma_config_pset()
955 return -EINVAL; in edma_config_pset()
960 epset->len = dma_length; in edma_config_pset()
967 epset->addr = src_addr; in edma_config_pset()
973 epset->addr = dst_addr; in edma_config_pset()
979 epset->addr = src_addr; in edma_config_pset()
982 return -EINVAL; in edma_config_pset()
985 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); in edma_config_pset()
988 param->opt |= SYNCDIM; in edma_config_pset()
990 param->src = src_addr; in edma_config_pset()
991 param->dst = dst_addr; in edma_config_pset()
993 param->src_dst_bidx = (dst_bidx << 16) | src_bidx; in edma_config_pset()
994 param->src_dst_cidx = (dst_cidx << 16) | src_cidx; in edma_config_pset()
996 param->a_b_cnt = bcnt << 16 | acnt; in edma_config_pset()
997 param->ccnt = ccnt; in edma_config_pset()
1000 * A-sync case, and in this case, a requirement of reload value in edma_config_pset()
1001 * of SZ_64K-1 only is assured. 'link' is initially set to NULL in edma_config_pset()
1004 param->link_bcntrld = 0xffffffff; in edma_config_pset()
1014 struct device *dev = chan->device->dev; in edma_prep_slave_sg()
1026 src_addr = echan->cfg.src_addr; in edma_prep_slave_sg()
1027 dev_width = echan->cfg.src_addr_width; in edma_prep_slave_sg()
1028 burst = echan->cfg.src_maxburst; in edma_prep_slave_sg()
1030 dst_addr = echan->cfg.dst_addr; in edma_prep_slave_sg()
1031 dev_width = echan->cfg.dst_addr_width; in edma_prep_slave_sg()
1032 burst = echan->cfg.dst_maxburst; in edma_prep_slave_sg()
1047 edesc->pset_nr = sg_len; in edma_prep_slave_sg()
1048 edesc->residue = 0; in edma_prep_slave_sg()
1049 edesc->direction = direction; in edma_prep_slave_sg()
1050 edesc->echan = echan; in edma_prep_slave_sg()
1056 if (echan->slot[i] < 0) { in edma_prep_slave_sg()
1057 echan->slot[i] = in edma_prep_slave_sg()
1058 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_slave_sg()
1059 if (echan->slot[i] < 0) { in edma_prep_slave_sg()
1076 ret = edma_config_pset(chan, &edesc->pset[i], src_addr, in edma_prep_slave_sg()
1084 edesc->absync = ret; in edma_prep_slave_sg()
1085 edesc->residue += sg_dma_len(sg); in edma_prep_slave_sg()
1087 if (i == sg_len - 1) in edma_prep_slave_sg()
1089 edesc->pset[i].param.opt |= TCINTEN; in edma_prep_slave_sg()
1097 edesc->pset[i].param.opt |= (TCINTEN | TCCMODE); in edma_prep_slave_sg()
1099 edesc->residue_stat = edesc->residue; in edma_prep_slave_sg()
1101 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_slave_sg()
1110 struct device *dev = chan->device->dev; in edma_prep_dma_memcpy()
1120 array_size = SZ_32K - 1; in edma_prep_dma_memcpy()
1123 array_size = SZ_32K - 2; in edma_prep_dma_memcpy()
1126 array_size = SZ_32K - 4; in edma_prep_dma_memcpy()
1146 * ACNT = full_length - length1, length2 = ACNT in edma_prep_dma_memcpy()
1153 /* One slot is enough for lengths multiple of (SZ_32K -1) */ in edma_prep_dma_memcpy()
1164 edesc->pset_nr = nslots; in edma_prep_dma_memcpy()
1165 edesc->residue = edesc->residue_stat = len; in edma_prep_dma_memcpy()
1166 edesc->direction = DMA_MEM_TO_MEM; in edma_prep_dma_memcpy()
1167 edesc->echan = echan; in edma_prep_dma_memcpy()
1169 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1, in edma_prep_dma_memcpy()
1176 edesc->absync = ret; in edma_prep_dma_memcpy()
1178 edesc->pset[0].param.opt |= ITCCHEN; in edma_prep_dma_memcpy()
1182 edesc->pset[0].param.opt |= TCINTEN; in edma_prep_dma_memcpy()
1185 edesc->pset[0].param.opt |= TCCHEN; in edma_prep_dma_memcpy()
1187 if (echan->slot[1] < 0) { in edma_prep_dma_memcpy()
1188 echan->slot[1] = edma_alloc_slot(echan->ecc, in edma_prep_dma_memcpy()
1190 if (echan->slot[1] < 0) { in edma_prep_dma_memcpy()
1201 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1, in edma_prep_dma_memcpy()
1208 edesc->pset[1].param.opt |= ITCCHEN; in edma_prep_dma_memcpy()
1211 edesc->pset[1].param.opt |= TCINTEN; in edma_prep_dma_memcpy()
1215 edesc->polled = true; in edma_prep_dma_memcpy()
1217 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_dma_memcpy()
1225 struct device *dev = chan->device->dev; in edma_prep_dma_interleaved()
1233 if (is_slave_direction(xt->dir)) in edma_prep_dma_interleaved()
1236 if (xt->frame_size != 1 || xt->numf == 0) in edma_prep_dma_interleaved()
1239 if (xt->sgl[0].size > SZ_64K || xt->numf > SZ_64K) in edma_prep_dma_interleaved()
1242 src_icg = dmaengine_get_src_icg(xt, &xt->sgl[0]); in edma_prep_dma_interleaved()
1244 src_bidx = src_icg + xt->sgl[0].size; in edma_prep_dma_interleaved()
1245 } else if (xt->src_inc) { in edma_prep_dma_interleaved()
1246 src_bidx = xt->sgl[0].size; in edma_prep_dma_interleaved()
1253 dst_icg = dmaengine_get_dst_icg(xt, &xt->sgl[0]); in edma_prep_dma_interleaved()
1255 dst_bidx = dst_icg + xt->sgl[0].size; in edma_prep_dma_interleaved()
1256 } else if (xt->dst_inc) { in edma_prep_dma_interleaved()
1257 dst_bidx = xt->sgl[0].size; in edma_prep_dma_interleaved()
1271 edesc->direction = DMA_MEM_TO_MEM; in edma_prep_dma_interleaved()
1272 edesc->echan = echan; in edma_prep_dma_interleaved()
1273 edesc->pset_nr = 1; in edma_prep_dma_interleaved()
1275 param = &edesc->pset[0].param; in edma_prep_dma_interleaved()
1277 param->src = xt->src_start; in edma_prep_dma_interleaved()
1278 param->dst = xt->dst_start; in edma_prep_dma_interleaved()
1279 param->a_b_cnt = xt->numf << 16 | xt->sgl[0].size; in edma_prep_dma_interleaved()
1280 param->ccnt = 1; in edma_prep_dma_interleaved()
1281 param->src_dst_bidx = (dst_bidx << 16) | src_bidx; in edma_prep_dma_interleaved()
1282 param->src_dst_cidx = 0; in edma_prep_dma_interleaved()
1284 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num)); in edma_prep_dma_interleaved()
1285 param->opt |= ITCCHEN; in edma_prep_dma_interleaved()
1288 param->opt |= TCINTEN; in edma_prep_dma_interleaved()
1290 edesc->polled = true; in edma_prep_dma_interleaved()
1292 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_dma_interleaved()
1301 struct device *dev = chan->device->dev; in edma_prep_dma_cyclic()
1313 src_addr = echan->cfg.src_addr; in edma_prep_dma_cyclic()
1315 dev_width = echan->cfg.src_addr_width; in edma_prep_dma_cyclic()
1316 burst = echan->cfg.src_maxburst; in edma_prep_dma_cyclic()
1319 dst_addr = echan->cfg.dst_addr; in edma_prep_dma_cyclic()
1320 dev_width = echan->cfg.dst_addr_width; in edma_prep_dma_cyclic()
1321 burst = echan->cfg.dst_maxburst; in edma_prep_dma_cyclic()
1342 * number of SGs the EDMA driver can handle at a time. For DMA types in edma_prep_dma_cyclic()
1367 edesc->cyclic = 1; in edma_prep_dma_cyclic()
1368 edesc->pset_nr = nslots; in edma_prep_dma_cyclic()
1369 edesc->residue = edesc->residue_stat = buf_len; in edma_prep_dma_cyclic()
1370 edesc->direction = direction; in edma_prep_dma_cyclic()
1371 edesc->echan = echan; in edma_prep_dma_cyclic()
1374 __func__, echan->ch_num, nslots, period_len, buf_len); in edma_prep_dma_cyclic()
1378 if (echan->slot[i] < 0) { in edma_prep_dma_cyclic()
1379 echan->slot[i] = in edma_prep_dma_cyclic()
1380 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY); in edma_prep_dma_cyclic()
1381 if (echan->slot[i] < 0) { in edma_prep_dma_cyclic()
1389 if (i == nslots - 1) { in edma_prep_dma_cyclic()
1390 memcpy(&edesc->pset[i], &edesc->pset[0], in edma_prep_dma_cyclic()
1391 sizeof(edesc->pset[0])); in edma_prep_dma_cyclic()
1395 ret = edma_config_pset(chan, &edesc->pset[i], src_addr, in edma_prep_dma_cyclic()
1421 i, echan->ch_num, echan->slot[i], in edma_prep_dma_cyclic()
1422 edesc->pset[i].param.opt, in edma_prep_dma_cyclic()
1423 edesc->pset[i].param.src, in edma_prep_dma_cyclic()
1424 edesc->pset[i].param.dst, in edma_prep_dma_cyclic()
1425 edesc->pset[i].param.a_b_cnt, in edma_prep_dma_cyclic()
1426 edesc->pset[i].param.ccnt, in edma_prep_dma_cyclic()
1427 edesc->pset[i].param.src_dst_bidx, in edma_prep_dma_cyclic()
1428 edesc->pset[i].param.src_dst_cidx, in edma_prep_dma_cyclic()
1429 edesc->pset[i].param.link_bcntrld); in edma_prep_dma_cyclic()
1431 edesc->absync = ret; in edma_prep_dma_cyclic()
1437 edesc->pset[i].param.opt |= TCINTEN; in edma_prep_dma_cyclic()
1441 edesc->pset[i].param.opt |= ITCINTEN; in edma_prep_dma_cyclic()
1446 if (!echan->tc) in edma_prep_dma_cyclic()
1449 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags); in edma_prep_dma_cyclic()
1454 struct device *dev = echan->vchan.chan.device->dev; in edma_completion_handler()
1457 spin_lock(&echan->vchan.lock); in edma_completion_handler()
1458 edesc = echan->edesc; in edma_completion_handler()
1460 if (edesc->cyclic) { in edma_completion_handler()
1461 vchan_cyclic_callback(&edesc->vdesc); in edma_completion_handler()
1462 spin_unlock(&echan->vchan.lock); in edma_completion_handler()
1464 } else if (edesc->processed == edesc->pset_nr) { in edma_completion_handler()
1465 edesc->residue = 0; in edma_completion_handler()
1467 vchan_cookie_complete(&edesc->vdesc); in edma_completion_handler()
1468 echan->edesc = NULL; in edma_completion_handler()
1471 echan->ch_num); in edma_completion_handler()
1474 echan->ch_num); in edma_completion_handler()
1479 edesc->residue -= edesc->sg_len; in edma_completion_handler()
1480 edesc->residue_stat = edesc->residue; in edma_completion_handler()
1481 edesc->processed_stat = edesc->processed; in edma_completion_handler()
1486 spin_unlock(&echan->vchan.lock); in edma_completion_handler()
1489 /* eDMA interrupt handler */
1498 ctlr = ecc->id; in dma_irq_handler()
1502 dev_vdbg(ecc->dev, "dma_irq_handler\n"); in dma_irq_handler()
1527 edma_completion_handler(&ecc->slave_chans[channel]); in dma_irq_handler()
1537 struct edma_cc *ecc = echan->ecc; in edma_error_handler()
1538 struct device *dev = echan->vchan.chan.device->dev; in edma_error_handler()
1540 int err; in edma_error_handler() local
1542 if (!echan->edesc) in edma_error_handler()
1545 spin_lock(&echan->vchan.lock); in edma_error_handler()
1547 err = edma_read_slot(ecc, echan->slot[0], &p); in edma_error_handler()
1561 if (err || (p.a_b_cnt == 0 && p.ccnt == 0)) { in edma_error_handler()
1563 echan->missed = 1; in edma_error_handler()
1575 spin_unlock(&echan->vchan.lock); in edma_error_handler()
1588 /* eDMA error interrupt handler */
1597 ctlr = ecc->id; in dma_ccerr_handler()
1601 dev_vdbg(ecc->dev, "dma_ccerr_handler\n"); in dma_ccerr_handler()
1607 * Ask eDMA to re-evaluate the error registers. in dma_ccerr_handler()
1609 dev_err(ecc->dev, "%s: Error interrupt without error event!\n", in dma_ccerr_handler()
1624 dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val); in dma_ccerr_handler()
1634 edma_error_handler(&ecc->slave_chans[k]); in dma_ccerr_handler()
1640 dev_dbg(ecc->dev, "QEMR 0x%02x\n", val); in dma_ccerr_handler()
1648 dev_warn(ecc->dev, "CCERR 0x%08x\n", val); in dma_ccerr_handler()
1667 struct edma_cc *ecc = echan->ecc; in edma_alloc_chan_resources()
1668 struct device *dev = ecc->dev; in edma_alloc_chan_resources()
1672 if (echan->tc) { in edma_alloc_chan_resources()
1673 eventq_no = echan->tc->id; in edma_alloc_chan_resources()
1674 } else if (ecc->tc_list) { in edma_alloc_chan_resources()
1676 echan->tc = &ecc->tc_list[ecc->info->default_queue]; in edma_alloc_chan_resources()
1677 eventq_no = echan->tc->id; in edma_alloc_chan_resources()
1684 echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num); in edma_alloc_chan_resources()
1685 if (echan->slot[0] < 0) { in edma_alloc_chan_resources()
1687 EDMA_CHAN_SLOT(echan->ch_num)); in edma_alloc_chan_resources()
1688 ret = echan->slot[0]; in edma_alloc_chan_resources()
1692 /* Set up channel -> slot mapping for the entry slot */ in edma_alloc_chan_resources()
1693 edma_set_chmap(echan, echan->slot[0]); in edma_alloc_chan_resources()
1694 echan->alloced = true; in edma_alloc_chan_resources()
1696 dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n", in edma_alloc_chan_resources()
1697 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id, in edma_alloc_chan_resources()
1698 echan->hw_triggered ? "HW" : "SW"); in edma_alloc_chan_resources()
1711 struct device *dev = echan->ecc->dev; in edma_free_chan_resources()
1717 vchan_free_chan_resources(&echan->vchan); in edma_free_chan_resources()
1719 /* Free EDMA PaRAM slots */ in edma_free_chan_resources()
1721 if (echan->slot[i] >= 0) { in edma_free_chan_resources()
1722 edma_free_slot(echan->ecc, echan->slot[i]); in edma_free_chan_resources()
1723 echan->slot[i] = -1; in edma_free_chan_resources()
1728 edma_set_chmap(echan, echan->ecc->dummy_slot); in edma_free_chan_resources()
1730 /* Free EDMA channel */ in edma_free_chan_resources()
1731 if (echan->alloced) { in edma_free_chan_resources()
1733 echan->alloced = false; in edma_free_chan_resources()
1736 echan->tc = NULL; in edma_free_chan_resources()
1737 echan->hw_triggered = false; in edma_free_chan_resources()
1739 dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n", in edma_free_chan_resources()
1740 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id); in edma_free_chan_resources()
1749 spin_lock_irqsave(&echan->vchan.lock, flags); in edma_issue_pending()
1750 if (vchan_issue_pending(&echan->vchan) && !echan->edesc) in edma_issue_pending()
1752 spin_unlock_irqrestore(&echan->vchan.lock, flags); in edma_issue_pending()
1760 * RX-FIFO, as many as 55 loops have been seen.
1766 bool dst = edesc->direction == DMA_DEV_TO_MEM; in edma_residue()
1768 struct edma_chan *echan = edesc->echan; in edma_residue()
1769 struct edma_pset *pset = edesc->pset; in edma_residue()
1771 int channel = EDMA_CHAN_SLOT(echan->ch_num); in edma_residue()
1781 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1791 if (is_slave_direction(edesc->direction)) in edma_residue()
1797 while (edma_shadow0_read_array(echan->ecc, event_reg, idx) & ch_bit) { in edma_residue()
1798 pos = edma_get_position(echan->ecc, echan->slot[0], dst); in edma_residue()
1802 if (!--loop_count) { in edma_residue()
1803 dev_dbg_ratelimited(echan->vchan.chan.device->dev, in edma_residue()
1815 * We never update edesc->residue in the cyclic case, so we in edma_residue()
1819 if (edesc->cyclic) { in edma_residue()
1820 done = pos - pset->addr; in edma_residue()
1821 edesc->residue_stat = edesc->residue - done; in edma_residue()
1822 return edesc->residue_stat; in edma_residue()
1826 * If the position is 0, then EDMA loaded the closing dummy slot, the in edma_residue()
1835 pset += edesc->processed_stat; in edma_residue()
1837 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) { in edma_residue()
1843 if (pos >= pset->addr && pos < pset->addr + pset->len) in edma_residue()
1844 return edesc->residue_stat - (pos - pset->addr); in edma_residue()
1847 edesc->processed_stat++; in edma_residue()
1848 edesc->residue_stat -= pset->len; in edma_residue()
1850 return edesc->residue_stat; in edma_residue()
1872 spin_lock_irqsave(&echan->vchan.lock, flags); in edma_tx_status()
1873 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie) { in edma_tx_status()
1874 txstate->residue = edma_residue(echan->edesc); in edma_tx_status()
1876 struct virt_dma_desc *vdesc = vchan_find_desc(&echan->vchan, in edma_tx_status()
1880 txstate->residue = to_edma_desc(&vdesc->tx)->residue; in edma_tx_status()
1882 txstate->residue = 0; in edma_tx_status()
1889 if (ret != DMA_COMPLETE && !txstate->residue && in edma_tx_status()
1890 echan->edesc && echan->edesc->polled && in edma_tx_status()
1891 echan->edesc->vdesc.tx.cookie == cookie) { in edma_tx_status()
1893 vchan_cookie_complete(&echan->edesc->vdesc); in edma_tx_status()
1894 echan->edesc = NULL; in edma_tx_status()
1899 spin_unlock_irqrestore(&echan->vchan.lock, flags); in edma_tx_status()
1908 while (*memcpy_channels != -1) { in edma_is_memcpy_channel()
1923 struct dma_device *s_ddev = &ecc->dma_slave; in edma_dma_init()
1925 s32 *memcpy_channels = ecc->info->memcpy_channels; in edma_dma_init()
1928 dma_cap_zero(s_ddev->cap_mask); in edma_dma_init()
1929 dma_cap_set(DMA_SLAVE, s_ddev->cap_mask); in edma_dma_init()
1930 dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask); in edma_dma_init()
1931 if (ecc->legacy_mode && !memcpy_channels) { in edma_dma_init()
1932 dev_warn(ecc->dev, in edma_dma_init()
1935 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask); in edma_dma_init()
1936 dma_cap_set(DMA_INTERLEAVE, s_ddev->cap_mask); in edma_dma_init()
1937 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; in edma_dma_init()
1938 s_ddev->device_prep_interleaved_dma = edma_prep_dma_interleaved; in edma_dma_init()
1939 s_ddev->directions = BIT(DMA_MEM_TO_MEM); in edma_dma_init()
1942 s_ddev->device_prep_slave_sg = edma_prep_slave_sg; in edma_dma_init()
1943 s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic; in edma_dma_init()
1944 s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; in edma_dma_init()
1945 s_ddev->device_free_chan_resources = edma_free_chan_resources; in edma_dma_init()
1946 s_ddev->device_issue_pending = edma_issue_pending; in edma_dma_init()
1947 s_ddev->device_tx_status = edma_tx_status; in edma_dma_init()
1948 s_ddev->device_config = edma_slave_config; in edma_dma_init()
1949 s_ddev->device_pause = edma_dma_pause; in edma_dma_init()
1950 s_ddev->device_resume = edma_dma_resume; in edma_dma_init()
1951 s_ddev->device_terminate_all = edma_terminate_all; in edma_dma_init()
1952 s_ddev->device_synchronize = edma_synchronize; in edma_dma_init()
1954 s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1955 s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1956 s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); in edma_dma_init()
1957 s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in edma_dma_init()
1958 s_ddev->max_burst = SZ_32K - 1; /* CIDX: 16bit signed */ in edma_dma_init()
1960 s_ddev->dev = ecc->dev; in edma_dma_init()
1961 INIT_LIST_HEAD(&s_ddev->channels); in edma_dma_init()
1964 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL); in edma_dma_init()
1966 dev_warn(ecc->dev, "memcpy is disabled due to OoM\n"); in edma_dma_init()
1970 ecc->dma_memcpy = m_ddev; in edma_dma_init()
1972 dma_cap_zero(m_ddev->cap_mask); in edma_dma_init()
1973 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask); in edma_dma_init()
1974 dma_cap_set(DMA_INTERLEAVE, m_ddev->cap_mask); in edma_dma_init()
1976 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy; in edma_dma_init()
1977 m_ddev->device_prep_interleaved_dma = edma_prep_dma_interleaved; in edma_dma_init()
1978 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources; in edma_dma_init()
1979 m_ddev->device_free_chan_resources = edma_free_chan_resources; in edma_dma_init()
1980 m_ddev->device_issue_pending = edma_issue_pending; in edma_dma_init()
1981 m_ddev->device_tx_status = edma_tx_status; in edma_dma_init()
1982 m_ddev->device_config = edma_slave_config; in edma_dma_init()
1983 m_ddev->device_pause = edma_dma_pause; in edma_dma_init()
1984 m_ddev->device_resume = edma_dma_resume; in edma_dma_init()
1985 m_ddev->device_terminate_all = edma_terminate_all; in edma_dma_init()
1986 m_ddev->device_synchronize = edma_synchronize; in edma_dma_init()
1988 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1989 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS; in edma_dma_init()
1990 m_ddev->directions = BIT(DMA_MEM_TO_MEM); in edma_dma_init()
1991 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in edma_dma_init()
1993 m_ddev->dev = ecc->dev; in edma_dma_init()
1994 INIT_LIST_HEAD(&m_ddev->channels); in edma_dma_init()
1995 } else if (!ecc->legacy_mode) { in edma_dma_init()
1996 dev_info(ecc->dev, "memcpy is disabled\n"); in edma_dma_init()
2000 for (i = 0; i < ecc->num_channels; i++) { in edma_dma_init()
2001 struct edma_chan *echan = &ecc->slave_chans[i]; in edma_dma_init()
2002 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i); in edma_dma_init()
2003 echan->ecc = ecc; in edma_dma_init()
2004 echan->vchan.desc_free = edma_desc_free; in edma_dma_init()
2007 vchan_init(&echan->vchan, m_ddev); in edma_dma_init()
2009 vchan_init(&echan->vchan, s_ddev); in edma_dma_init()
2011 INIT_LIST_HEAD(&echan->node); in edma_dma_init()
2013 echan->slot[j] = -1; in edma_dma_init()
2028 ecc->num_region = BIT(value); in edma_setup_from_hw()
2031 ecc->num_channels = BIT(value + 1); in edma_setup_from_hw()
2034 ecc->num_qchannels = value * 2; in edma_setup_from_hw()
2037 ecc->num_slots = BIT(value + 4); in edma_setup_from_hw()
2040 ecc->num_tc = value + 1; in edma_setup_from_hw()
2042 ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false; in edma_setup_from_hw()
2045 dev_dbg(dev, "num_region: %u\n", ecc->num_region); in edma_setup_from_hw()
2046 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels); in edma_setup_from_hw()
2047 dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels); in edma_setup_from_hw()
2048 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots); in edma_setup_from_hw()
2049 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc); in edma_setup_from_hw()
2050 dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no"); in edma_setup_from_hw()
2053 if (pdata->queue_priority_mapping) in edma_setup_from_hw()
2058 * Q0 - priority 0 in edma_setup_from_hw()
2059 * Q1 - priority 1 in edma_setup_from_hw()
2060 * Q2 - priority 2 in edma_setup_from_hw()
2066 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8), in edma_setup_from_hw()
2069 return -ENOMEM; in edma_setup_from_hw()
2071 for (i = 0; i < ecc->num_tc; i++) { in edma_setup_from_hw()
2075 queue_priority_map[i][0] = -1; in edma_setup_from_hw()
2076 queue_priority_map[i][1] = -1; in edma_setup_from_hw()
2078 pdata->queue_priority_mapping = queue_priority_map; in edma_setup_from_hw()
2080 pdata->default_queue = i - 1; in edma_setup_from_hw()
2089 const char pname[] = "ti,edma-xbar-event-map"; in edma_xbar_event_map()
2099 return -ENOMEM; in edma_xbar_event_map()
2101 ret = of_address_to_resource(dev->of_node, 1, &res); in edma_xbar_event_map()
2103 return -ENOMEM; in edma_xbar_event_map()
2107 return -ENOMEM; in edma_xbar_event_map()
2109 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans, in edma_xbar_event_map()
2112 return -EIO; in edma_xbar_event_map()
2116 xbar_chans[nelm][0] = -1; in edma_xbar_event_map()
2117 xbar_chans[nelm][1] = -1; in edma_xbar_event_map()
2128 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans; in edma_xbar_event_map()
2141 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2144 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", in edma_setup_info_from_dt()
2155 prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz); in edma_setup_info_from_dt()
2157 const char pname[] = "ti,edma-memcpy-channels"; in edma_setup_info_from_dt()
2164 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2166 ret = of_property_read_u32_array(dev->of_node, pname, in edma_setup_info_from_dt()
2171 memcpy_ch[nelm] = -1; in edma_setup_info_from_dt()
2172 info->memcpy_channels = memcpy_ch; in edma_setup_info_from_dt()
2175 prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges", in edma_setup_info_from_dt()
2178 const char pname[] = "ti,edma-reserved-slot-ranges"; in edma_setup_info_from_dt()
2190 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2195 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2202 return ERR_PTR(-ENOMEM); in edma_setup_info_from_dt()
2205 ret = of_property_read_u32_array(dev->of_node, pname, in edma_setup_info_from_dt()
2216 rsv_slots[nelm][0] = -1; in edma_setup_info_from_dt()
2217 rsv_slots[nelm][1] = -1; in edma_setup_info_from_dt()
2219 info->rsv = rsv_info; in edma_setup_info_from_dt()
2220 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots; in edma_setup_info_from_dt()
2231 struct edma_cc *ecc = ofdma->of_dma_data; in of_edma_xlate()
2236 if (!ecc || dma_spec->args_count < 1) in of_edma_xlate()
2239 for (i = 0; i < ecc->num_channels; i++) { in of_edma_xlate()
2240 echan = &ecc->slave_chans[i]; in of_edma_xlate()
2241 if (echan->ch_num == dma_spec->args[0]) { in of_edma_xlate()
2242 chan = &echan->vchan.chan; in of_edma_xlate()
2250 if (echan->ecc->legacy_mode && dma_spec->args_count == 1) in of_edma_xlate()
2253 if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 && in of_edma_xlate()
2254 dma_spec->args[1] < echan->ecc->num_tc) { in of_edma_xlate()
2255 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]]; in of_edma_xlate()
2262 echan->hw_triggered = true; in of_edma_xlate()
2269 return ERR_PTR(-EINVAL); in edma_setup_info_from_dt()
2283 struct edma_soc_info *info = pdev->dev.platform_data; in edma_probe()
2289 struct device_node *node = pdev->dev.of_node; in edma_probe()
2290 struct device *dev = &pdev->dev; in edma_probe()
2299 if (match && (*(u32 *)match->data) == EDMA_BINDING_TPCC) in edma_probe()
2310 return -ENODEV; in edma_probe()
2318 return -ENOMEM; in edma_probe()
2320 ecc->dev = dev; in edma_probe()
2321 ecc->id = pdev->id; in edma_probe()
2322 ecc->legacy_mode = legacy_mode; in edma_probe()
2323 /* When booting with DT the pdev->id is -1 */ in edma_probe()
2324 if (ecc->id < 0) in edma_probe()
2325 ecc->id = 0; in edma_probe()
2333 return -ENODEV; in edma_probe()
2336 ecc->base = devm_ioremap_resource(dev, mem); in edma_probe()
2337 if (IS_ERR(ecc->base)) in edma_probe()
2338 return PTR_ERR(ecc->base); in edma_probe()
2356 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels, in edma_probe()
2357 sizeof(*ecc->slave_chans), GFP_KERNEL); in edma_probe()
2359 ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots), in edma_probe()
2362 ecc->channels_mask = devm_kcalloc(dev, in edma_probe()
2363 BITS_TO_LONGS(ecc->num_channels), in edma_probe()
2365 if (!ecc->slave_chans || !ecc->slot_inuse || !ecc->channels_mask) { in edma_probe()
2366 ret = -ENOMEM; in edma_probe()
2371 bitmap_fill(ecc->channels_mask, ecc->num_channels); in edma_probe()
2373 ecc->default_queue = info->default_queue; in edma_probe()
2375 if (info->rsv) { in edma_probe()
2377 reserved = info->rsv->rsv_slots; in edma_probe()
2379 for (i = 0; reserved[i][0] != -1; i++) in edma_probe()
2380 bitmap_set(ecc->slot_inuse, reserved[i][0], in edma_probe()
2385 reserved = info->rsv->rsv_chans; in edma_probe()
2387 for (i = 0; reserved[i][0] != -1; i++) in edma_probe()
2388 bitmap_clear(ecc->channels_mask, reserved[i][0], in edma_probe()
2393 for (i = 0; i < ecc->num_slots; i++) { in edma_probe()
2394 /* Reset only unused - not reserved - paRAM slots */ in edma_probe()
2395 if (!test_bit(i, ecc->slot_inuse)) in edma_probe()
2407 ret = -ENOMEM; in edma_probe()
2414 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret); in edma_probe()
2417 ecc->ccint = irq; in edma_probe()
2428 ret = -ENOMEM; in edma_probe()
2435 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret); in edma_probe()
2438 ecc->ccerrint = irq; in edma_probe()
2441 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY); in edma_probe()
2442 if (ecc->dummy_slot < 0) { in edma_probe()
2444 ret = ecc->dummy_slot; in edma_probe()
2448 queue_priority_mapping = info->queue_priority_mapping; in edma_probe()
2450 if (!ecc->legacy_mode) { in edma_probe()
2455 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc, in edma_probe()
2456 sizeof(*ecc->tc_list), GFP_KERNEL); in edma_probe()
2457 if (!ecc->tc_list) { in edma_probe()
2458 ret = -ENOMEM; in edma_probe()
2465 if (ret || i == ecc->num_tc) in edma_probe()
2468 ecc->tc_list[i].id = i; in edma_probe()
2472 info->default_queue = i; in edma_probe()
2477 /* See if we have optional dma-channel-mask array */ in edma_probe()
2478 array_max = DIV_ROUND_UP(ecc->num_channels, BITS_PER_TYPE(u32)); in edma_probe()
2480 "dma-channel-mask", in edma_probe()
2481 (u32 *)ecc->channels_mask, in edma_probe()
2484 dev_warn(dev, "dma-channel-mask is not complete.\n"); in edma_probe()
2485 else if (ret == -EOVERFLOW || ret == -ENODATA) in edma_probe()
2487 "dma-channel-mask is out of range or empty\n"); in edma_probe()
2491 for (i = 0; queue_priority_mapping[i][0] != -1; i++) in edma_probe()
2499 ecc->info = info; in edma_probe()
2504 for (i = 0; i < ecc->num_channels; i++) { in edma_probe()
2506 if (!test_bit(i, ecc->channels_mask)) in edma_probe()
2510 edma_assign_channel_eventq(&ecc->slave_chans[i], in edma_probe()
2511 info->default_queue); in edma_probe()
2513 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot); in edma_probe()
2516 ecc->dma_slave.filter.map = info->slave_map; in edma_probe()
2517 ecc->dma_slave.filter.mapcnt = info->slavecnt; in edma_probe()
2518 ecc->dma_slave.filter.fn = edma_filter_fn; in edma_probe()
2520 ret = dma_async_device_register(&ecc->dma_slave); in edma_probe()
2526 if (ecc->dma_memcpy) { in edma_probe()
2527 ret = dma_async_device_register(ecc->dma_memcpy); in edma_probe()
2531 dma_async_device_unregister(&ecc->dma_slave); in edma_probe()
2539 dev_info(dev, "TI EDMA DMA engine driver\n"); in edma_probe()
2544 edma_free_slot(ecc, ecc->dummy_slot); in edma_probe()
2556 &dmadev->channels, vchan.chan.device_node) { in edma_cleanupp_vchan()
2557 list_del(&echan->vchan.chan.device_node); in edma_cleanupp_vchan()
2558 tasklet_kill(&echan->vchan.task); in edma_cleanupp_vchan()
2564 struct device *dev = &pdev->dev; in edma_remove()
2567 devm_free_irq(dev, ecc->ccint, ecc); in edma_remove()
2568 devm_free_irq(dev, ecc->ccerrint, ecc); in edma_remove()
2570 edma_cleanupp_vchan(&ecc->dma_slave); in edma_remove()
2572 if (dev->of_node) in edma_remove()
2573 of_dma_controller_free(dev->of_node); in edma_remove()
2574 dma_async_device_unregister(&ecc->dma_slave); in edma_remove()
2575 if (ecc->dma_memcpy) in edma_remove()
2576 dma_async_device_unregister(ecc->dma_memcpy); in edma_remove()
2577 edma_free_slot(ecc, ecc->dummy_slot); in edma_remove()
2588 struct edma_chan *echan = ecc->slave_chans; in edma_pm_suspend()
2591 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_suspend()
2602 struct edma_chan *echan = ecc->slave_chans; in edma_pm_resume()
2607 edma_write_slot(ecc, ecc->dummy_slot, &dummy_paramset); in edma_pm_resume()
2609 queue_priority_mapping = ecc->info->queue_priority_mapping; in edma_pm_resume()
2612 for (i = 0; queue_priority_mapping[i][0] != -1; i++) in edma_pm_resume()
2616 for (i = 0; i < ecc->num_channels; i++) { in edma_pm_resume()
2625 /* Set up channel -> slot mapping for the entry slot */ in edma_pm_resume()
2642 .name = "edma",
2650 pm_runtime_enable(&pdev->dev); in edma_tptc_probe()
2651 return pm_runtime_get_sync(&pdev->dev); in edma_tptc_probe()
2657 .name = "edma3-tptc",
2666 if (chan->device->dev->driver == &edma_driver.driver) { in edma_filter_fn()
2669 if (ch_req == echan->ch_num) { in edma_filter_fn()
2671 echan->hw_triggered = true; in edma_filter_fn()
2698 MODULE_DESCRIPTION("TI EDMA DMA engine driver");