1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2013-2014 Freescale Semiconductor, Inc. 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring#include <dt-bindings/interrupt-controller/arm-gic.h> 7*724ba675SRob Herring#include <dt-bindings/thermal/thermal.h> 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring #address-cells = <2>; 11*724ba675SRob Herring #size-cells = <2>; 12*724ba675SRob Herring interrupt-parent = <&gic>; 13*724ba675SRob Herring 14*724ba675SRob Herring aliases { 15*724ba675SRob Herring crypto = &crypto; 16*724ba675SRob Herring ethernet0 = &enet0; 17*724ba675SRob Herring ethernet1 = &enet1; 18*724ba675SRob Herring ethernet2 = &enet2; 19*724ba675SRob Herring rtc1 = &ftm_alarm0; 20*724ba675SRob Herring serial0 = &lpuart0; 21*724ba675SRob Herring serial1 = &lpuart1; 22*724ba675SRob Herring serial2 = &lpuart2; 23*724ba675SRob Herring serial3 = &lpuart3; 24*724ba675SRob Herring serial4 = &lpuart4; 25*724ba675SRob Herring serial5 = &lpuart5; 26*724ba675SRob Herring sysclk = &sysclk; 27*724ba675SRob Herring }; 28*724ba675SRob Herring 29*724ba675SRob Herring cpus { 30*724ba675SRob Herring #address-cells = <1>; 31*724ba675SRob Herring #size-cells = <0>; 32*724ba675SRob Herring 33*724ba675SRob Herring cpu0: cpu@f00 { 34*724ba675SRob Herring compatible = "arm,cortex-a7"; 35*724ba675SRob Herring device_type = "cpu"; 36*724ba675SRob Herring reg = <0xf00>; 37*724ba675SRob Herring clocks = <&clockgen 1 0>; 38*724ba675SRob Herring #cooling-cells = <2>; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring cpu1: cpu@f01 { 42*724ba675SRob Herring compatible = "arm,cortex-a7"; 43*724ba675SRob Herring device_type = "cpu"; 44*724ba675SRob Herring reg = <0xf01>; 45*724ba675SRob Herring clocks = <&clockgen 1 0>; 46*724ba675SRob Herring #cooling-cells = <2>; 47*724ba675SRob Herring }; 48*724ba675SRob Herring }; 49*724ba675SRob Herring 50*724ba675SRob Herring memory@0 { 51*724ba675SRob Herring device_type = "memory"; 52*724ba675SRob Herring reg = <0x0 0x0 0x0 0x0>; 53*724ba675SRob Herring }; 54*724ba675SRob Herring 55*724ba675SRob Herring sysclk: sysclk { 56*724ba675SRob Herring compatible = "fixed-clock"; 57*724ba675SRob Herring #clock-cells = <0>; 58*724ba675SRob Herring clock-frequency = <100000000>; 59*724ba675SRob Herring clock-output-names = "sysclk"; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring timer { 63*724ba675SRob Herring compatible = "arm,armv7-timer"; 64*724ba675SRob Herring interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 65*724ba675SRob Herring <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 66*724ba675SRob Herring <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 67*724ba675SRob Herring <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 68*724ba675SRob Herring }; 69*724ba675SRob Herring 70*724ba675SRob Herring pmu { 71*724ba675SRob Herring compatible = "arm,cortex-a7-pmu"; 72*724ba675SRob Herring interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 73*724ba675SRob Herring <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 74*724ba675SRob Herring interrupt-affinity = <&cpu0>, <&cpu1>; 75*724ba675SRob Herring }; 76*724ba675SRob Herring 77*724ba675SRob Herring reboot { 78*724ba675SRob Herring compatible = "syscon-reboot"; 79*724ba675SRob Herring regmap = <&dcfg>; 80*724ba675SRob Herring offset = <0xb0>; 81*724ba675SRob Herring mask = <0x02>; 82*724ba675SRob Herring }; 83*724ba675SRob Herring 84*724ba675SRob Herring soc { 85*724ba675SRob Herring compatible = "simple-bus"; 86*724ba675SRob Herring #address-cells = <2>; 87*724ba675SRob Herring #size-cells = <2>; 88*724ba675SRob Herring device_type = "soc"; 89*724ba675SRob Herring interrupt-parent = <&gic>; 90*724ba675SRob Herring ranges; 91*724ba675SRob Herring 92*724ba675SRob Herring ddr: memory-controller@1080000 { 93*724ba675SRob Herring compatible = "fsl,qoriq-memory-controller"; 94*724ba675SRob Herring reg = <0x0 0x1080000 0x0 0x1000>; 95*724ba675SRob Herring interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 96*724ba675SRob Herring big-endian; 97*724ba675SRob Herring }; 98*724ba675SRob Herring 99*724ba675SRob Herring gic: interrupt-controller@1400000 { 100*724ba675SRob Herring compatible = "arm,gic-400", "arm,cortex-a7-gic"; 101*724ba675SRob Herring #interrupt-cells = <3>; 102*724ba675SRob Herring interrupt-controller; 103*724ba675SRob Herring reg = <0x0 0x1401000 0x0 0x1000>, 104*724ba675SRob Herring <0x0 0x1402000 0x0 0x2000>, 105*724ba675SRob Herring <0x0 0x1404000 0x0 0x2000>, 106*724ba675SRob Herring <0x0 0x1406000 0x0 0x2000>; 107*724ba675SRob Herring interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 108*724ba675SRob Herring 109*724ba675SRob Herring }; 110*724ba675SRob Herring 111*724ba675SRob Herring msi1: msi-controller@1570e00 { 112*724ba675SRob Herring compatible = "fsl,ls1021a-msi"; 113*724ba675SRob Herring reg = <0x0 0x1570e00 0x0 0x8>; 114*724ba675SRob Herring msi-controller; 115*724ba675SRob Herring interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 116*724ba675SRob Herring }; 117*724ba675SRob Herring 118*724ba675SRob Herring msi2: msi-controller@1570e08 { 119*724ba675SRob Herring compatible = "fsl,ls1021a-msi"; 120*724ba675SRob Herring reg = <0x0 0x1570e08 0x0 0x8>; 121*724ba675SRob Herring msi-controller; 122*724ba675SRob Herring interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 123*724ba675SRob Herring }; 124*724ba675SRob Herring 125*724ba675SRob Herring ifc: memory-controller@1530000 { 126*724ba675SRob Herring compatible = "fsl,ifc"; 127*724ba675SRob Herring reg = <0x0 0x1530000 0x0 0x10000>; 128*724ba675SRob Herring interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 129*724ba675SRob Herring status = "disabled"; 130*724ba675SRob Herring }; 131*724ba675SRob Herring 132*724ba675SRob Herring sfp: efuse@1e80000 { 133*724ba675SRob Herring compatible = "fsl,ls1021a-sfp"; 134*724ba675SRob Herring reg = <0x0 0x1e80000 0x0 0x10000>; 135*724ba675SRob Herring clocks = <&clockgen 4 3>; 136*724ba675SRob Herring clock-names = "sfp"; 137*724ba675SRob Herring }; 138*724ba675SRob Herring 139*724ba675SRob Herring dcfg: dcfg@1ee0000 { 140*724ba675SRob Herring compatible = "fsl,ls1021a-dcfg", "syscon"; 141*724ba675SRob Herring reg = <0x0 0x1ee0000 0x0 0x1000>; 142*724ba675SRob Herring big-endian; 143*724ba675SRob Herring }; 144*724ba675SRob Herring 145*724ba675SRob Herring qspi: spi@1550000 { 146*724ba675SRob Herring compatible = "fsl,ls1021a-qspi"; 147*724ba675SRob Herring #address-cells = <1>; 148*724ba675SRob Herring #size-cells = <0>; 149*724ba675SRob Herring reg = <0x0 0x1550000 0x0 0x10000>, 150*724ba675SRob Herring <0x0 0x40000000 0x0 0x20000000>; 151*724ba675SRob Herring reg-names = "QuadSPI", "QuadSPI-memory"; 152*724ba675SRob Herring interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 153*724ba675SRob Herring clock-names = "qspi_en", "qspi"; 154*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>; 155*724ba675SRob Herring status = "disabled"; 156*724ba675SRob Herring }; 157*724ba675SRob Herring 158*724ba675SRob Herring esdhc: esdhc@1560000 { 159*724ba675SRob Herring compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 160*724ba675SRob Herring reg = <0x0 0x1560000 0x0 0x10000>; 161*724ba675SRob Herring interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 162*724ba675SRob Herring clock-frequency = <0>; 163*724ba675SRob Herring voltage-ranges = <1800 1800 3300 3300>; 164*724ba675SRob Herring sdhci,auto-cmd12; 165*724ba675SRob Herring big-endian; 166*724ba675SRob Herring bus-width = <4>; 167*724ba675SRob Herring status = "disabled"; 168*724ba675SRob Herring }; 169*724ba675SRob Herring 170*724ba675SRob Herring sata: sata@3200000 { 171*724ba675SRob Herring compatible = "fsl,ls1021a-ahci"; 172*724ba675SRob Herring reg = <0x0 0x3200000 0x0 0x10000>, 173*724ba675SRob Herring <0x0 0x20220520 0x0 0x4>; 174*724ba675SRob Herring reg-names = "ahci", "sata-ecc"; 175*724ba675SRob Herring interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 176*724ba675SRob Herring clocks = <&clockgen 4 1>; 177*724ba675SRob Herring dma-coherent; 178*724ba675SRob Herring status = "disabled"; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring scfg: scfg@1570000 { 182*724ba675SRob Herring compatible = "fsl,ls1021a-scfg", "syscon"; 183*724ba675SRob Herring reg = <0x0 0x1570000 0x0 0x10000>; 184*724ba675SRob Herring big-endian; 185*724ba675SRob Herring #address-cells = <1>; 186*724ba675SRob Herring #size-cells = <1>; 187*724ba675SRob Herring ranges = <0x0 0x0 0x1570000 0x10000>; 188*724ba675SRob Herring 189*724ba675SRob Herring extirq: interrupt-controller@1ac { 190*724ba675SRob Herring compatible = "fsl,ls1021a-extirq"; 191*724ba675SRob Herring #interrupt-cells = <2>; 192*724ba675SRob Herring #address-cells = <0>; 193*724ba675SRob Herring interrupt-controller; 194*724ba675SRob Herring reg = <0x1ac 4>; 195*724ba675SRob Herring interrupt-map = 196*724ba675SRob Herring <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 197*724ba675SRob Herring <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 198*724ba675SRob Herring <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 199*724ba675SRob Herring <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 200*724ba675SRob Herring <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 201*724ba675SRob Herring <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 202*724ba675SRob Herring interrupt-map-mask = <0x7 0x0>; 203*724ba675SRob Herring }; 204*724ba675SRob Herring }; 205*724ba675SRob Herring 206*724ba675SRob Herring crypto: crypto@1700000 { 207*724ba675SRob Herring compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 208*724ba675SRob Herring fsl,sec-era = <7>; 209*724ba675SRob Herring #address-cells = <1>; 210*724ba675SRob Herring #size-cells = <1>; 211*724ba675SRob Herring reg = <0x0 0x1700000 0x0 0x100000>; 212*724ba675SRob Herring ranges = <0x0 0x0 0x1700000 0x100000>; 213*724ba675SRob Herring interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 214*724ba675SRob Herring dma-coherent; 215*724ba675SRob Herring 216*724ba675SRob Herring sec_jr0: jr@10000 { 217*724ba675SRob Herring compatible = "fsl,sec-v5.0-job-ring", 218*724ba675SRob Herring "fsl,sec-v4.0-job-ring"; 219*724ba675SRob Herring reg = <0x10000 0x10000>; 220*724ba675SRob Herring interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 221*724ba675SRob Herring }; 222*724ba675SRob Herring 223*724ba675SRob Herring sec_jr1: jr@20000 { 224*724ba675SRob Herring compatible = "fsl,sec-v5.0-job-ring", 225*724ba675SRob Herring "fsl,sec-v4.0-job-ring"; 226*724ba675SRob Herring reg = <0x20000 0x10000>; 227*724ba675SRob Herring interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 228*724ba675SRob Herring }; 229*724ba675SRob Herring 230*724ba675SRob Herring sec_jr2: jr@30000 { 231*724ba675SRob Herring compatible = "fsl,sec-v5.0-job-ring", 232*724ba675SRob Herring "fsl,sec-v4.0-job-ring"; 233*724ba675SRob Herring reg = <0x30000 0x10000>; 234*724ba675SRob Herring interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 235*724ba675SRob Herring }; 236*724ba675SRob Herring 237*724ba675SRob Herring sec_jr3: jr@40000 { 238*724ba675SRob Herring compatible = "fsl,sec-v5.0-job-ring", 239*724ba675SRob Herring "fsl,sec-v4.0-job-ring"; 240*724ba675SRob Herring reg = <0x40000 0x10000>; 241*724ba675SRob Herring interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 242*724ba675SRob Herring }; 243*724ba675SRob Herring 244*724ba675SRob Herring }; 245*724ba675SRob Herring 246*724ba675SRob Herring clockgen: clocking@1ee1000 { 247*724ba675SRob Herring compatible = "fsl,ls1021a-clockgen"; 248*724ba675SRob Herring reg = <0x0 0x1ee1000 0x0 0x1000>; 249*724ba675SRob Herring #clock-cells = <2>; 250*724ba675SRob Herring clocks = <&sysclk>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring tmu: tmu@1f00000 { 254*724ba675SRob Herring compatible = "fsl,qoriq-tmu"; 255*724ba675SRob Herring reg = <0x0 0x1f00000 0x0 0x10000>; 256*724ba675SRob Herring interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 257*724ba675SRob Herring fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; 258*724ba675SRob Herring fsl,tmu-calibration = <0x00000000 0x00000020>, 259*724ba675SRob Herring <0x00000001 0x00000024>, 260*724ba675SRob Herring <0x00000002 0x0000002a>, 261*724ba675SRob Herring <0x00000003 0x00000032>, 262*724ba675SRob Herring <0x00000004 0x00000038>, 263*724ba675SRob Herring <0x00000005 0x0000003e>, 264*724ba675SRob Herring <0x00000006 0x00000043>, 265*724ba675SRob Herring <0x00000007 0x0000004a>, 266*724ba675SRob Herring <0x00000008 0x00000050>, 267*724ba675SRob Herring <0x00000009 0x00000059>, 268*724ba675SRob Herring <0x0000000a 0x0000005f>, 269*724ba675SRob Herring <0x0000000b 0x00000066>, 270*724ba675SRob Herring 271*724ba675SRob Herring <0x00010000 0x00000023>, 272*724ba675SRob Herring <0x00010001 0x0000002b>, 273*724ba675SRob Herring <0x00010002 0x00000033>, 274*724ba675SRob Herring <0x00010003 0x0000003a>, 275*724ba675SRob Herring <0x00010004 0x00000042>, 276*724ba675SRob Herring <0x00010005 0x0000004a>, 277*724ba675SRob Herring <0x00010006 0x00000054>, 278*724ba675SRob Herring <0x00010007 0x0000005c>, 279*724ba675SRob Herring <0x00010008 0x00000065>, 280*724ba675SRob Herring <0x00010009 0x0000006f>, 281*724ba675SRob Herring 282*724ba675SRob Herring <0x00020000 0x00000029>, 283*724ba675SRob Herring <0x00020001 0x00000033>, 284*724ba675SRob Herring <0x00020002 0x0000003d>, 285*724ba675SRob Herring <0x00020003 0x00000048>, 286*724ba675SRob Herring <0x00020004 0x00000054>, 287*724ba675SRob Herring <0x00020005 0x00000060>, 288*724ba675SRob Herring <0x00020006 0x0000006c>, 289*724ba675SRob Herring 290*724ba675SRob Herring <0x00030000 0x00000025>, 291*724ba675SRob Herring <0x00030001 0x00000033>, 292*724ba675SRob Herring <0x00030002 0x00000043>, 293*724ba675SRob Herring <0x00030003 0x00000055>; 294*724ba675SRob Herring #thermal-sensor-cells = <1>; 295*724ba675SRob Herring }; 296*724ba675SRob Herring 297*724ba675SRob Herring dspi0: spi@2100000 { 298*724ba675SRob Herring compatible = "fsl,ls1021a-v1.0-dspi"; 299*724ba675SRob Herring #address-cells = <1>; 300*724ba675SRob Herring #size-cells = <0>; 301*724ba675SRob Herring reg = <0x0 0x2100000 0x0 0x10000>; 302*724ba675SRob Herring interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 303*724ba675SRob Herring clock-names = "dspi"; 304*724ba675SRob Herring clocks = <&clockgen 4 1>; 305*724ba675SRob Herring spi-num-chipselects = <6>; 306*724ba675SRob Herring big-endian; 307*724ba675SRob Herring status = "disabled"; 308*724ba675SRob Herring }; 309*724ba675SRob Herring 310*724ba675SRob Herring dspi1: spi@2110000 { 311*724ba675SRob Herring compatible = "fsl,ls1021a-v1.0-dspi"; 312*724ba675SRob Herring #address-cells = <1>; 313*724ba675SRob Herring #size-cells = <0>; 314*724ba675SRob Herring reg = <0x0 0x2110000 0x0 0x10000>; 315*724ba675SRob Herring interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 316*724ba675SRob Herring clock-names = "dspi"; 317*724ba675SRob Herring clocks = <&clockgen 4 1>; 318*724ba675SRob Herring spi-num-chipselects = <6>; 319*724ba675SRob Herring big-endian; 320*724ba675SRob Herring status = "disabled"; 321*724ba675SRob Herring }; 322*724ba675SRob Herring 323*724ba675SRob Herring i2c0: i2c@2180000 { 324*724ba675SRob Herring compatible = "fsl,vf610-i2c"; 325*724ba675SRob Herring #address-cells = <1>; 326*724ba675SRob Herring #size-cells = <0>; 327*724ba675SRob Herring reg = <0x0 0x2180000 0x0 0x10000>; 328*724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 329*724ba675SRob Herring clocks = <&clockgen 4 1>; 330*724ba675SRob Herring dma-names = "rx", "tx"; 331*724ba675SRob Herring dmas = <&edma0 1 38>, <&edma0 1 39>; 332*724ba675SRob Herring status = "disabled"; 333*724ba675SRob Herring }; 334*724ba675SRob Herring 335*724ba675SRob Herring i2c1: i2c@2190000 { 336*724ba675SRob Herring compatible = "fsl,vf610-i2c"; 337*724ba675SRob Herring #address-cells = <1>; 338*724ba675SRob Herring #size-cells = <0>; 339*724ba675SRob Herring reg = <0x0 0x2190000 0x0 0x10000>; 340*724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 341*724ba675SRob Herring clocks = <&clockgen 4 1>; 342*724ba675SRob Herring dma-names = "rx", "tx"; 343*724ba675SRob Herring dmas = <&edma0 1 36>, <&edma0 1 37>; 344*724ba675SRob Herring status = "disabled"; 345*724ba675SRob Herring }; 346*724ba675SRob Herring 347*724ba675SRob Herring i2c2: i2c@21a0000 { 348*724ba675SRob Herring compatible = "fsl,vf610-i2c"; 349*724ba675SRob Herring #address-cells = <1>; 350*724ba675SRob Herring #size-cells = <0>; 351*724ba675SRob Herring reg = <0x0 0x21a0000 0x0 0x10000>; 352*724ba675SRob Herring interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 353*724ba675SRob Herring clocks = <&clockgen 4 1>; 354*724ba675SRob Herring dma-names = "rx", "tx"; 355*724ba675SRob Herring dmas = <&edma0 1 34>, <&edma0 1 35>; 356*724ba675SRob Herring status = "disabled"; 357*724ba675SRob Herring }; 358*724ba675SRob Herring 359*724ba675SRob Herring uart0: serial@21c0500 { 360*724ba675SRob Herring compatible = "fsl,16550-FIFO64", "ns16550a"; 361*724ba675SRob Herring reg = <0x0 0x21c0500 0x0 0x100>; 362*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 363*724ba675SRob Herring clock-frequency = <0>; 364*724ba675SRob Herring fifo-size = <15>; 365*724ba675SRob Herring status = "disabled"; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring uart1: serial@21c0600 { 369*724ba675SRob Herring compatible = "fsl,16550-FIFO64", "ns16550a"; 370*724ba675SRob Herring reg = <0x0 0x21c0600 0x0 0x100>; 371*724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 372*724ba675SRob Herring clock-frequency = <0>; 373*724ba675SRob Herring fifo-size = <15>; 374*724ba675SRob Herring status = "disabled"; 375*724ba675SRob Herring }; 376*724ba675SRob Herring 377*724ba675SRob Herring uart2: serial@21d0500 { 378*724ba675SRob Herring compatible = "fsl,16550-FIFO64", "ns16550a"; 379*724ba675SRob Herring reg = <0x0 0x21d0500 0x0 0x100>; 380*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 381*724ba675SRob Herring clock-frequency = <0>; 382*724ba675SRob Herring fifo-size = <15>; 383*724ba675SRob Herring status = "disabled"; 384*724ba675SRob Herring }; 385*724ba675SRob Herring 386*724ba675SRob Herring uart3: serial@21d0600 { 387*724ba675SRob Herring compatible = "fsl,16550-FIFO64", "ns16550a"; 388*724ba675SRob Herring reg = <0x0 0x21d0600 0x0 0x100>; 389*724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 390*724ba675SRob Herring clock-frequency = <0>; 391*724ba675SRob Herring fifo-size = <15>; 392*724ba675SRob Herring status = "disabled"; 393*724ba675SRob Herring }; 394*724ba675SRob Herring 395*724ba675SRob Herring counter0: counter@29d0000 { 396*724ba675SRob Herring compatible = "fsl,ftm-quaddec"; 397*724ba675SRob Herring reg = <0x0 0x29d0000 0x0 0x10000>; 398*724ba675SRob Herring big-endian; 399*724ba675SRob Herring status = "disabled"; 400*724ba675SRob Herring }; 401*724ba675SRob Herring 402*724ba675SRob Herring counter1: counter@29e0000 { 403*724ba675SRob Herring compatible = "fsl,ftm-quaddec"; 404*724ba675SRob Herring reg = <0x0 0x29e0000 0x0 0x10000>; 405*724ba675SRob Herring big-endian; 406*724ba675SRob Herring status = "disabled"; 407*724ba675SRob Herring }; 408*724ba675SRob Herring 409*724ba675SRob Herring counter2: counter@29f0000 { 410*724ba675SRob Herring compatible = "fsl,ftm-quaddec"; 411*724ba675SRob Herring reg = <0x0 0x29f0000 0x0 0x10000>; 412*724ba675SRob Herring big-endian; 413*724ba675SRob Herring status = "disabled"; 414*724ba675SRob Herring }; 415*724ba675SRob Herring 416*724ba675SRob Herring counter3: counter@2a00000 { 417*724ba675SRob Herring compatible = "fsl,ftm-quaddec"; 418*724ba675SRob Herring reg = <0x0 0x2a00000 0x0 0x10000>; 419*724ba675SRob Herring big-endian; 420*724ba675SRob Herring status = "disabled"; 421*724ba675SRob Herring }; 422*724ba675SRob Herring 423*724ba675SRob Herring gpio0: gpio@2300000 { 424*724ba675SRob Herring compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 425*724ba675SRob Herring reg = <0x0 0x2300000 0x0 0x10000>; 426*724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 427*724ba675SRob Herring gpio-controller; 428*724ba675SRob Herring #gpio-cells = <2>; 429*724ba675SRob Herring interrupt-controller; 430*724ba675SRob Herring #interrupt-cells = <2>; 431*724ba675SRob Herring }; 432*724ba675SRob Herring 433*724ba675SRob Herring gpio1: gpio@2310000 { 434*724ba675SRob Herring compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 435*724ba675SRob Herring reg = <0x0 0x2310000 0x0 0x10000>; 436*724ba675SRob Herring interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 437*724ba675SRob Herring gpio-controller; 438*724ba675SRob Herring #gpio-cells = <2>; 439*724ba675SRob Herring interrupt-controller; 440*724ba675SRob Herring #interrupt-cells = <2>; 441*724ba675SRob Herring }; 442*724ba675SRob Herring 443*724ba675SRob Herring gpio2: gpio@2320000 { 444*724ba675SRob Herring compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 445*724ba675SRob Herring reg = <0x0 0x2320000 0x0 0x10000>; 446*724ba675SRob Herring interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 447*724ba675SRob Herring gpio-controller; 448*724ba675SRob Herring #gpio-cells = <2>; 449*724ba675SRob Herring interrupt-controller; 450*724ba675SRob Herring #interrupt-cells = <2>; 451*724ba675SRob Herring }; 452*724ba675SRob Herring 453*724ba675SRob Herring gpio3: gpio@2330000 { 454*724ba675SRob Herring compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 455*724ba675SRob Herring reg = <0x0 0x2330000 0x0 0x10000>; 456*724ba675SRob Herring interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 457*724ba675SRob Herring gpio-controller; 458*724ba675SRob Herring #gpio-cells = <2>; 459*724ba675SRob Herring interrupt-controller; 460*724ba675SRob Herring #interrupt-cells = <2>; 461*724ba675SRob Herring }; 462*724ba675SRob Herring 463*724ba675SRob Herring lpuart0: serial@2950000 { 464*724ba675SRob Herring compatible = "fsl,ls1021a-lpuart"; 465*724ba675SRob Herring reg = <0x0 0x2950000 0x0 0x1000>; 466*724ba675SRob Herring interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 467*724ba675SRob Herring clocks = <&sysclk>; 468*724ba675SRob Herring clock-names = "ipg"; 469*724ba675SRob Herring status = "disabled"; 470*724ba675SRob Herring }; 471*724ba675SRob Herring 472*724ba675SRob Herring lpuart1: serial@2960000 { 473*724ba675SRob Herring compatible = "fsl,ls1021a-lpuart"; 474*724ba675SRob Herring reg = <0x0 0x2960000 0x0 0x1000>; 475*724ba675SRob Herring interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 476*724ba675SRob Herring clocks = <&clockgen 4 1>; 477*724ba675SRob Herring clock-names = "ipg"; 478*724ba675SRob Herring status = "disabled"; 479*724ba675SRob Herring }; 480*724ba675SRob Herring 481*724ba675SRob Herring lpuart2: serial@2970000 { 482*724ba675SRob Herring compatible = "fsl,ls1021a-lpuart"; 483*724ba675SRob Herring reg = <0x0 0x2970000 0x0 0x1000>; 484*724ba675SRob Herring interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 485*724ba675SRob Herring clocks = <&clockgen 4 1>; 486*724ba675SRob Herring clock-names = "ipg"; 487*724ba675SRob Herring status = "disabled"; 488*724ba675SRob Herring }; 489*724ba675SRob Herring 490*724ba675SRob Herring lpuart3: serial@2980000 { 491*724ba675SRob Herring compatible = "fsl,ls1021a-lpuart"; 492*724ba675SRob Herring reg = <0x0 0x2980000 0x0 0x1000>; 493*724ba675SRob Herring interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 494*724ba675SRob Herring clocks = <&clockgen 4 1>; 495*724ba675SRob Herring clock-names = "ipg"; 496*724ba675SRob Herring status = "disabled"; 497*724ba675SRob Herring }; 498*724ba675SRob Herring 499*724ba675SRob Herring lpuart4: serial@2990000 { 500*724ba675SRob Herring compatible = "fsl,ls1021a-lpuart"; 501*724ba675SRob Herring reg = <0x0 0x2990000 0x0 0x1000>; 502*724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 503*724ba675SRob Herring clocks = <&clockgen 4 1>; 504*724ba675SRob Herring clock-names = "ipg"; 505*724ba675SRob Herring status = "disabled"; 506*724ba675SRob Herring }; 507*724ba675SRob Herring 508*724ba675SRob Herring lpuart5: serial@29a0000 { 509*724ba675SRob Herring compatible = "fsl,ls1021a-lpuart"; 510*724ba675SRob Herring reg = <0x0 0x29a0000 0x0 0x1000>; 511*724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 512*724ba675SRob Herring clocks = <&clockgen 4 1>; 513*724ba675SRob Herring clock-names = "ipg"; 514*724ba675SRob Herring status = "disabled"; 515*724ba675SRob Herring }; 516*724ba675SRob Herring 517*724ba675SRob Herring pwm0: pwm@29d0000 { 518*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 519*724ba675SRob Herring #pwm-cells = <3>; 520*724ba675SRob Herring reg = <0x0 0x29d0000 0x0 0x10000>; 521*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 522*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 523*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 524*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 525*724ba675SRob Herring big-endian; 526*724ba675SRob Herring status = "disabled"; 527*724ba675SRob Herring }; 528*724ba675SRob Herring 529*724ba675SRob Herring pwm1: pwm@29e0000 { 530*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 531*724ba675SRob Herring #pwm-cells = <3>; 532*724ba675SRob Herring reg = <0x0 0x29e0000 0x0 0x10000>; 533*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 534*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 535*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 536*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 537*724ba675SRob Herring big-endian; 538*724ba675SRob Herring status = "disabled"; 539*724ba675SRob Herring }; 540*724ba675SRob Herring 541*724ba675SRob Herring pwm2: pwm@29f0000 { 542*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 543*724ba675SRob Herring #pwm-cells = <3>; 544*724ba675SRob Herring reg = <0x0 0x29f0000 0x0 0x10000>; 545*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 546*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 547*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 548*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 549*724ba675SRob Herring big-endian; 550*724ba675SRob Herring status = "disabled"; 551*724ba675SRob Herring }; 552*724ba675SRob Herring 553*724ba675SRob Herring pwm3: pwm@2a00000 { 554*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 555*724ba675SRob Herring #pwm-cells = <3>; 556*724ba675SRob Herring reg = <0x0 0x2a00000 0x0 0x10000>; 557*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 558*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 559*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 560*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 561*724ba675SRob Herring big-endian; 562*724ba675SRob Herring status = "disabled"; 563*724ba675SRob Herring }; 564*724ba675SRob Herring 565*724ba675SRob Herring pwm4: pwm@2a10000 { 566*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 567*724ba675SRob Herring #pwm-cells = <3>; 568*724ba675SRob Herring reg = <0x0 0x2a10000 0x0 0x10000>; 569*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 570*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 571*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 572*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 573*724ba675SRob Herring big-endian; 574*724ba675SRob Herring status = "disabled"; 575*724ba675SRob Herring }; 576*724ba675SRob Herring 577*724ba675SRob Herring pwm5: pwm@2a20000 { 578*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 579*724ba675SRob Herring #pwm-cells = <3>; 580*724ba675SRob Herring reg = <0x0 0x2a20000 0x0 0x10000>; 581*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 582*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 583*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 584*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 585*724ba675SRob Herring big-endian; 586*724ba675SRob Herring status = "disabled"; 587*724ba675SRob Herring }; 588*724ba675SRob Herring 589*724ba675SRob Herring pwm6: pwm@2a30000 { 590*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 591*724ba675SRob Herring #pwm-cells = <3>; 592*724ba675SRob Herring reg = <0x0 0x2a30000 0x0 0x10000>; 593*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 594*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 595*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 596*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 597*724ba675SRob Herring big-endian; 598*724ba675SRob Herring status = "disabled"; 599*724ba675SRob Herring }; 600*724ba675SRob Herring 601*724ba675SRob Herring pwm7: pwm@2a40000 { 602*724ba675SRob Herring compatible = "fsl,vf610-ftm-pwm"; 603*724ba675SRob Herring #pwm-cells = <3>; 604*724ba675SRob Herring reg = <0x0 0x2a40000 0x0 0x10000>; 605*724ba675SRob Herring clock-names = "ftm_sys", "ftm_ext", 606*724ba675SRob Herring "ftm_fix", "ftm_cnt_clk_en"; 607*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 608*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 609*724ba675SRob Herring big-endian; 610*724ba675SRob Herring status = "disabled"; 611*724ba675SRob Herring }; 612*724ba675SRob Herring 613*724ba675SRob Herring wdog0: watchdog@2ad0000 { 614*724ba675SRob Herring compatible = "fsl,imx21-wdt"; 615*724ba675SRob Herring reg = <0x0 0x2ad0000 0x0 0x10000>; 616*724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 617*724ba675SRob Herring clocks = <&clockgen 4 1>; 618*724ba675SRob Herring clock-names = "wdog-en"; 619*724ba675SRob Herring big-endian; 620*724ba675SRob Herring }; 621*724ba675SRob Herring 622*724ba675SRob Herring sai1: sai@2b50000 { 623*724ba675SRob Herring #sound-dai-cells = <0>; 624*724ba675SRob Herring compatible = "fsl,vf610-sai"; 625*724ba675SRob Herring reg = <0x0 0x2b50000 0x0 0x10000>; 626*724ba675SRob Herring interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 627*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 628*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 629*724ba675SRob Herring clock-names = "bus", "mclk1", "mclk2", "mclk3"; 630*724ba675SRob Herring dma-names = "tx", "rx"; 631*724ba675SRob Herring dmas = <&edma0 1 47>, 632*724ba675SRob Herring <&edma0 1 46>; 633*724ba675SRob Herring status = "disabled"; 634*724ba675SRob Herring }; 635*724ba675SRob Herring 636*724ba675SRob Herring sai2: sai@2b60000 { 637*724ba675SRob Herring #sound-dai-cells = <0>; 638*724ba675SRob Herring compatible = "fsl,vf610-sai"; 639*724ba675SRob Herring reg = <0x0 0x2b60000 0x0 0x10000>; 640*724ba675SRob Herring interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 641*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>, 642*724ba675SRob Herring <&clockgen 4 1>, <&clockgen 4 1>; 643*724ba675SRob Herring clock-names = "bus", "mclk1", "mclk2", "mclk3"; 644*724ba675SRob Herring dma-names = "tx", "rx"; 645*724ba675SRob Herring dmas = <&edma0 1 45>, 646*724ba675SRob Herring <&edma0 1 44>; 647*724ba675SRob Herring status = "disabled"; 648*724ba675SRob Herring }; 649*724ba675SRob Herring 650*724ba675SRob Herring edma0: dma-controller@2c00000 { 651*724ba675SRob Herring #dma-cells = <2>; 652*724ba675SRob Herring compatible = "fsl,vf610-edma"; 653*724ba675SRob Herring reg = <0x0 0x2c00000 0x0 0x10000>, 654*724ba675SRob Herring <0x0 0x2c10000 0x0 0x10000>, 655*724ba675SRob Herring <0x0 0x2c20000 0x0 0x10000>; 656*724ba675SRob Herring interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 657*724ba675SRob Herring <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 658*724ba675SRob Herring interrupt-names = "edma-tx", "edma-err"; 659*724ba675SRob Herring dma-channels = <32>; 660*724ba675SRob Herring big-endian; 661*724ba675SRob Herring clock-names = "dmamux0", "dmamux1"; 662*724ba675SRob Herring clocks = <&clockgen 4 1>, 663*724ba675SRob Herring <&clockgen 4 1>; 664*724ba675SRob Herring }; 665*724ba675SRob Herring 666*724ba675SRob Herring dcu: dcu@2ce0000 { 667*724ba675SRob Herring compatible = "fsl,ls1021a-dcu"; 668*724ba675SRob Herring reg = <0x0 0x2ce0000 0x0 0x10000>; 669*724ba675SRob Herring interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 670*724ba675SRob Herring clocks = <&clockgen 4 0>, 671*724ba675SRob Herring <&clockgen 4 0>; 672*724ba675SRob Herring clock-names = "dcu", "pix"; 673*724ba675SRob Herring big-endian; 674*724ba675SRob Herring status = "disabled"; 675*724ba675SRob Herring }; 676*724ba675SRob Herring 677*724ba675SRob Herring mdio0: mdio@2d24000 { 678*724ba675SRob Herring compatible = "gianfar"; 679*724ba675SRob Herring device_type = "mdio"; 680*724ba675SRob Herring #address-cells = <1>; 681*724ba675SRob Herring #size-cells = <0>; 682*724ba675SRob Herring reg = <0x0 0x2d24000 0x0 0x4000>, 683*724ba675SRob Herring <0x0 0x2d10030 0x0 0x4>; 684*724ba675SRob Herring }; 685*724ba675SRob Herring 686*724ba675SRob Herring mdio1: mdio@2d64000 { 687*724ba675SRob Herring compatible = "gianfar"; 688*724ba675SRob Herring device_type = "mdio"; 689*724ba675SRob Herring #address-cells = <1>; 690*724ba675SRob Herring #size-cells = <0>; 691*724ba675SRob Herring reg = <0x0 0x2d64000 0x0 0x4000>, 692*724ba675SRob Herring <0x0 0x2d50030 0x0 0x4>; 693*724ba675SRob Herring }; 694*724ba675SRob Herring 695*724ba675SRob Herring ptp_clock@2d10e00 { 696*724ba675SRob Herring compatible = "fsl,etsec-ptp"; 697*724ba675SRob Herring reg = <0x0 0x2d10e00 0x0 0xb0>; 698*724ba675SRob Herring interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 699*724ba675SRob Herring fsl,tclk-period = <5>; 700*724ba675SRob Herring fsl,tmr-prsc = <2>; 701*724ba675SRob Herring fsl,tmr-add = <0xaaaaaaab>; 702*724ba675SRob Herring fsl,tmr-fiper1 = <999999995>; 703*724ba675SRob Herring fsl,tmr-fiper2 = <999999995>; 704*724ba675SRob Herring fsl,max-adj = <499999999>; 705*724ba675SRob Herring fsl,extts-fifo; 706*724ba675SRob Herring }; 707*724ba675SRob Herring 708*724ba675SRob Herring enet0: ethernet@2d10000 { 709*724ba675SRob Herring compatible = "fsl,etsec2"; 710*724ba675SRob Herring device_type = "network"; 711*724ba675SRob Herring #address-cells = <2>; 712*724ba675SRob Herring #size-cells = <2>; 713*724ba675SRob Herring interrupt-parent = <&gic>; 714*724ba675SRob Herring model = "eTSEC"; 715*724ba675SRob Herring fsl,magic-packet; 716*724ba675SRob Herring ranges; 717*724ba675SRob Herring dma-coherent; 718*724ba675SRob Herring 719*724ba675SRob Herring queue-group@2d10000 { 720*724ba675SRob Herring #address-cells = <2>; 721*724ba675SRob Herring #size-cells = <2>; 722*724ba675SRob Herring reg = <0x0 0x2d10000 0x0 0x1000>; 723*724ba675SRob Herring interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 724*724ba675SRob Herring <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 725*724ba675SRob Herring <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 726*724ba675SRob Herring }; 727*724ba675SRob Herring 728*724ba675SRob Herring queue-group@2d14000 { 729*724ba675SRob Herring #address-cells = <2>; 730*724ba675SRob Herring #size-cells = <2>; 731*724ba675SRob Herring reg = <0x0 0x2d14000 0x0 0x1000>; 732*724ba675SRob Herring interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 733*724ba675SRob Herring <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 734*724ba675SRob Herring <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 735*724ba675SRob Herring }; 736*724ba675SRob Herring }; 737*724ba675SRob Herring 738*724ba675SRob Herring enet1: ethernet@2d50000 { 739*724ba675SRob Herring compatible = "fsl,etsec2"; 740*724ba675SRob Herring device_type = "network"; 741*724ba675SRob Herring #address-cells = <2>; 742*724ba675SRob Herring #size-cells = <2>; 743*724ba675SRob Herring interrupt-parent = <&gic>; 744*724ba675SRob Herring model = "eTSEC"; 745*724ba675SRob Herring ranges; 746*724ba675SRob Herring dma-coherent; 747*724ba675SRob Herring 748*724ba675SRob Herring queue-group@2d50000 { 749*724ba675SRob Herring #address-cells = <2>; 750*724ba675SRob Herring #size-cells = <2>; 751*724ba675SRob Herring reg = <0x0 0x2d50000 0x0 0x1000>; 752*724ba675SRob Herring interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 753*724ba675SRob Herring <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 754*724ba675SRob Herring <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 755*724ba675SRob Herring }; 756*724ba675SRob Herring 757*724ba675SRob Herring queue-group@2d54000 { 758*724ba675SRob Herring #address-cells = <2>; 759*724ba675SRob Herring #size-cells = <2>; 760*724ba675SRob Herring reg = <0x0 0x2d54000 0x0 0x1000>; 761*724ba675SRob Herring interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 762*724ba675SRob Herring <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 763*724ba675SRob Herring <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 764*724ba675SRob Herring }; 765*724ba675SRob Herring }; 766*724ba675SRob Herring 767*724ba675SRob Herring enet2: ethernet@2d90000 { 768*724ba675SRob Herring compatible = "fsl,etsec2"; 769*724ba675SRob Herring device_type = "network"; 770*724ba675SRob Herring #address-cells = <2>; 771*724ba675SRob Herring #size-cells = <2>; 772*724ba675SRob Herring interrupt-parent = <&gic>; 773*724ba675SRob Herring model = "eTSEC"; 774*724ba675SRob Herring ranges; 775*724ba675SRob Herring dma-coherent; 776*724ba675SRob Herring 777*724ba675SRob Herring queue-group@2d90000 { 778*724ba675SRob Herring #address-cells = <2>; 779*724ba675SRob Herring #size-cells = <2>; 780*724ba675SRob Herring reg = <0x0 0x2d90000 0x0 0x1000>; 781*724ba675SRob Herring interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 782*724ba675SRob Herring <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 783*724ba675SRob Herring <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 784*724ba675SRob Herring }; 785*724ba675SRob Herring 786*724ba675SRob Herring queue-group@2d94000 { 787*724ba675SRob Herring #address-cells = <2>; 788*724ba675SRob Herring #size-cells = <2>; 789*724ba675SRob Herring reg = <0x0 0x2d94000 0x0 0x1000>; 790*724ba675SRob Herring interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 791*724ba675SRob Herring <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 792*724ba675SRob Herring <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 793*724ba675SRob Herring }; 794*724ba675SRob Herring }; 795*724ba675SRob Herring 796*724ba675SRob Herring usb2: usb@8600000 { 797*724ba675SRob Herring compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 798*724ba675SRob Herring reg = <0x0 0x8600000 0x0 0x1000>; 799*724ba675SRob Herring interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 800*724ba675SRob Herring dr_mode = "host"; 801*724ba675SRob Herring phy_type = "ulpi"; 802*724ba675SRob Herring }; 803*724ba675SRob Herring 804*724ba675SRob Herring usb3: usb@3100000 { 805*724ba675SRob Herring compatible = "snps,dwc3"; 806*724ba675SRob Herring reg = <0x0 0x3100000 0x0 0x10000>; 807*724ba675SRob Herring interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 808*724ba675SRob Herring dr_mode = "host"; 809*724ba675SRob Herring snps,quirk-frame-length-adjustment = <0x20>; 810*724ba675SRob Herring snps,dis_rxdet_inp3_quirk; 811*724ba675SRob Herring snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 812*724ba675SRob Herring }; 813*724ba675SRob Herring 814*724ba675SRob Herring pcie@3400000 { 815*724ba675SRob Herring compatible = "fsl,ls1021a-pcie"; 816*724ba675SRob Herring reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ 817*724ba675SRob Herring <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 818*724ba675SRob Herring reg-names = "regs", "config"; 819*724ba675SRob Herring interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 820*724ba675SRob Herring fsl,pcie-scfg = <&scfg 0>; 821*724ba675SRob Herring #address-cells = <3>; 822*724ba675SRob Herring #size-cells = <2>; 823*724ba675SRob Herring device_type = "pci"; 824*724ba675SRob Herring num-viewport = <6>; 825*724ba675SRob Herring bus-range = <0x0 0xff>; 826*724ba675SRob Herring ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */ 827*724ba675SRob Herring <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 828*724ba675SRob Herring msi-parent = <&msi1>, <&msi2>; 829*724ba675SRob Herring #interrupt-cells = <1>; 830*724ba675SRob Herring interrupt-map-mask = <0 0 0 7>; 831*724ba675SRob Herring interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 832*724ba675SRob Herring <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 833*724ba675SRob Herring <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 834*724ba675SRob Herring <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 835*724ba675SRob Herring status = "disabled"; 836*724ba675SRob Herring }; 837*724ba675SRob Herring 838*724ba675SRob Herring pcie@3500000 { 839*724ba675SRob Herring compatible = "fsl,ls1021a-pcie"; 840*724ba675SRob Herring reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ 841*724ba675SRob Herring <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 842*724ba675SRob Herring reg-names = "regs", "config"; 843*724ba675SRob Herring interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 844*724ba675SRob Herring fsl,pcie-scfg = <&scfg 1>; 845*724ba675SRob Herring #address-cells = <3>; 846*724ba675SRob Herring #size-cells = <2>; 847*724ba675SRob Herring device_type = "pci"; 848*724ba675SRob Herring num-viewport = <6>; 849*724ba675SRob Herring bus-range = <0x0 0xff>; 850*724ba675SRob Herring ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */ 851*724ba675SRob Herring <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 852*724ba675SRob Herring msi-parent = <&msi1>, <&msi2>; 853*724ba675SRob Herring #interrupt-cells = <1>; 854*724ba675SRob Herring interrupt-map-mask = <0 0 0 7>; 855*724ba675SRob Herring interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 856*724ba675SRob Herring <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 857*724ba675SRob Herring <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 858*724ba675SRob Herring <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 859*724ba675SRob Herring status = "disabled"; 860*724ba675SRob Herring }; 861*724ba675SRob Herring 862*724ba675SRob Herring can0: can@2a70000 { 863*724ba675SRob Herring compatible = "fsl,ls1021ar2-flexcan"; 864*724ba675SRob Herring reg = <0x0 0x2a70000 0x0 0x1000>; 865*724ba675SRob Herring interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 866*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>; 867*724ba675SRob Herring clock-names = "ipg", "per"; 868*724ba675SRob Herring big-endian; 869*724ba675SRob Herring status = "disabled"; 870*724ba675SRob Herring }; 871*724ba675SRob Herring 872*724ba675SRob Herring can1: can@2a80000 { 873*724ba675SRob Herring compatible = "fsl,ls1021ar2-flexcan"; 874*724ba675SRob Herring reg = <0x0 0x2a80000 0x0 0x1000>; 875*724ba675SRob Herring interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 876*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>; 877*724ba675SRob Herring clock-names = "ipg", "per"; 878*724ba675SRob Herring big-endian; 879*724ba675SRob Herring status = "disabled"; 880*724ba675SRob Herring }; 881*724ba675SRob Herring 882*724ba675SRob Herring can2: can@2a90000 { 883*724ba675SRob Herring compatible = "fsl,ls1021ar2-flexcan"; 884*724ba675SRob Herring reg = <0x0 0x2a90000 0x0 0x1000>; 885*724ba675SRob Herring interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 886*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>; 887*724ba675SRob Herring clock-names = "ipg", "per"; 888*724ba675SRob Herring big-endian; 889*724ba675SRob Herring status = "disabled"; 890*724ba675SRob Herring }; 891*724ba675SRob Herring 892*724ba675SRob Herring can3: can@2aa0000 { 893*724ba675SRob Herring compatible = "fsl,ls1021ar2-flexcan"; 894*724ba675SRob Herring reg = <0x0 0x2aa0000 0x0 0x1000>; 895*724ba675SRob Herring interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 896*724ba675SRob Herring clocks = <&clockgen 4 1>, <&clockgen 4 1>; 897*724ba675SRob Herring clock-names = "ipg", "per"; 898*724ba675SRob Herring big-endian; 899*724ba675SRob Herring status = "disabled"; 900*724ba675SRob Herring }; 901*724ba675SRob Herring 902*724ba675SRob Herring ocram1: sram@10000000 { 903*724ba675SRob Herring compatible = "mmio-sram"; 904*724ba675SRob Herring reg = <0x0 0x10000000 0x0 0x10000>; 905*724ba675SRob Herring #address-cells = <1>; 906*724ba675SRob Herring #size-cells = <1>; 907*724ba675SRob Herring ranges = <0x0 0x0 0x10000000 0x10000>; 908*724ba675SRob Herring }; 909*724ba675SRob Herring 910*724ba675SRob Herring ocram2: sram@10010000 { 911*724ba675SRob Herring compatible = "mmio-sram"; 912*724ba675SRob Herring reg = <0x0 0x10010000 0x0 0x10000>; 913*724ba675SRob Herring #address-cells = <1>; 914*724ba675SRob Herring #size-cells = <1>; 915*724ba675SRob Herring ranges = <0x0 0x0 0x10010000 0x10000>; 916*724ba675SRob Herring }; 917*724ba675SRob Herring 918*724ba675SRob Herring qdma: dma-controller@8390000 { 919*724ba675SRob Herring compatible = "fsl,ls1021a-qdma"; 920*724ba675SRob Herring reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 921*724ba675SRob Herring <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 922*724ba675SRob Herring <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 923*724ba675SRob Herring interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 924*724ba675SRob Herring <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 925*724ba675SRob Herring <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 926*724ba675SRob Herring interrupt-names = "qdma-error", 927*724ba675SRob Herring "qdma-queue0", "qdma-queue1"; 928*724ba675SRob Herring #dma-cells = <2>; 929*724ba675SRob Herring dma-channels = <8>; 930*724ba675SRob Herring block-number = <1>; 931*724ba675SRob Herring block-offset = <0x1000>; 932*724ba675SRob Herring fsl,dma-queues = <2>; 933*724ba675SRob Herring status-sizes = <64>; 934*724ba675SRob Herring queue-sizes = <64 64>; 935*724ba675SRob Herring big-endian; 936*724ba675SRob Herring }; 937*724ba675SRob Herring 938*724ba675SRob Herring rcpm: power-controller@1ee2140 { 939*724ba675SRob Herring compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; 940*724ba675SRob Herring reg = <0x0 0x1ee2140 0x0 0x8>; 941*724ba675SRob Herring #fsl,rcpm-wakeup-cells = <2>; 942*724ba675SRob Herring #power-domain-cells = <0>; 943*724ba675SRob Herring }; 944*724ba675SRob Herring 945*724ba675SRob Herring ftm_alarm0: timer0@29d0000 { 946*724ba675SRob Herring compatible = "fsl,ls1021a-ftm-alarm"; 947*724ba675SRob Herring reg = <0x0 0x29d0000 0x0 0x10000>; 948*724ba675SRob Herring reg-names = "ftm"; 949*724ba675SRob Herring fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>; 950*724ba675SRob Herring interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 951*724ba675SRob Herring big-endian; 952*724ba675SRob Herring }; 953*724ba675SRob Herring }; 954*724ba675SRob Herring 955*724ba675SRob Herring thermal-zones { 956*724ba675SRob Herring cpu_thermal: cpu-thermal { 957*724ba675SRob Herring polling-delay-passive = <1000>; 958*724ba675SRob Herring polling-delay = <5000>; 959*724ba675SRob Herring 960*724ba675SRob Herring thermal-sensors = <&tmu 0>; 961*724ba675SRob Herring 962*724ba675SRob Herring trips { 963*724ba675SRob Herring cpu_alert: cpu-alert { 964*724ba675SRob Herring temperature = <85000>; 965*724ba675SRob Herring hysteresis = <2000>; 966*724ba675SRob Herring type = "passive"; 967*724ba675SRob Herring }; 968*724ba675SRob Herring cpu_crit: cpu-crit { 969*724ba675SRob Herring temperature = <95000>; 970*724ba675SRob Herring hysteresis = <2000>; 971*724ba675SRob Herring type = "critical"; 972*724ba675SRob Herring }; 973*724ba675SRob Herring }; 974*724ba675SRob Herring 975*724ba675SRob Herring cooling-maps { 976*724ba675SRob Herring map0 { 977*724ba675SRob Herring trip = <&cpu_alert>; 978*724ba675SRob Herring cooling-device = 979*724ba675SRob Herring <&cpu0 THERMAL_NO_LIMIT 980*724ba675SRob Herring THERMAL_NO_LIMIT>, 981*724ba675SRob Herring <&cpu1 THERMAL_NO_LIMIT 982*724ba675SRob Herring THERMAL_NO_LIMIT>; 983*724ba675SRob Herring }; 984*724ba675SRob Herring }; 985*724ba675SRob Herring }; 986*724ba675SRob Herring }; 987*724ba675SRob Herring}; 988