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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c30 #include "dc.h"
135 #define SRI(reg_name, block, id)\ argument
136 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 mm ## block ## id ## _ ## reg_name
139 #define SRI2_DWB(reg_name, block, id)\ argument
145 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ argument
148 #define SRIR(var_name, reg_name, block, id)\ argument
149 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 mm ## block ## id ## _ ## reg_name
152 #define SRII(reg_name, block, id)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 dc->ctx->logger
118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
119 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
123 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
127 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
131 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
[all …]
H A Ddce110_hw_sequencer.c27 #include "dc.h"
73 * For eDP, after power-up/power/down,
83 hws->ctx
88 hws->regs->reg
92 hws->shifts->field_name, hws->masks->field_name
100 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
103 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
106 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
109 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
113 #define HW_REG_BLND(reg, id)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c27 #include "dc.h"
112 #define SRI(reg_name, block, id)\ argument
113 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
114 mm ## block ## id ## _ ## reg_name
117 #define SRII(reg_name, block, id)\ argument
118 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
119 mm ## block ## id ## _ ## reg_name
121 #define VUPDATE_SRII(reg_name, block, id)\ argument
122 .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \
123 mm ## reg_name ## 0 ## _ ## block ## id
[all …]
H A Ddcn10_hw_sequencer.c63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
84 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
93 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
102 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
103 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
104 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
111 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.c1 // SPDX-License-Identifier: MIT
28 #include "dc.h"
108 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
115 #define SR_ARR(reg_name, id) \ argument
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
119 REG_STRUCT[id].reg_name = value
121 #define SRI(reg_name, block, id)\ argument
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pixel-link.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
27 - fsl,imx8qm-dc-pixel-link
28 - fsl,imx8qxp-dc-pixel-link
30 fsl,dc-id:
36 fsl,dc-stream-id:
39 u8 value representing the display controller stream index that the pixel
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_fpga.c36 struct dc *dc = pipe_ctx->stream->ctx->dc; in dp_fpga_hpo_enable_link_and_stream() local
37 struct dc_stream_state *stream = pipe_ctx->stream; in dp_fpga_hpo_enable_link_and_stream() local
41 uint8_t vc_id = 1; /// VC ID always 1 for SST in dp_fpga_hpo_enable_link_and_stream()
42 struct dc_link_settings link_settings = pipe_ctx->link_config.dp_link_settings; in dp_fpga_hpo_enable_link_and_stream()
43 const struct link_hwss *link_hwss = get_link_hwss(stream->link, &pipe_ctx->link_res); in dp_fpga_hpo_enable_link_and_stream()
44 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); in dp_fpga_hpo_enable_link_and_stream()
46 stream->link->cur_link_settings = link_settings; in dp_fpga_hpo_enable_link_and_stream()
48 if (link_hwss->ext.enable_dp_link_output) in dp_fpga_hpo_enable_link_and_stream()
49 link_hwss->ext.enable_dp_link_output(stream->link, &pipe_ctx->link_res, in dp_fpga_hpo_enable_link_and_stream()
50 stream->signal, pipe_ctx->clock_source->id, in dp_fpga_hpo_enable_link_and_stream()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 #define SRI(reg_name, block, id)\ argument
40 .reg_name = mm ## block ## id ## _ ## reg_name
55 /*ClocksStateInvalid - should not be used*/
57 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
67 const struct dc *dc, in determine_sclk_from_bounding_box() argument
76 if (dc->sclk_lvls.num_levels == 0) in determine_sclk_from_bounding_box()
79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { in determine_sclk_from_bounding_box()
80 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) in determine_sclk_from_bounding_box()
81 return dc->sclk_lvls.clocks_in_khz[i]; in determine_sclk_from_bounding_box()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c27 * This file owns the programming sequence of stream's dpms state associated
28 * with the link and link's enable/disable sequences as result of the stream's
31 * TODO - The reason link owns stream's dpms programming sequence is
34 * stream state programming sequence. This creates a gray area where the
35 * boundary between link and stream is not clearly defined.
68 #include "dc/dcn30/dcn30_vpg.h"
74 void link_blank_all_dp_displays(struct dc *dc) in link_blank_all_dp_displays() argument
80 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
81 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
82 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_dio.c32 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
34 stream_encoder->funcs->set_throttled_vcp_size( in set_dio_throttled_vcp_size()
41 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); in setup_dio_stream_encoder()
42 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
44 link_enc->funcs->connect_dig_be_to_fe(link_enc, in setup_dio_stream_encoder()
45 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
46 if (dc_is_dp_signal(pipe_ctx->stream->signal)) in setup_dio_stream_encoder()
47 pipe_ctx->stream->ctx->dc->link_srv->dp_trace_source_sequence(pipe_ctx->stream->link, in setup_dio_stream_encoder()
49 if (stream_enc->funcs->map_stream_to_link) in setup_dio_stream_encoder()
50 stream_enc->funcs->map_stream_to_link(stream_enc, in setup_dio_stream_encoder()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h29 #include "dc.h"
81 struct dc *dc,
85 struct dc *dc, struct dc_state *context,
90 struct dc *dc, struct dc_state *context);
93 * @populate_dml_pipes - Populate pipe data struct
99 struct dc *dc,
111 struct dc *dc,
116 * Unassign a link encoder from a stream.
123 struct dc_stream_state *stream);
126 struct dc *dc,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_enc_cfg.c29 #define DC_LOGGER dc->ctx->logger
31 /* Check whether stream is supported by DIG link encoders. */
32 static bool is_dig_link_enc_stream(struct dc_stream_state *stream) in is_dig_link_enc_stream() argument
39 if (stream) { in is_dig_link_enc_stream()
40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
43 /* Need to check link signal type rather than stream signal type which may not in is_dig_link_enc_stream()
46 if (link_enc && ((uint32_t)stream->link->connector_signal & link_enc->output_signals)) { in is_dig_link_enc_stream()
47 if (dc_is_dp_signal(stream->signal)) { in is_dig_link_enc_stream()
51 stream->ctx->dc->link_srv->dp_decide_link_settings(stream, &link_settings); in is_dig_link_enc_stream()
[all …]
H A Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
86 #define UNABLE_TO_SPLIT -1
196 struct resource_pool *dc_create_resource_pool(struct dc *dc, in dc_create_resource_pool() argument
206 init_data->num_virtual_links, dc); in dc_create_resource_pool()
210 init_data->num_virtual_links, dc); in dc_create_resource_pool()
214 init_data->num_virtual_links, dc); in dc_create_resource_pool()
319 dc_destroy_resource_pool(struct dc * dc) dc_destroy_resource_pool() argument
358 resource_construct(unsigned int num_virtual_links,struct dc * dc,struct resource_pool * pool,const struct resource_create_funcs * create_funcs) resource_construct() argument
846 const struct dc_stream_state *stream = pipe_ctx->stream; calculate_odm_slice_in_timing_active() local
935 const struct dc_stream_state *stream = pipe_ctx->stream; calculate_plane_rec_in_timing_active() local
964 const struct dc_stream_state *stream = pipe_ctx->stream; calculate_mpc_slice_in_timing_active() local
996 struct dc *dc = pipe_ctx->stream->ctx->dc; adjust_recout_for_visual_confirm() local
1179 const struct dc_stream_state *stream = pipe_ctx->stream; calculate_scaling_ratios() local
1544 resource_build_scaling_params_for_context(const struct dc * dc,struct dc_state * context) resource_build_scaling_params_for_context() argument
1753 resource_get_otg_master_for_stream(struct resource_context * res_ctx,struct dc_stream_state * stream) resource_get_otg_master_for_stream() argument
1800 acquire_first_split_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream) acquire_first_split_pipe() argument
1909 dc_add_plane_to_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context) dc_add_plane_to_context() argument
1910 dc_add_plane_to_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context) dc_add_plane_to_context() argument
1950 dc_remove_plane_from_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context) dc_remove_plane_from_context() argument
1951 dc_remove_plane_from_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context) dc_remove_plane_from_context() argument
2035 dc_rem_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_state * context) dc_rem_all_planes_for_stream() argument
2036 dc_rem_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_state * context) dc_rem_all_planes_for_stream() argument
2067 add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * context) add_all_planes_for_stream() argument
2068 add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * context) add_all_planes_for_stream() argument
2092 dc_add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * const * plane_states,int plane_count,struct dc_state * context) dc_add_all_planes_for_stream() argument
2093 dc_add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * const * plane_states,int plane_count,struct dc_state * context) dc_add_all_planes_for_stream() argument
2156 dc_is_stream_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream) dc_is_stream_unchanged() argument
2178 dc_is_stream_scaling_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream) dc_is_stream_scaling_unchanged() argument
2281 add_hpo_dp_link_enc_to_ctx(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream) add_hpo_dp_link_enc_to_ctx() argument
2303 remove_hpo_dp_link_enc_from_ctx(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream) remove_hpo_dp_link_enc_from_ctx() argument
2332 acquire_first_free_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream) acquire_first_free_pipe() argument
2368 find_first_free_match_hpo_dp_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream) find_first_free_match_hpo_dp_stream_enc_for_link() argument
2386 find_first_free_audio(struct resource_context * res_ctx,const struct resource_pool * pool,enum engine_id id,enum dce_version dc_version) find_first_free_audio() argument
2422 dc_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream) dc_add_stream_to_ctx() argument
2424 dc_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream) dc_add_stream_to_ctx() argument
2449 dc_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream) dc_remove_stream_from_ctx() argument
2451 dc_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream) dc_remove_stream_from_ctx() argument
2582 calculate_phy_pix_clks(struct dc_stream_state * stream) calculate_phy_pix_clks() argument
2599 acquire_resource_from_hw_enabled_state(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream) acquire_resource_from_hw_enabled_state() argument
2708 mark_seamless_boot_stream(const struct dc * dc,struct dc_stream_state * stream) mark_seamless_boot_stream() argument
2709 mark_seamless_boot_stream(const struct dc * dc,struct dc_stream_state * stream) mark_seamless_boot_stream() argument
2721 resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream) resource_map_pool_resources() argument
2723 resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream) resource_map_pool_resources() argument
2842 dc_resource_state_copy_construct_current(const struct dc * dc,struct dc_state * dst_ctx) dc_resource_state_copy_construct_current() argument
2850 dc_resource_state_construct(const struct dc * dc,struct dc_state * dst_ctx) dc_resource_state_construct() argument
2860 dc_resource_is_dsc_encoding_supported(const struct dc * dc) dc_resource_is_dsc_encoding_supported() argument
2869 planes_changed_for_existing_stream(struct dc_state * context,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count) planes_changed_for_existing_stream() argument
2923 dc_validate_with_context(struct dc * dc,const struct dc_validation_set set[],int set_count,struct dc_state * context,bool fast_validate) dc_validate_with_context() argument
2944 struct dc_stream_state *stream = context->streams[i]; dc_validate_with_context() local
2961 struct dc_stream_state *stream = set[i].stream; dc_validate_with_context() local
3107 dc_validate_global_state(struct dc * dc,struct dc_state * new_ctx,bool fast_validate) dc_validate_global_state() argument
3124 struct dc_stream_state *stream = new_ctx->streams[i]; dc_validate_global_state() local
3201 struct dc_stream_state *stream = pipe_ctx->stream; set_avi_info_frame() local
3478 set_vendor_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream) set_vendor_info_packet() argument
3493 set_spd_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream) set_spd_info_packet() argument
3508 set_hdr_static_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream) set_hdr_static_info_packet() argument
3521 set_vsc_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream) set_vsc_info_packet() argument
3530 set_hfvs_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream) set_hfvs_info_packet() argument
3568 set_adaptive_sync_info_packet(struct dc_info_packet * info_packet,const struct dc_stream_state * stream,struct encoder_info_frame * info_frame,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dlg_param) set_adaptive_sync_info_packet() argument
3585 set_vtem_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream) set_vtem_info_packet() argument
3705 resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream) resource_map_clock_resources() argument
3707 resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream) resource_map_clock_resources() argument
3794 struct dc *dc = pipe_ctx_old->stream->ctx->dc; pipe_need_reprogram() local
3807 resource_build_bit_depth_reduction_params(struct dc_stream_state * stream,struct bit_depth_reduction_params * fmt_bit_depth) resource_build_bit_depth_reduction_params() argument
3933 dc_validate_stream(struct dc * dc,struct dc_stream_state * stream) dc_validate_stream() argument
3964 dc_validate_plane(struct dc * dc,const struct dc_plane_state * plane_state) dc_validate_plane() argument
4079 const struct dc *dc = link->dc; get_temp_dp_link_res() local
4093 reset_syncd_pipes_from_disabled_pipes(struct dc * dc,struct dc_state * context) reset_syncd_pipes_from_disabled_pipes() argument
4121 check_syncd_pipes_for_disabled_master_pipe(struct dc * dc,struct dc_state * context,uint8_t disabled_master_pipe_idx) check_syncd_pipes_for_disabled_master_pipe() argument
4155 reset_sync_context_for_pipe(const struct dc * dc,struct dc_state * context,uint8_t pipe_idx) reset_sync_context_for_pipe() argument
4172 resource_transmitter_to_phy_idx(const struct dc * dc,enum transmitter transmitter) resource_transmitter_to_phy_idx() argument
4239 is_h_timing_divisible_by_2(struct dc_stream_state * stream) is_h_timing_divisible_by_2() argument
4262 dc_resource_acquire_secondary_pipe_for_mpc_odm(const struct dc * dc,struct dc_state * state,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm) dc_resource_acquire_secondary_pipe_for_mpc_odm() argument
4313 update_dp_encoder_resources_for_test_harness(const struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx) update_dp_encoder_resources_for_test_harness() argument
[all...]
H A Ddc.c27 #include "dc.h"
81 dc->ctx
84 dc->ctx->logger
86 static const char DC_BUILD_ID[] = "production-build";
91 * DC is the OS-agnostic component of the amdgpu DC driver.
93 * DC maintains and validates a set of structs representing the state of the
96 * Main DC HW structs:
98 * struct dc - The central struct. One per driver. Created on driver load,
101 * struct dc_context - One per driver.
102 * Used as a backpointer by most other structs in dc.
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
63 dc->ctx->logger
119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_edp_panel_control.c38 #include "dc/dc_dmub_srv.h"
90 link->panel_mode = panel_mode; in dp_set_panel_mode()
93 link->link_index, in dp_set_panel_mode()
94 link->dpcd_caps.panel_mode_edp, in dp_set_panel_mode()
104 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { in dp_get_panel_mode()
106 switch (link->dpcd_caps.branch_dev_id) { in dp_get_panel_mode()
110 * provide sink device id, alternate scrambler in dp_get_panel_mode()
115 link->dpcd_caps.branch_dev_name, in dp_get_panel_mode()
118 link->dpcd_caps. in dp_get_panel_mode()
126 * sink device id, alternate scrambler scheme will in dp_get_panel_mode()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c28 #include "dc.h"
119 #define SRI(reg_name, block, id)\ argument
120 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
121 mm ## block ## id ## _ ## reg_name
123 #define SRI2(reg_name, block, id)\ argument
127 #define SRIR(var_name, reg_name, block, id)\ argument
128 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
129 mm ## block ## id ## _ ## reg_name
131 #define SRII(reg_name, block, id)\ argument
132 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c30 #include "dc.h"
32 #include "dc/inc/core_types.h"
35 #include "dc/inc/hw/dmcu.h"
36 #include "dc/inc/hw/abm.h"
37 #include "dc/dc_dmub_srv.h"
38 #include "dc/dc_edid_parser.h"
39 #include "dc/dc_stat.h"
154 * **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
155 * requests into DC requests, and DC response
378 update_planes_and_stream_adapter(struct dc * dc,int update_type,int planes_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,struct dc_surface_update * array_of_surface_update) update_planes_and_stream_adapter() argument
381 update_planes_and_stream_adapter(struct dc * dc,int update_type,int planes_count,struct dc_stream_state * stream,struct dc_stream_update * stream_update,struct dc_surface_update * array_of_surface_update) update_planes_and_stream_adapter() argument
1427 hpd_rx_irq_create_workqueue(struct dc * dc) hpd_rx_irq_create_workqueue() argument
2572 amdgpu_dm_commit_zero_streams(struct dc * dc) amdgpu_dm_commit_zero_streams() argument
2590 struct dc_stream_state *stream = context->streams[i]; amdgpu_dm_commit_zero_streams() local
3531 struct dc *dc = adev->dm.dc; dce60_register_irq_handlers() local
3614 struct dc *dc = adev->dm.dc; dce110_register_irq_handlers() local
3720 struct dc *dc = adev->dm.dc; dcn10_register_irq_handlers() local
3873 struct dc *dc = adev->dm.dc; register_outbox_irq_handlers() local
5271 update_stream_scaling_settings(const struct drm_display_mode * mode,const struct dm_connector_state * dm_state,struct dc_stream_state * stream) update_stream_scaling_settings() argument
5488 fill_stream_properties_from_drm_display_mode(struct dc_stream_state * stream,const struct drm_display_mode * mode_in,const struct drm_connector * connector,const struct drm_connector_state * connector_state,const struct dc_stream_state * old_stream,int requested_bpc) fill_stream_properties_from_drm_display_mode() argument
5687 set_multisync_trigger_params(struct dc_stream_state * stream) set_multisync_trigger_params() argument
5726 struct dc_stream_state *stream; dm_enable_per_frame_crtc_master_sync() local
5866 update_dsc_caps(struct amdgpu_dm_connector * aconnector,struct dc_sink * sink,struct dc_stream_state * stream,struct dsc_dec_dpcd_caps * dsc_caps) update_dsc_caps() argument
5885 apply_dsc_policy_for_edp(struct amdgpu_dm_connector * aconnector,struct dc_sink * sink,struct dc_stream_state * stream,struct dsc_dec_dpcd_caps * dsc_caps,uint32_t max_dsc_target_bpp_limit_override) apply_dsc_policy_for_edp() argument
5892 struct dc *dc = sink->ctx->dc; apply_dsc_policy_for_edp() local
5949 apply_dsc_policy_for_stream(struct amdgpu_dm_connector * aconnector,struct dc_sink * sink,struct dc_stream_state * stream,struct dsc_dec_dpcd_caps * dsc_caps) apply_dsc_policy_for_stream() argument
5954 struct dc *dc = sink->ctx->dc; apply_dsc_policy_for_stream() local
6036 struct dc_stream_state *stream = NULL; create_stream_for_sink() local
6544 dm_validate_stream_and_context(struct dc * dc,struct dc_stream_state * stream) dm_validate_stream_and_context() argument
6545 dm_validate_stream_and_context(struct dc * dc,struct dc_stream_state * stream) dm_validate_stream_and_context() argument
6615 struct dc_stream_state *stream; create_validate_stream_for_sink() local
6669 struct dc_stream_state *stream; amdgpu_dm_connector_mode_valid() local
6930 struct dc_stream_state *stream = NULL; dm_update_mst_vcpi_slots_for_dsc() local
7325 const struct dc *dc = amdgpu_dm_connector->dc_link->dc; amdgpu_dm_connector_get_modes() local
7537 struct dc *dc = dm->dc; amdgpu_dm_connector_init() local
7837 remove_stream(struct amdgpu_device * adev,struct amdgpu_crtc * acrtc,struct dc_stream_state * stream) remove_stream() argument
9735 dm_update_plane_state(struct dc * dc,struct drm_atomic_state * state,struct drm_plane * plane,struct drm_plane_state * old_plane_state,struct drm_plane_state * new_plane_state,bool enable,bool * lock_and_validation_needed,bool * is_top_most_overlay) dm_update_plane_state() argument
10090 struct dc *dc = adev->dm.dc; amdgpu_dm_atomic_check() local
10521 is_dp_capable_without_timing_msa(struct dc * dc,struct amdgpu_dm_connector * amdgpu_dm_connector) is_dp_capable_without_timing_msa() argument
10961 struct dc *dc = adev->dm.dc; amdgpu_dm_trigger_timing_sync() local
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H A Damdgpu_dm_crtc.c1 // SPDX-License-Identifier: MIT
29 #include "dc.h"
39 struct drm_crtc *crtc = &acrtc->base; in amdgpu_dm_crtc_handle_vblank()
40 struct drm_device *dev = crtc->dev; in amdgpu_dm_crtc_handle_vblank()
45 spin_lock_irqsave(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
47 /* Send completion event for cursor-only commits */ in amdgpu_dm_crtc_handle_vblank()
48 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in amdgpu_dm_crtc_handle_vblank()
49 drm_crtc_send_vblank_event(crtc, acrtc->event); in amdgpu_dm_crtc_handle_vblank()
51 acrtc->event = NULL; in amdgpu_dm_crtc_handle_vblank()
54 spin_unlock_irqrestore(&dev->event_lock, flags); in amdgpu_dm_crtc_handle_vblank()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/
H A Ddcn315_resource.c28 #include "dc.h"
165 #define SRI(reg_name, block, id)\ argument
166 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
167 reg ## block ## id ## _ ## reg_name
169 #define SRI2(reg_name, block, id)\ argument
173 #define SRIR(var_name, reg_name, block, id)\ argument
174 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
175 reg ## block ## id ## _ ## reg_name
177 #define SRII(reg_name, block, id)\ argument
178 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8qxp-pixel-link.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/media-bus-format.h>
18 #include <dt-bindings/firmware/imx/rsrc.h>
20 #define DRIVER_NAME "imx8qxp-display-pixel-link"
43 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_en()
44 pl->mst_en_ctrl, true); in imx8qxp_pixel_link_enable_mst_en()
46 DRM_DEV_ERROR(pl->dev, in imx8qxp_pixel_link_enable_mst_en()
47 "failed to enable DC%u stream%u pixel link mst_en: %d\n", in imx8qxp_pixel_link_enable_mst_en()
48 pl->dc_id, pl->stream_id, ret); in imx8qxp_pixel_link_enable_mst_en()
55 ret = imx_sc_misc_set_control(pl->ipc_handle, pl->sink_rsc, in imx8qxp_pixel_link_enable_mst_vld()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/
H A Ddce100_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
110 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
114 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c30 #include "dc.h"
105 #define SRI(reg_name, block, id)\ argument
106 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
107 mm ## block ## id ## _ ## reg_name
109 #define SRIR(var_name, reg_name, block, id)\ argument
110 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
111 mm ## block ## id ## _ ## reg_name
113 #define SRII(reg_name, block, id)\ argument
114 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
115 mm ## block ## id ## _ ## reg_name
[all …]
/openbmc/qemu/hw/audio/
H A Dhda-codec.c22 #include "hw/qdev-properties.h"
23 #include "intel-hda.h"
25 #include "qemu/host-utils.h"
27 #include "intel-hda-defs.h"
32 /* -------------------------------------------------------------------------- */
35 uint32_t id; member
57 static const desc_param* hda_codec_find_param(const desc_node *node, uint32_t id) in hda_codec_find_param() argument
61 for (i = 0; i < node->nparams; i++) { in hda_codec_find_param()
62 if (node->params[i].id == id) { in hda_codec_find_param()
63 return &node->params[i]; in hda_codec_find_param()
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