14562236bSHarry Wentland /* 24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc. 34562236bSHarry Wentland * 44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a 54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"), 64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation 74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense, 84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the 94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions: 104562236bSHarry Wentland * 114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in 124562236bSHarry Wentland * all copies or substantial portions of the Software. 134562236bSHarry Wentland * 144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE. 214562236bSHarry Wentland * 224562236bSHarry Wentland * Authors: AMD 234562236bSHarry Wentland * 244562236bSHarry Wentland */ 254562236bSHarry Wentland 264562236bSHarry Wentland #ifndef _CORE_TYPES_H_ 274562236bSHarry Wentland #define _CORE_TYPES_H_ 284562236bSHarry Wentland 294562236bSHarry Wentland #include "dc.h" 305e141de4SHarry Wentland #include "dce_calcs.h" 31ff5ef992SAlex Deucher #include "dcn_calcs.h" 324562236bSHarry Wentland #include "ddc_service_types.h" 334562236bSHarry Wentland #include "dc_bios_types.h" 34ff5ef992SAlex Deucher #include "mem_input.h" 358feabd03SYue Hin Lau #include "hubp.h" 36ff5ef992SAlex Deucher #include "mpc.h" 37345429a6SHarry Wentland #include "dwb.h" 38345429a6SHarry Wentland #include "mcif_wb.h" 39d4caa72eSAnthony Koo #include "panel_cntl.h" 400baae624SAlvin Lee #include "dmub/inc/dmub_cmd.h" 414562236bSHarry Wentland 424562236bSHarry Wentland #define MAX_CLOCK_SOURCES 7 4320dad381SJun Lei #define MAX_SVP_PHANTOM_STREAMS 2 4420dad381SJun Lei #define MAX_SVP_PHANTOM_PLANES 2 454562236bSHarry Wentland 463be5262eSHarry Wentland void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 474562236bSHarry Wentland uint32_t controller_id); 484562236bSHarry Wentland 494562236bSHarry Wentland #include "grph_object_id.h" 504562236bSHarry Wentland #include "link_encoder.h" 514562236bSHarry Wentland #include "stream_encoder.h" 524562236bSHarry Wentland #include "clock_source.h" 534562236bSHarry Wentland #include "audio.h" 54a185048cSTony Cheng #include "dm_pp_smu.h" 55d462fcf5SBhawanpreet Lakha #include "dm_cp_psp.h" 56fd249266SWenjing Liu #include "link_hwss.h" 574562236bSHarry Wentland 584562236bSHarry Wentland /********** DAL Core*********************/ 594562236bSHarry Wentland #include "transform.h" 60d94585a0SYue Hin Lau #include "dpp.h" 614562236bSHarry Wentland 624562236bSHarry Wentland struct resource_pool; 63608ac7bbSJerry Zuo struct dc_state; 644562236bSHarry Wentland struct resource_context; 65aa919167SBhawanpreet Lakha struct clk_bw_params; 664562236bSHarry Wentland 674562236bSHarry Wentland struct resource_funcs { 68*64be47baSMustapha Ghaddar enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); 694562236bSHarry Wentland void (*destroy)(struct resource_pool **pool); 7066b198ffSDmytro Laktyushkin void (*link_init)(struct dc_link *link); 71d4caa72eSAnthony Koo struct panel_cntl*(*panel_cntl_create)( 72d4caa72eSAnthony Koo const struct panel_cntl_init_data *panel_cntl_init_data); 734562236bSHarry Wentland struct link_encoder *(*link_enc_create)( 74e216431bSAurabindo Pillai struct dc_context *ctx, 754562236bSHarry Wentland const struct encoder_init_data *init); 76e1f4328fSJimmy Kizito /* Create a minimal link encoder object with no dc_link object 77e1f4328fSJimmy Kizito * associated with it. */ 78e1f4328fSJimmy Kizito struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 79e1f4328fSJimmy Kizito 8045209ef7SDmytro Laktyushkin bool (*validate_bandwidth)( 81fb3466a4SBhawanpreet Lakha struct dc *dc, 82afcd526bSJoshua Aberback struct dc_state *context, 83afcd526bSJoshua Aberback bool fast_validate); 848e02c26aSJoshua Aberback void (*calculate_wm_and_dlg)( 85b3ff538cSDmytro Laktyushkin struct dc *dc, struct dc_state *context, 86b3ff538cSDmytro Laktyushkin display_e2e_pipe_params_st *pipes, 87b3ff538cSDmytro Laktyushkin int pipe_cnt, 88b3ff538cSDmytro Laktyushkin int vlevel); 89443dfba0SDmytro Laktyushkin void (*update_soc_for_wm_a)( 90443dfba0SDmytro Laktyushkin struct dc *dc, struct dc_state *context); 911682bd1aSRodrigo Siqueira 921682bd1aSRodrigo Siqueira /** 931682bd1aSRodrigo Siqueira * @populate_dml_pipes - Populate pipe data struct 941682bd1aSRodrigo Siqueira * 951682bd1aSRodrigo Siqueira * Returns: 961682bd1aSRodrigo Siqueira * Total of pipes available in the specific ASIC. 971682bd1aSRodrigo Siqueira */ 98ed07237cSIlya Bakoulin int (*populate_dml_pipes)( 99ed07237cSIlya Bakoulin struct dc *dc, 1002f488884SAlvin Lee struct dc_state *context, 101fa896813SIsabel Zhang display_e2e_pipe_params_st *pipes, 102fa896813SIsabel Zhang bool fast_validate); 103ed07237cSIlya Bakoulin 104f42ef862SJimmy Kizito /* 105f42ef862SJimmy Kizito * Algorithm for assigning available link encoders to links. 106f42ef862SJimmy Kizito * 107f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 108f42ef862SJimmy Kizito * struct resource_context. 109f42ef862SJimmy Kizito */ 110f42ef862SJimmy Kizito void (*link_encs_assign)( 111f42ef862SJimmy Kizito struct dc *dc, 112f42ef862SJimmy Kizito struct dc_state *state, 113f42ef862SJimmy Kizito struct dc_stream_state *streams[], 114f42ef862SJimmy Kizito uint8_t stream_count); 115f42ef862SJimmy Kizito /* 116f42ef862SJimmy Kizito * Unassign a link encoder from a stream. 117f42ef862SJimmy Kizito * 118f42ef862SJimmy Kizito * Update link_enc_assignments table and link_enc_avail list accordingly in 119f42ef862SJimmy Kizito * struct resource_context. 120f42ef862SJimmy Kizito */ 121f42ef862SJimmy Kizito void (*link_enc_unassign)( 122f42ef862SJimmy Kizito struct dc_state *state, 123f42ef862SJimmy Kizito struct dc_stream_state *stream); 124f42ef862SJimmy Kizito 1251dc90497SAndrey Grodzovsky enum dc_status (*validate_global)( 1261dc90497SAndrey Grodzovsky struct dc *dc, 127608ac7bbSJerry Zuo struct dc_state *context); 1281dc90497SAndrey Grodzovsky 129198f0e89SWenjing Liu struct pipe_ctx *(*acquire_free_pipe_as_secondary_dpp_pipe)( 130460ea898SWenjing Liu const struct dc_state *cur_ctx, 131460ea898SWenjing Liu struct dc_state *new_ctx, 132a2b8659dSTony Cheng const struct resource_pool *pool, 133460ea898SWenjing Liu const struct pipe_ctx *opp_head_pipe); 1341dc90497SAndrey Grodzovsky 135460ea898SWenjing Liu enum dc_status (*validate_plane)( 136460ea898SWenjing Liu const struct dc_plane_state *plane_state, 137460ea898SWenjing Liu struct dc_caps *caps); 1381dc90497SAndrey Grodzovsky 1391dc90497SAndrey Grodzovsky enum dc_status (*add_stream_to_ctx)( 1401dc90497SAndrey Grodzovsky struct dc *dc, 141608ac7bbSJerry Zuo struct dc_state *new_ctx, 1421dc90497SAndrey Grodzovsky struct dc_stream_state *dc_stream); 143e56ae556SNikola Cornij 144e56ae556SNikola Cornij enum dc_status (*remove_stream_from_ctx)( 145e56ae556SNikola Cornij struct dc *dc, 146e56ae556SNikola Cornij struct dc_state *new_ctx, 147e56ae556SNikola Cornij struct dc_stream_state *stream); 1488d8c82b6SJoseph Gravenor enum dc_status (*patch_unknown_plane_state)( 14974eac5f3SSu Sung Chung struct dc_plane_state *plane_state); 15074eac5f3SSu Sung Chung 15178cc70b1SWesley Chalmers struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 15278cc70b1SWesley Chalmers struct resource_context *res_ctx, 15378cc70b1SWesley Chalmers const struct resource_pool *pool, 15478cc70b1SWesley Chalmers struct dc_stream_state *stream); 155345429a6SHarry Wentland void (*populate_dml_writeback_from_context)( 156345429a6SHarry Wentland struct dc *dc, 157345429a6SHarry Wentland struct resource_context *res_ctx, 158345429a6SHarry Wentland display_e2e_pipe_params_st *pipes); 15978cc70b1SWesley Chalmers 160345429a6SHarry Wentland void (*set_mcif_arb_params)( 161345429a6SHarry Wentland struct dc *dc, 162345429a6SHarry Wentland struct dc_state *context, 163345429a6SHarry Wentland display_e2e_pipe_params_st *pipes, 164345429a6SHarry Wentland int pipe_cnt); 1651b2c7b2cSBhawanpreet Lakha void (*update_bw_bounding_box)( 1661b2c7b2cSBhawanpreet Lakha struct dc *dc, 1671b2c7b2cSBhawanpreet Lakha struct clk_bw_params *bw_params); 1685dba4991SBhawanpreet Lakha bool (*acquire_post_bldn_3dlut)( 1695dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1705dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1715dba4991SBhawanpreet Lakha int mpcc_id, 1725dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1735dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 1745dba4991SBhawanpreet Lakha 1755dba4991SBhawanpreet Lakha bool (*release_post_bldn_3dlut)( 1765dba4991SBhawanpreet Lakha struct resource_context *res_ctx, 1775dba4991SBhawanpreet Lakha const struct resource_pool *pool, 1785dba4991SBhawanpreet Lakha struct dc_3dlut **lut, 1795dba4991SBhawanpreet Lakha struct dc_transfer_func **shaper); 18059b8ca24SAlex Hung 181b4f71c8cSAurabindo Pillai enum dc_status (*add_dsc_to_stream_resource)( 182b4f71c8cSAurabindo Pillai struct dc *dc, struct dc_state *state, 183b4f71c8cSAurabindo Pillai struct dc_stream_state *stream); 184d3dfceb5SAurabindo Pillai 185d3dfceb5SAurabindo Pillai void (*add_phantom_pipes)( 186d3dfceb5SAurabindo Pillai struct dc *dc, 187d3dfceb5SAurabindo Pillai struct dc_state *context, 188d3dfceb5SAurabindo Pillai display_e2e_pipe_params_st *pipes, 189d3dfceb5SAurabindo Pillai unsigned int pipe_cnt, 190d3dfceb5SAurabindo Pillai unsigned int index); 19185f4bc0cSAlvin Lee 192fd9978aaSAlvin Lee bool (*remove_phantom_pipes)(struct dc *dc, struct dc_state *context, bool fast_update); 1939b216b7eSAlvin Lee void (*retain_phantom_pipes)(struct dc *dc, struct dc_state *context); 1941178ac68SIan Chen void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); 195aaae5211SAlvin Lee void (*save_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 196aaae5211SAlvin Lee void (*restore_mall_state)(struct dc *dc, struct dc_state *context, struct mall_temp_config *temp_config); 1974562236bSHarry Wentland }; 1984562236bSHarry Wentland 1994562236bSHarry Wentland struct audio_support{ 2004562236bSHarry Wentland bool dp_audio; 2014562236bSHarry Wentland bool hdmi_audio_on_dongle; 2024562236bSHarry Wentland bool hdmi_audio_native; 2034562236bSHarry Wentland }; 2044562236bSHarry Wentland 205f0e3db90SHarry Wentland #define NO_UNDERLAY_PIPE -1 206f0e3db90SHarry Wentland 2074562236bSHarry Wentland struct resource_pool { 2084562236bSHarry Wentland struct mem_input *mis[MAX_PIPES]; 2098feabd03SYue Hin Lau struct hubp *hubps[MAX_PIPES]; 2104562236bSHarry Wentland struct input_pixel_processor *ipps[MAX_PIPES]; 2114562236bSHarry Wentland struct transform *transforms[MAX_PIPES]; 212d94585a0SYue Hin Lau struct dpp *dpps[MAX_PIPES]; 2134562236bSHarry Wentland struct output_pixel_processor *opps[MAX_PIPES]; 2144562236bSHarry Wentland struct timing_generator *timing_generators[MAX_PIPES]; 2154562236bSHarry Wentland struct stream_encoder *stream_enc[MAX_PIPES * 2]; 216c9ef081dSYue Hin Lau struct hubbub *hubbub; 217cc408d72SDmytro Laktyushkin struct mpc *mpc; 2180f1a6ad7SJun Lei struct pp_smu_funcs *pp_smu; 2191877ccf6SDavid Francis struct dce_aux *engines[MAX_PIPES]; 220c85e6e54SDavid Francis struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 221c85e6e54SDavid Francis struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 222c85e6e54SDavid Francis bool i2c_hw_buffer_in_use; 2234562236bSHarry Wentland 224345429a6SHarry Wentland struct dwbc *dwbc[MAX_DWB_PIPES]; 225345429a6SHarry Wentland struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 226345429a6SHarry Wentland struct { 227345429a6SHarry Wentland unsigned int gsl_0:1; 228345429a6SHarry Wentland unsigned int gsl_1:1; 229345429a6SHarry Wentland unsigned int gsl_2:1; 230345429a6SHarry Wentland } gsl_groups; 231345429a6SHarry Wentland 23297bda032SHarry Wentland struct display_stream_compressor *dscs[MAX_PIPES]; 233345429a6SHarry Wentland 2344562236bSHarry Wentland unsigned int pipe_count; 2354562236bSHarry Wentland unsigned int underlay_pipe_index; 2364562236bSHarry Wentland unsigned int stream_enc_count; 237929c3aaaSEric Bernstein 238e1f4328fSJimmy Kizito /* An array for accessing the link encoder objects that have been created. 239e1f4328fSJimmy Kizito * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 240e1f4328fSJimmy Kizito */ 241e1f4328fSJimmy Kizito struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 242e1f4328fSJimmy Kizito /* Number of DIG link encoder objects created - i.e. number of valid 243e1f4328fSJimmy Kizito * entries in link_encoders array. 244e1f4328fSJimmy Kizito */ 245e1f4328fSJimmy Kizito unsigned int dig_link_enc_count; 246eabf2019SJimmy Kizito /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 247eabf2019SJimmy Kizito unsigned int usb4_dpia_count; 248e1f4328fSJimmy Kizito 24983228ebbSFangzhi Zuo unsigned int hpo_dp_stream_enc_count; 25083228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 2513bc8d921SFangzhi Zuo unsigned int hpo_dp_link_enc_count; 2523bc8d921SFangzhi Zuo struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 2535dba4991SBhawanpreet Lakha struct dc_3dlut *mpc_lut[MAX_PIPES]; 2545dba4991SBhawanpreet Lakha struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 25559b8ca24SAlex Hung 25633d7598dSJun Lei struct { 25733d7598dSJun Lei unsigned int xtalin_clock_inKhz; 25833d7598dSJun Lei unsigned int dccg_ref_clock_inKhz; 25933d7598dSJun Lei unsigned int dchub_ref_clock_inKhz; 26033d7598dSJun Lei } ref_clocks; 2613be1406aSYongqiang Sun unsigned int timing_generator_count; 262345429a6SHarry Wentland unsigned int mpcc_count; 2634562236bSHarry Wentland 264345429a6SHarry Wentland unsigned int writeback_pipe_count; 2654562236bSHarry Wentland /* 2664562236bSHarry Wentland * reserved clock source for DP 2674562236bSHarry Wentland */ 2684562236bSHarry Wentland struct clock_source *dp_clock_source; 2694562236bSHarry Wentland 2704562236bSHarry Wentland struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 2714562236bSHarry Wentland unsigned int clk_src_count; 2724562236bSHarry Wentland 2737352193aSTai Man struct audio *audios[MAX_AUDIOS]; 2744562236bSHarry Wentland unsigned int audio_count; 2754562236bSHarry Wentland struct audio_support audio_support; 2764562236bSHarry Wentland 277ea2e8d92SDmytro Laktyushkin struct dccg *dccg; 2784562236bSHarry Wentland struct irq_service *irqs; 2794562236bSHarry Wentland 2805e7773a2SAnthony Koo struct abm *abm; 2815e7773a2SAnthony Koo struct dmcu *dmcu; 2824c1a1335SWyatt Wood struct dmub_psr *psr; 2835e7773a2SAnthony Koo 284e0138644SBhawanpreet Lakha struct dmub_replay *replay; 285e0138644SBhawanpreet Lakha 286d99f1387SBhawanpreet Lakha struct abm *multiple_abms[MAX_PIPES]; 287d99f1387SBhawanpreet Lakha 2884562236bSHarry Wentland const struct resource_funcs *funcs; 2894562236bSHarry Wentland const struct resource_caps *res_cap; 290d9a07577SJun Lei 291d9a07577SJun Lei struct ddc_service *oem_device; 2924562236bSHarry Wentland }; 2934562236bSHarry Wentland 294f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth { 29569338c1fSDmytro Laktyushkin int dppclk_khz; 296799c5b9cSWesley Chalmers 297f553e681SDmytro Laktyushkin }; 298f553e681SDmytro Laktyushkin 29979b06f0cSHarry Wentland struct stream_resource { 300a6a6cb34SHarry Wentland struct output_pixel_processor *opp; 30197bda032SHarry Wentland struct display_stream_compressor *dsc; 3026b670fa9SHarry Wentland struct timing_generator *tg; 3038e9c4c8cSHarry Wentland struct stream_encoder *stream_enc; 30483228ebbSFangzhi Zuo struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 305afaacef4SHarry Wentland struct audio *audio; 30610688217SHarry Wentland 30710688217SHarry Wentland struct pixel_clk_params pix_clk_params; 30896c50c0dSHarry Wentland struct encoder_info_frame encoder_info_frame; 3099aef1a31SSivapiriyanKumarasamy 3109aef1a31SSivapiriyanKumarasamy struct abm *abm; 311345429a6SHarry Wentland /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 312345429a6SHarry Wentland * otherwise it's using group number 'gsl_group-1' 313345429a6SHarry Wentland */ 314345429a6SHarry Wentland uint8_t gsl_group; 31579b06f0cSHarry Wentland }; 31679b06f0cSHarry Wentland 31779b06f0cSHarry Wentland struct plane_resource { 3186702a9acSHarry Wentland struct scaler_data scl_data; 3198feabd03SYue Hin Lau struct hubp *hubp; 32086a66c4eSHarry Wentland struct mem_input *mi; 32186a66c4eSHarry Wentland struct input_pixel_processor *ipp; 32286a66c4eSHarry Wentland struct transform *xfm; 323d94585a0SYue Hin Lau struct dpp *dpp; 324e07f541fSYongqiang Sun uint8_t mpcc_inst; 325f553e681SDmytro Laktyushkin 326f553e681SDmytro Laktyushkin struct dcn_fe_bandwidth bw; 32779b06f0cSHarry Wentland }; 32879b06f0cSHarry Wentland 3294c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__MASK 0xFFFF 3304c3adc0bSWenjing Liu #define LINK_RES_HPO_DP_REC_MAP__SHIFT 0 3314c3adc0bSWenjing Liu 332ef30f441SWenjing Liu /* all mappable hardware resources used to enable a link */ 333ef30f441SWenjing Liu struct link_resource { 334f3fac948SWenjing Liu struct hpo_dp_link_encoder *hpo_dp_link_enc; 335ef30f441SWenjing Liu }; 336ef30f441SWenjing Liu 337017860c9SWenjing Liu struct link_config { 338017860c9SWenjing Liu struct dc_link_settings dp_link_settings; 339017860c9SWenjing Liu }; 34024c18794SDmytro Laktyushkin union pipe_update_flags { 34124c18794SDmytro Laktyushkin struct { 34224c18794SDmytro Laktyushkin uint32_t enable : 1; 34324c18794SDmytro Laktyushkin uint32_t disable : 1; 34424c18794SDmytro Laktyushkin uint32_t odm : 1; 34524c18794SDmytro Laktyushkin uint32_t global_sync : 1; 34624c18794SDmytro Laktyushkin uint32_t opp_changed : 1; 34724c18794SDmytro Laktyushkin uint32_t tg_changed : 1; 34824c18794SDmytro Laktyushkin uint32_t mpcc : 1; 34924c18794SDmytro Laktyushkin uint32_t dppclk : 1; 35024c18794SDmytro Laktyushkin uint32_t hubp_interdependent : 1; 35124c18794SDmytro Laktyushkin uint32_t hubp_rq_dlg_ttu : 1; 35224c18794SDmytro Laktyushkin uint32_t gamut_remap : 1; 35324c18794SDmytro Laktyushkin uint32_t scaler : 1; 35424c18794SDmytro Laktyushkin uint32_t viewport : 1; 355498563cfSJinZe.Xu uint32_t plane_changed : 1; 356ba5a5371SNicholas Kazlauskas uint32_t det_size : 1; 357fe9fa385SAlvin Lee uint32_t unbounded_req : 1; 35824c18794SDmytro Laktyushkin } bits; 35924c18794SDmytro Laktyushkin uint32_t raw; 36024c18794SDmytro Laktyushkin }; 36124c18794SDmytro Laktyushkin 3624562236bSHarry Wentland struct pipe_ctx { 3633be5262eSHarry Wentland struct dc_plane_state *plane_state; 3640971c40eSHarry Wentland struct dc_stream_state *stream; 3654562236bSHarry Wentland 36679b06f0cSHarry Wentland struct plane_resource plane_res; 367fdf17f10SRodrigo Siqueira 368fdf17f10SRodrigo Siqueira /** 369fdf17f10SRodrigo Siqueira * @stream_res: Reference to DCN resource components such OPP and DSC. 370fdf17f10SRodrigo Siqueira */ 37179b06f0cSHarry Wentland struct stream_resource stream_res; 372ef30f441SWenjing Liu struct link_resource link_res; 37379b06f0cSHarry Wentland 3744562236bSHarry Wentland struct clock_source *clock_source; 3754562236bSHarry Wentland 3764562236bSHarry Wentland struct pll_settings pll_settings; 3774562236bSHarry Wentland 3786a0114e0SRodrigo Siqueira /** 3796a0114e0SRodrigo Siqueira * @link_config: 3806a0114e0SRodrigo Siqueira * 3816a0114e0SRodrigo Siqueira * link config records software decision for what link config should be 382017860c9SWenjing Liu * enabled given current link capability and stream during hw resource 383017860c9SWenjing Liu * mapping. This is to decouple the dependency on link capability during 384017860c9SWenjing Liu * dc commit or update. 385017860c9SWenjing Liu */ 386017860c9SWenjing Liu struct link_config link_config; 387017860c9SWenjing Liu 3884562236bSHarry Wentland uint8_t pipe_idx; 389a896f870SMeenakshikumar Somasundaram uint8_t pipe_idx_syncd; 3904562236bSHarry Wentland 3914562236bSHarry Wentland struct pipe_ctx *top_pipe; 3924562236bSHarry Wentland struct pipe_ctx *bottom_pipe; 393b1f6d01cSDmytro Laktyushkin struct pipe_ctx *next_odm_pipe; 394b1f6d01cSDmytro Laktyushkin struct pipe_ctx *prev_odm_pipe; 395f0558542SDmytro Laktyushkin 396ff5ef992SAlex Deucher struct _vcs_dpi_display_dlg_regs_st dlg_regs; 397ff5ef992SAlex Deucher struct _vcs_dpi_display_ttu_regs_st ttu_regs; 398ff5ef992SAlex Deucher struct _vcs_dpi_display_rq_regs_st rq_regs; 399ff5ef992SAlex Deucher struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 4001f2fcc81SHarry Wentland struct _vcs_dpi_display_rq_params_st dml_rq_param; 4011f2fcc81SHarry Wentland struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 4021f2fcc81SHarry Wentland struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 403ba5a5371SNicholas Kazlauskas int det_buffer_size_kb; 404ba5a5371SNicholas Kazlauskas bool unbounded_req; 405238debcaSDillon Varone unsigned int surface_size_in_mall_bytes; 40659b8ca24SAlex Hung 407345429a6SHarry Wentland struct dwbc *dwbc; 408345429a6SHarry Wentland struct mcif_wb *mcif_wb; 409238debcaSDillon Varone union pipe_update_flags update_flags; 410d205a800SLeo (Hanghong) Ma struct tg_color visual_confirm_color; 411d205a800SLeo (Hanghong) Ma bool has_vactive_margin; 4124562236bSHarry Wentland }; 4134562236bSHarry Wentland 4140d4b4253SJimmy Kizito /* Data used for dynamic link encoder assignment. 4150d4b4253SJimmy Kizito * Tracks current and future assignments; available link encoders; 4160d4b4253SJimmy Kizito * and mode of operation (whether to use current or future assignments). 4170d4b4253SJimmy Kizito */ 4180d4b4253SJimmy Kizito struct link_enc_cfg_context { 4190d4b4253SJimmy Kizito enum link_enc_cfg_mode mode; 4200d4b4253SJimmy Kizito struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 4210d4b4253SJimmy Kizito enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 4220d4b4253SJimmy Kizito struct link_enc_assignment transient_assignments[MAX_PIPES]; 4230d4b4253SJimmy Kizito }; 4240d4b4253SJimmy Kizito 4254562236bSHarry Wentland struct resource_context { 4264562236bSHarry Wentland struct pipe_ctx pipe_ctx[MAX_PIPES]; 4274562236bSHarry Wentland bool is_stream_enc_acquired[MAX_PIPES * 2]; 4284562236bSHarry Wentland bool is_audio_acquired[MAX_PIPES]; 4294562236bSHarry Wentland uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 4304562236bSHarry Wentland uint8_t dp_clock_source_ref_count; 431345429a6SHarry Wentland bool is_dsc_acquired[MAX_PIPES]; 4320d4b4253SJimmy Kizito struct link_enc_cfg_context link_enc_cfg_ctx; 43383228ebbSFangzhi Zuo bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 4346dd8931bSWenjing Liu unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 4356dd8931bSWenjing Liu int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 4365dba4991SBhawanpreet Lakha bool is_mpc_3dlut_acquired[MAX_PIPES]; 4374562236bSHarry Wentland }; 4384562236bSHarry Wentland 4399037d802SDmytro Laktyushkin struct dce_bw_output { 4409037d802SDmytro Laktyushkin bool cpuc_state_change_enable; 4419037d802SDmytro Laktyushkin bool cpup_state_change_enable; 4429037d802SDmytro Laktyushkin bool stutter_mode_enable; 4439037d802SDmytro Laktyushkin bool nbp_state_change_enable; 4449037d802SDmytro Laktyushkin bool all_displays_in_sync; 4459037d802SDmytro Laktyushkin struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 4469037d802SDmytro Laktyushkin struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 447b361521fSMikita Lipski struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 4489037d802SDmytro Laktyushkin struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 4499037d802SDmytro Laktyushkin int sclk_khz; 4509037d802SDmytro Laktyushkin int sclk_deep_sleep_khz; 4519037d802SDmytro Laktyushkin int yclk_khz; 4529037d802SDmytro Laktyushkin int dispclk_khz; 4539037d802SDmytro Laktyushkin int blackout_recovery_time_us; 4549037d802SDmytro Laktyushkin }; 4559037d802SDmytro Laktyushkin 456345429a6SHarry Wentland struct dcn_bw_writeback { 457345429a6SHarry Wentland struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 458345429a6SHarry Wentland }; 459345429a6SHarry Wentland 4609037d802SDmytro Laktyushkin struct dcn_bw_output { 461d578839cSDmytro Laktyushkin struct dc_clocks clk; 4629037d802SDmytro Laktyushkin struct dcn_watermark_set watermarks; 463345429a6SHarry Wentland struct dcn_bw_writeback bw_writeback; 464ba5a5371SNicholas Kazlauskas int compbuf_size_kb; 465238debcaSDillon Varone unsigned int mall_ss_size_bytes; 466238debcaSDillon Varone unsigned int mall_ss_psr_active_size_bytes; 467238debcaSDillon Varone unsigned int mall_subvp_size_bytes; 46820dad381SJun Lei unsigned int legacy_svp_drr_stream_index; 46920dad381SJun Lei bool legacy_svp_drr_stream_index_valid; 4709037d802SDmytro Laktyushkin }; 4719037d802SDmytro Laktyushkin 472813d20dcSAidan Wood union bw_output { 4739037d802SDmytro Laktyushkin struct dcn_bw_output dcn; 4749037d802SDmytro Laktyushkin struct dce_bw_output dce; 4759037d802SDmytro Laktyushkin }; 4769037d802SDmytro Laktyushkin 477813d20dcSAidan Wood struct bw_context { 478813d20dcSAidan Wood union bw_output bw; 479813d20dcSAidan Wood struct display_mode_lib dml; 480813d20dcSAidan Wood }; 481fa0fc4fbSRodrigo Siqueira 4820baae624SAlvin Lee struct dc_dmub_cmd { 4830baae624SAlvin Lee union dmub_rb_cmd dmub_cmd; 4840baae624SAlvin Lee enum dm_dmub_wait_type wait_type; 4850baae624SAlvin Lee }; 4860baae624SAlvin Lee 4872119aa17SDavid Francis /** 488fa0fc4fbSRodrigo Siqueira * struct dc_state - The full description of a state requested by users 4892119aa17SDavid Francis */ 490608ac7bbSJerry Zuo struct dc_state { 491fa0fc4fbSRodrigo Siqueira /** 492fa0fc4fbSRodrigo Siqueira * @streams: Stream state properties 493fa0fc4fbSRodrigo Siqueira */ 4940971c40eSHarry Wentland struct dc_stream_state *streams[MAX_PIPES]; 495fa0fc4fbSRodrigo Siqueira 496fa0fc4fbSRodrigo Siqueira /** 497fa0fc4fbSRodrigo Siqueira * @stream_status: Planes status on a given stream 498fa0fc4fbSRodrigo Siqueira */ 499ab2541b6SAric Cyr struct dc_stream_status stream_status[MAX_PIPES]; 500fa0fc4fbSRodrigo Siqueira 501fa0fc4fbSRodrigo Siqueira /** 502fa0fc4fbSRodrigo Siqueira * @stream_count: Total of streams in use 503fa0fc4fbSRodrigo Siqueira */ 504ab2541b6SAric Cyr uint8_t stream_count; 5050825d965SEric Yang uint8_t stream_mask; 5064562236bSHarry Wentland 507fa0fc4fbSRodrigo Siqueira /** 508fa0fc4fbSRodrigo Siqueira * @res_ctx: Persistent state of resources 509fa0fc4fbSRodrigo Siqueira */ 5104562236bSHarry Wentland struct resource_context res_ctx; 5114562236bSHarry Wentland 512fa0fc4fbSRodrigo Siqueira /** 513fa0fc4fbSRodrigo Siqueira * @pp_display_cfg: PowerPlay clocks and settings 514fa0fc4fbSRodrigo Siqueira * Note: this is a big struct, do *not* put on stack! 515fa0fc4fbSRodrigo Siqueira */ 5164562236bSHarry Wentland struct dm_pp_display_configuration pp_display_cfg; 517fa0fc4fbSRodrigo Siqueira 518fa0fc4fbSRodrigo Siqueira /** 519fa0fc4fbSRodrigo Siqueira * @dcn_bw_vars: non-stack memory to support bandwidth calculations 520fa0fc4fbSRodrigo Siqueira * Note: this is a big struct, do *not* put on stack! 521fa0fc4fbSRodrigo Siqueira */ 522ff5ef992SAlex Deucher struct dcn_bw_internal_vars dcn_bw_vars; 5238a76708eSAndrey Grodzovsky 5240de34efcSDmytro Laktyushkin struct clk_mgr *clk_mgr; 525ab8db3e1SAndrey Grodzovsky 5266a0114e0SRodrigo Siqueira /** 5279ed90489SAric Cyr * @bw_ctx: The output from bandwidth and watermark calculations and the DML 5289ed90489SAric Cyr * 5299ed90489SAric Cyr * Each context must have its own instance of VBA, and in order to 5309ed90489SAric Cyr * initialize and obtain IP and SOC, the base DML instance from DC is 5319ed90489SAric Cyr * initially copied into every context. 5329ed90489SAric Cyr */ 5339ed90489SAric Cyr struct bw_context bw_ctx; 5349ed90489SAric Cyr 5350baae624SAlvin Lee struct block_sequence block_sequence[50]; 5360baae624SAlvin Lee unsigned int block_sequence_steps; 5370baae624SAlvin Lee struct dc_dmub_cmd dc_dmub_cmd[10]; 5380baae624SAlvin Lee unsigned int dmub_cmd_count; 5390baae624SAlvin Lee 5409ed90489SAric Cyr /** 5416a0114e0SRodrigo Siqueira * @refcount: refcount reference 5426a0114e0SRodrigo Siqueira * 5436a0114e0SRodrigo Siqueira * Notice that dc_state is used around the code to capture the current 5446a0114e0SRodrigo Siqueira * context, so we need to pass it everywhere. That's why we want to use 5456a0114e0SRodrigo Siqueira * kref in this struct. 5466a0114e0SRodrigo Siqueira */ 5478ee5702aSDave Airlie struct kref refcount; 5486b85151fSMartin Leung 5496b85151fSMartin Leung struct { 5506b85151fSMartin Leung unsigned int stutter_period_us; 5516b85151fSMartin Leung } perf_params; 5524562236bSHarry Wentland }; 5534562236bSHarry Wentland 554e0138644SBhawanpreet Lakha struct replay_context { 555e0138644SBhawanpreet Lakha /* ddc line */ 556e0138644SBhawanpreet Lakha enum channel_id aux_inst; 557e0138644SBhawanpreet Lakha /* Transmitter id */ 558e0138644SBhawanpreet Lakha enum transmitter digbe_inst; 559e0138644SBhawanpreet Lakha /* Engine Id is used for Dig Be source select */ 560e0138644SBhawanpreet Lakha enum engine_id digfe_inst; 561e0138644SBhawanpreet Lakha /* Controller Id used for Dig Fe source select */ 562e0138644SBhawanpreet Lakha enum controller_id controllerId; 563e0138644SBhawanpreet Lakha unsigned int line_time_in_ns; 564e0138644SBhawanpreet Lakha }; 565e0138644SBhawanpreet Lakha 566e0138644SBhawanpreet Lakha enum dc_replay_enable { 567e0138644SBhawanpreet Lakha DC_REPLAY_DISABLE = 0, 568e0138644SBhawanpreet Lakha DC_REPLAY_ENABLE = 1, 569e0138644SBhawanpreet Lakha }; 570e0138644SBhawanpreet Lakha 571e4b0eac3SJasdeep Dhillon struct dc_bounding_box_max_clk { 572e4b0eac3SJasdeep Dhillon int max_dcfclk_mhz; 573e4b0eac3SJasdeep Dhillon int max_dispclk_mhz; 574e4b0eac3SJasdeep Dhillon int max_dppclk_mhz; 575e4b0eac3SJasdeep Dhillon int max_phyclk_mhz; 576e4b0eac3SJasdeep Dhillon }; 577e4b0eac3SJasdeep Dhillon 5784562236bSHarry Wentland #endif /* _CORE_TYPES_H_ */ 579