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/openbmc/qemu/tests/tcg/mips/user/ase/msa/
H A Dtest_msa_run_64r6eb.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6eb
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6eb
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6eb
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6eb
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6eb
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6eb
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6eb
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6eb
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6eb
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6eb
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H A Dtest_msa_run_32r5eb.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5eb
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5eb
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5eb
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5eb
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5eb
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5eb
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5eb
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5eb
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5eb
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5eb
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H A Dtest_msa_run_64r6el.sh8 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_b_64r6el
9 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_h_64r6el
10 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_w_64r6el
11 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nloc_d_64r6el
12 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_b_64r6el
13 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_h_64r6el
14 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_w_64r6el
15 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_nlzc_d_64r6el
16 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_b_64r6el
17 $PATH_TO_QEMU -cpu I6400 /tmp/test_msa_pcnt_h_64r6el
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H A Dtest_msa_run_32r5el.sh8 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_b_32r5el
9 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_h_32r5el
10 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_w_32r5el
11 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nloc_d_32r5el
12 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_b_32r5el
13 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_h_32r5el
14 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_w_32r5el
15 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_nlzc_d_32r5el
16 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_b_32r5el
17 $PATH_TO_QEMU -cpu P5600 /tmp/test_msa_pcnt_h_32r5el
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/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
22 /* Share AArch32 -cpu max features with AArch64. */
23 void aa32_max_features(ARMCPU *cpu) in aa32_max_features() argument
28 t = cpu->isar.id_isar5; in aa32_max_features()
35 cpu->isar.id_isar5 = t; in aa32_max_features()
37 t = cpu->isar.id_isar6; in aa32_max_features()
45 cpu->isar.id_isar6 = t; in aa32_max_features()
47 t = cpu->isar.mvfr1; in aa32_max_features()
50 cpu->isar.mvfr1 = t; in aa32_max_features()
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H A Dcpu-v7m.c12 #include "cpu.h"
13 #include "hw/core/tcg-cpu-ops.h"
23 ARMCPU *cpu = ARM_CPU(cs); in arm_v7m_cpu_exec_interrupt() local
24 CPUARMState *env = &cpu->env; in arm_v7m_cpu_exec_interrupt()
48 ARMCPU *cpu = ARM_CPU(obj); in cortex_m0_initfn() local
49 set_feature(&cpu->env, ARM_FEATURE_V6); in cortex_m0_initfn()
50 set_feature(&cpu->env, ARM_FEATURE_M); in cortex_m0_initfn()
52 cpu->midr = 0x410cc200; in cortex_m0_initfn()
62 cpu->isar.id_pfr0 = 0x00000030; in cortex_m0_initfn()
63 cpu->isar.id_pfr1 = 0x00000200; in cortex_m0_initfn()
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H A Dcpu64.c23 #include "cpu.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
41 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a35_initfn()
42 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a35_initfn()
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/openbmc/qemu/target/i386/hvf/
H A Dx86.h198 #define x86_reg(cpu, reg) ((x86_register *) &cpu->regs[reg]) argument
200 #define RRX(cpu, reg) (x86_reg(cpu, reg)->rrx) argument
201 #define RAX(cpu) RRX(cpu, R_EAX) argument
202 #define RCX(cpu) RRX(cpu, R_ECX) argument
203 #define RDX(cpu) RRX(cpu, R_EDX) argument
204 #define RBX(cpu) RRX(cpu, R_EBX) argument
205 #define RSP(cpu) RRX(cpu, R_ESP) argument
206 #define RBP(cpu) RRX(cpu, R_EBP) argument
207 #define RSI(cpu) RRX(cpu, R_ESI) argument
208 #define RDI(cpu) RRX(cpu, R_EDI) argument
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/openbmc/openbmc/poky/meta/recipes-support/boost/boost/
H A D0001-Don-t-set-up-arch-instruction-set-flags-we-do-that-o.patch19 @@ -1144,156 +1144,3 @@ local rule cpu-flags ( toolset variable : architecture : instruction-set + :
31 -cpu-flags gcc OPTIONS : x86 : native : -march=native ;
32 -cpu-flags gcc OPTIONS : x86 : i486 : -march=i486 ;
33 -cpu-flags gcc OPTIONS : x86 : i586 : -march=i586 ;
34 -cpu-flags gcc OPTIONS : x86 : i686 : -march=i686 ;
35 -cpu-flags gcc OPTIONS : x86 : pentium : -march=pentium ;
36 -cpu-flags gcc OPTIONS : x86 : pentium-mmx : -march=pentium-mmx ;
37 -cpu-flags gcc OPTIONS : x86 : pentiumpro : -march=pentiumpro ;
38 -cpu-flags gcc OPTIONS : x86 : pentium2 : -march=pentium2 ;
39 -cpu-flags gcc OPTIONS : x86 : pentium3 : -march=pentium3 ;
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/openbmc/linux/arch/arm/boot/dts/intel/axm/
H A Daxm5516-cpus.dtsi13 cpu-map {
16 cpu = <&CPU0>;
19 cpu = <&CPU1>;
22 cpu = <&CPU2>;
25 cpu = <&CPU3>;
30 cpu = <&CPU4>;
33 cpu = <&CPU5>;
36 cpu = <&CPU6>;
39 cpu = <&CPU7>;
44 cpu = <&CPU8>;
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/openbmc/qemu/hw/core/
H A Dcpu-common.c2 * QEMU CPU model
23 #include "hw/core/cpu.h"
40 CPUState *cpu; in cpu_by_arch_id() local
42 CPU_FOREACH(cpu) { in cpu_by_arch_id()
43 CPUClass *cc = CPU_GET_CLASS(cpu); in cpu_by_arch_id()
45 if (cc->get_arch_id(cpu) == id) { in cpu_by_arch_id()
46 return cpu; in cpu_by_arch_id()
60 CPUState *cpu = CPU(object_new(typename)); in cpu_create() local
61 if (!qdev_realize(DEVICE(cpu), NULL, &err)) { in cpu_create()
63 object_unref(OBJECT(cpu)); in cpu_create()
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/openbmc/u-boot/arch/arm/dts/
H A Dthunderx-88xx.dtsi24 cpu@000 {
25 device_type = "cpu";
30 cpu@001 {
31 device_type = "cpu";
36 cpu@002 {
37 device_type = "cpu";
42 cpu@003 {
43 device_type = "cpu";
48 cpu@004 {
49 device_type = "cpu";
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/openbmc/qemu/include/hw/core/
H A Dcpu.h2 * QEMU CPU model
44 * SECTION:cpu
45 * @section_id: QEMU-cpu
46 * @title: CPU Class
50 #define TYPE_CPU "cpu"
56 #define CPU(obj) ((CPUState *)(obj)) macro
66 DECLARE_CLASS_CHECKERS(CPUClass, CPU,
73 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators
75 * This macro is typically used in "cpu-qom.h" header file, and will:
77 * - create the typedefs for the CPU object and class structs
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/openbmc/linux/arch/arm/mach-meson/
H A Dplatsmp.c38 static struct reset_control *meson_smp_get_core_reset(int cpu) in meson_smp_get_core_reset() argument
40 struct device_node *np = of_get_cpu_node(cpu, 0); in meson_smp_get_core_reset()
45 static void meson_smp_set_cpu_ctrl(int cpu, bool on_off) in meson_smp_set_cpu_ctrl() argument
50 val |= BIT(cpu); in meson_smp_set_cpu_ctrl()
52 val &= ~BIT(cpu); in meson_smp_set_cpu_ctrl()
116 static void meson_smp_begin_secondary_boot(unsigned int cpu) in meson_smp_begin_secondary_boot() argument
119 * Set the entry point before powering on the CPU through the SCU. This in meson_smp_begin_secondary_boot()
120 * is needed if the CPU is in "warm" state (= after rebooting the in meson_smp_begin_secondary_boot()
121 * system without power-cycling, or when taking the CPU offline and in meson_smp_begin_secondary_boot()
125 sram_base + MESON_SMP_SRAM_CPU_CTRL_ADDR_REG(cpu)); in meson_smp_begin_secondary_boot()
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/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Dcpu-topology.txt2 CPU topology binding description
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
32 The cpu nodes, as per bindings defined in [4], represent the devices that
35 A topology description containing phandles to cpu nodes that are not compliant
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dcrypto6.json3 "Unit": "CPU-M-CF",
7 …counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
10 "Unit": "CPU-M-CF",
14 …al number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- numb…
17 "Unit": "CPU-M-CF",
21 …that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing …
24 "Unit": "CPU-M-CF",
28 …CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the …
31 "Unit": "CPU-M-CF",
35 …"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
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/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dcrypto6.json3 "Unit": "CPU-M-CF",
7 …counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
10 "Unit": "CPU-M-CF",
14 …al number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- numb…
17 "Unit": "CPU-M-CF",
21 …that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing …
24 "Unit": "CPU-M-CF",
28 …CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the …
31 "Unit": "CPU-M-CF",
35 …"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dintel_pstate.c20 #include <linux/cpu.h>
30 #include <asm/cpu.h>
97 * to account for cpu idle period
133 * Stores the per cpu model P state limits and current P state.
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
221 * @sched_flags: Store scheduler flags for possible cross CPU update
226 * This structure stores per CPU instance data for all CPUs.
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/openbmc/qemu/qapi/
H A Dmachine-target.json12 # Virtual CPU model.
14 # A CPU model consists of the name of a CPU definition, to which delta
20 # @name: the name of the CPU definition the model is based on
33 # An enumeration of CPU model expansion types.
35 # @static: Expand to a static CPU model, a combination of a static
37 # model will never change, the expanded CPU model will be the
42 # The @static CPU models are migration-safe.
48 # .. note:: When a non-migration-safe CPU model is expanded in static
49 # mode, some features enabled by the CPU model may be omitted,
50 # because they can't be implemented by a static CPU model
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/openbmc/qemu/target/arm/
H A Dcpu64.c2 * QEMU AArch64 CPU
23 #include "cpu.h"
36 #include "cpu-features.h"
39 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_sve_finalize() argument
56 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
57 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
63 * CPU models specify a set of supported vector lengths which are in arm_cpu_sve_finalize()
70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); in arm_cpu_sve_finalize()
71 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
73 assert(!cpu_isar_feature(aa64_sve, cpu)); in arm_cpu_sve_finalize()
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/openbmc/linux/arch/arm64/boot/dts/cavium/
H A Dthunder-88xx.dtsi65 cpu@0 {
66 device_type = "cpu";
71 cpu@1 {
72 device_type = "cpu";
77 cpu@2 {
78 device_type = "cpu";
83 cpu@3 {
84 device_type = "cpu";
89 cpu@4 {
90 device_type = "cpu";
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/openbmc/linux/arch/arm/mach-tegra/
H A Dplatsmp.c36 static void tegra_secondary_init(unsigned int cpu) in tegra_secondary_init() argument
38 cpumask_set_cpu(cpu, &tegra_cpu_init_mask); in tegra_secondary_init()
42 static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle) in tegra20_boot_secondary() argument
44 cpu = cpu_logical_map(cpu); in tegra20_boot_secondary()
47 * Force the CPU into reset. The CPU must remain in reset when in tegra20_boot_secondary()
49 * flow controller to stop driving reset if the CPU has been in tegra20_boot_secondary()
51 * effect on first boot of the CPU since it should already be in tegra20_boot_secondary()
54 tegra_put_cpu_in_reset(cpu); in tegra20_boot_secondary()
57 * Unhalt the CPU. If the flow controller was used to in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
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/openbmc/linux/tools/testing/selftests/cpu-hotplug/
H A Dcpu-on-off-test.sh27 if ! ls $SYSFS/devices/system/cpu/cpu* > /dev/null 2>&1; then
28 echo $msg cpu hotplug is not supported >&2
32 echo "CPU online/offline summary:"
33 online_cpus=`cat $SYSFS/devices/system/cpu/online`
37 echo "$msg: since there is only one cpu: $online_cpus"
41 present_cpus=`cat $SYSFS/devices/system/cpu/present`
47 offline_cpus=`cat $SYSFS/devices/system/cpu/offline`
63 for cpu in $SYSFS/devices/system/cpu/cpu*; do
64 if [ -f $cpu/online ] && grep -q $state $cpu/online; then
65 echo ${cpu##/*/cpu}
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/openbmc/qemu/system/
H A Dcpus.c35 #include "exec/cpu-common.h"
44 #include "sysemu/cpu-timers.h"
76 bool cpu_is_stopped(CPUState *cpu) in cpu_is_stopped() argument
78 return cpu->stopped || !runstate_is_running(); in cpu_is_stopped()
81 bool cpu_work_list_empty(CPUState *cpu) in cpu_work_list_empty() argument
83 return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list); in cpu_work_list_empty()
86 bool cpu_thread_is_idle(CPUState *cpu) in cpu_thread_is_idle() argument
88 if (cpu->stop || !cpu_work_list_empty(cpu)) { in cpu_thread_is_idle()
91 if (cpu_is_stopped(cpu)) { in cpu_thread_is_idle()
94 if (!cpu->halted || cpu_has_work(cpu)) { in cpu_thread_is_idle()
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/openbmc/linux/arch/arm64/kernel/
H A Dsmp.c23 #include <linux/cpu.h>
40 #include <asm/cpu.h>
83 static void ipi_setup(int cpu);
86 static void ipi_teardown(int cpu);
87 static int op_cpu_kill(unsigned int cpu);
89 static inline int op_cpu_kill(unsigned int cpu) in op_cpu_kill() argument
97 * Boot a secondary CPU, and assign it the specified idle task.
98 * This also gives us the initial stack to use for this CPU.
100 static int boot_secondary(unsigned int cpu, struct task_struct *idle) in boot_secondary() argument
102 const struct cpu_operations *ops = get_cpu_ops(cpu); in boot_secondary()
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