Lines Matching full:cpu
2 * QEMU AArch64 CPU
23 #include "cpu.h"
36 #include "cpu-features.h"
39 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_sve_finalize() argument
56 uint32_t vq_map = cpu->sve_vq.map; in arm_cpu_sve_finalize()
57 uint32_t vq_init = cpu->sve_vq.init; in arm_cpu_sve_finalize()
63 * CPU models specify a set of supported vector lengths which are in arm_cpu_sve_finalize()
70 cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu); in arm_cpu_sve_finalize()
71 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
73 assert(!cpu_isar_feature(aa64_sve, cpu)); in arm_cpu_sve_finalize()
77 vq_supported = cpu->sve_vq.supported; in arm_cpu_sve_finalize()
89 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { in arm_cpu_sve_finalize()
93 max_vq * 128, cpu->sve_max_vq, in arm_cpu_sve_finalize()
94 cpu->sve_max_vq * 128); in arm_cpu_sve_finalize()
108 } else if (cpu->sve_max_vq == 0) { in arm_cpu_sve_finalize()
112 if (!cpu_isar_feature(aa64_sve, cpu)) { in arm_cpu_sve_finalize()
117 cpu->isar.id_aa64zfr0 = 0; in arm_cpu_sve_finalize()
153 if (cpu->sve_max_vq != 0) { in arm_cpu_sve_finalize()
154 max_vq = cpu->sve_max_vq; in arm_cpu_sve_finalize()
183 if (cpu->sve_max_vq) { in arm_cpu_sve_finalize()
184 error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq); in arm_cpu_sve_finalize()
185 error_append_hint(errp, "This CPU does not support " in arm_cpu_sve_finalize()
188 "sve-max-vq with this CPU. Try " in arm_cpu_sve_finalize()
193 error_append_hint(errp, "This CPU does not support " in arm_cpu_sve_finalize()
229 if (!cpu_isar_feature(aa64_sve, cpu)) { in arm_cpu_sve_finalize()
233 error_append_hint(errp, "Add sve=on to the CPU property list.\n"); in arm_cpu_sve_finalize()
238 cpu->sve_max_vq = max_vq; in arm_cpu_sve_finalize()
239 cpu->sve_vq.map = vq_map; in arm_cpu_sve_finalize()
250 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_get_vq() local
253 bool sve = vq_map == &cpu->sve_vq; in cpu_arm_get_vq()
258 ? !cpu_isar_feature(aa64_sve, cpu) in cpu_arm_get_vq()
259 : !cpu_isar_feature(aa64_sme, cpu)) { in cpu_arm_get_vq()
284 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_get_sve() local
285 return cpu_isar_feature(aa64_sve, cpu); in cpu_arm_get_sve()
290 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_set_sve() local
298 t = cpu->isar.id_aa64pfr0; in cpu_arm_set_sve()
300 cpu->isar.id_aa64pfr0 = t; in cpu_arm_set_sve()
303 void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_sme_finalize() argument
305 uint32_t vq_map = cpu->sme_vq.map; in arm_cpu_sme_finalize()
306 uint32_t vq_init = cpu->sme_vq.init; in arm_cpu_sme_finalize()
307 uint32_t vq_supported = cpu->sme_vq.supported; in arm_cpu_sme_finalize()
311 if (!cpu_isar_feature(aa64_sme, cpu)) { in arm_cpu_sme_finalize()
312 cpu->isar.id_aa64smfr0 = 0; in arm_cpu_sme_finalize()
328 if (!cpu_isar_feature(aa64_sme, cpu)) { in arm_cpu_sme_finalize()
333 error_append_hint(errp, "Add sme=on to the CPU property list.\n"); in arm_cpu_sme_finalize()
339 cpu->sme_vq.map = vq_map; in arm_cpu_sme_finalize()
344 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_get_sme() local
345 return cpu_isar_feature(aa64_sme, cpu); in cpu_arm_get_sme()
350 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_set_sme() local
353 t = cpu->isar.id_aa64pfr1; in cpu_arm_set_sme()
355 cpu->isar.id_aa64pfr1 = t; in cpu_arm_set_sme()
360 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_get_sme_fa64() local
361 return cpu_isar_feature(aa64_sme, cpu) && in cpu_arm_get_sme_fa64()
362 cpu_isar_feature(aa64_sme_fa64, cpu); in cpu_arm_get_sme_fa64()
367 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_set_sme_fa64() local
370 t = cpu->isar.id_aa64smfr0; in cpu_arm_set_sme_fa64()
372 cpu->isar.id_aa64smfr0 = t; in cpu_arm_set_sme_fa64()
402 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_set_default_vec_len() local
404 (ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme"); in cpu_arm_set_default_vec_len()
434 ARMCPU *cpu = ARM_CPU(obj); in aarch64_add_sve_properties() local
443 cpu_arm_set_vq, NULL, &cpu->sve_vq); in aarch64_add_sve_properties()
451 &cpu->sve_default_vq); in aarch64_add_sve_properties()
457 ARMCPU *cpu = ARM_CPU(obj); in aarch64_add_sme_properties() local
468 cpu_arm_set_vq, NULL, &cpu->sme_vq); in aarch64_add_sme_properties()
476 &cpu->sme_default_vq); in aarch64_add_sme_properties()
480 void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_pauth_finalize() argument
482 ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); in arm_cpu_pauth_finalize()
493 isar1 = cpu->isar.id_aa64isar1; in arm_cpu_pauth_finalize()
499 isar2 = cpu->isar.id_aa64isar2; in arm_cpu_pauth_finalize()
508 if (cpu->prop_pauth) { in arm_cpu_pauth_finalize()
518 assert(!cpu->prop_pauth); in arm_cpu_pauth_finalize()
522 if (cpu->prop_pauth) { in arm_cpu_pauth_finalize()
523 if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { in arm_cpu_pauth_finalize()
529 if (cpu->prop_pauth_impdef) { in arm_cpu_pauth_finalize()
532 } else if (cpu->prop_pauth_qarma3) { in arm_cpu_pauth_finalize()
539 } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { in arm_cpu_pauth_finalize()
542 error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); in arm_cpu_pauth_finalize()
546 cpu->isar.id_aa64isar1 = isar1; in arm_cpu_pauth_finalize()
547 cpu->isar.id_aa64isar2 = isar2; in arm_cpu_pauth_finalize()
559 ARMCPU *cpu = ARM_CPU(obj); in aarch64_add_pauth_properties() local
567 * Note that prop_pauth is true whether the host CPU supports the in aarch64_add_pauth_properties()
572 cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); in aarch64_add_pauth_properties()
579 void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) in arm_cpu_lpa2_finalize() argument
584 * We only install the property for tcg -cpu max; this is the in arm_cpu_lpa2_finalize()
585 * only situation in which the cpu field can be true. in arm_cpu_lpa2_finalize()
587 if (!cpu->prop_lpa2) { in arm_cpu_lpa2_finalize()
591 t = cpu->isar.id_aa64mmfr0; in arm_cpu_lpa2_finalize()
596 cpu->isar.id_aa64mmfr0 = t; in arm_cpu_lpa2_finalize()
601 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a57_initfn() local
603 cpu->dtb_compatible = "arm,cortex-a57"; in aarch64_a57_initfn()
604 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a57_initfn()
605 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a57_initfn()
606 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a57_initfn()
607 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a57_initfn()
608 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a57_initfn()
609 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a57_initfn()
610 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a57_initfn()
611 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a57_initfn()
612 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a57_initfn()
613 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; in aarch64_a57_initfn()
614 cpu->midr = 0x411fd070; in aarch64_a57_initfn()
615 cpu->revidr = 0x00000000; in aarch64_a57_initfn()
616 cpu->reset_fpsid = 0x41034070; in aarch64_a57_initfn()
617 cpu->isar.mvfr0 = 0x10110222; in aarch64_a57_initfn()
618 cpu->isar.mvfr1 = 0x12111111; in aarch64_a57_initfn()
619 cpu->isar.mvfr2 = 0x00000043; in aarch64_a57_initfn()
620 cpu->ctr = 0x8444c004; in aarch64_a57_initfn()
621 cpu->reset_sctlr = 0x00c50838; in aarch64_a57_initfn()
622 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a57_initfn()
623 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a57_initfn()
624 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a57_initfn()
625 cpu->id_afr0 = 0x00000000; in aarch64_a57_initfn()
626 cpu->isar.id_mmfr0 = 0x10101105; in aarch64_a57_initfn()
627 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a57_initfn()
628 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a57_initfn()
629 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a57_initfn()
630 cpu->isar.id_isar0 = 0x02101110; in aarch64_a57_initfn()
631 cpu->isar.id_isar1 = 0x13112111; in aarch64_a57_initfn()
632 cpu->isar.id_isar2 = 0x21232042; in aarch64_a57_initfn()
633 cpu->isar.id_isar3 = 0x01112131; in aarch64_a57_initfn()
634 cpu->isar.id_isar4 = 0x00011142; in aarch64_a57_initfn()
635 cpu->isar.id_isar5 = 0x00011121; in aarch64_a57_initfn()
636 cpu->isar.id_isar6 = 0; in aarch64_a57_initfn()
637 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a57_initfn()
638 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a57_initfn()
639 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a57_initfn()
640 cpu->isar.id_aa64mmfr0 = 0x00001124; in aarch64_a57_initfn()
641 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a57_initfn()
642 cpu->isar.dbgdevid = 0x01110f13; in aarch64_a57_initfn()
643 cpu->isar.dbgdevid1 = 0x2; in aarch64_a57_initfn()
644 cpu->isar.reset_pmcr_el0 = 0x41013000; in aarch64_a57_initfn()
645 cpu->clidr = 0x0a200023; in aarch64_a57_initfn()
647 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a57_initfn()
649 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); in aarch64_a57_initfn()
651 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7); in aarch64_a57_initfn()
652 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a57_initfn()
653 cpu->gic_num_lrs = 4; in aarch64_a57_initfn()
654 cpu->gic_vpribits = 5; in aarch64_a57_initfn()
655 cpu->gic_vprebits = 5; in aarch64_a57_initfn()
656 cpu->gic_pribits = 5; in aarch64_a57_initfn()
657 define_cortex_a72_a57_a53_cp_reginfo(cpu); in aarch64_a57_initfn()
662 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a53_initfn() local
664 cpu->dtb_compatible = "arm,cortex-a53"; in aarch64_a53_initfn()
665 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a53_initfn()
666 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a53_initfn()
667 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a53_initfn()
668 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a53_initfn()
669 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a53_initfn()
670 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a53_initfn()
671 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a53_initfn()
672 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a53_initfn()
673 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a53_initfn()
674 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; in aarch64_a53_initfn()
675 cpu->midr = 0x410fd034; in aarch64_a53_initfn()
676 cpu->revidr = 0x00000100; in aarch64_a53_initfn()
677 cpu->reset_fpsid = 0x41034070; in aarch64_a53_initfn()
678 cpu->isar.mvfr0 = 0x10110222; in aarch64_a53_initfn()
679 cpu->isar.mvfr1 = 0x12111111; in aarch64_a53_initfn()
680 cpu->isar.mvfr2 = 0x00000043; in aarch64_a53_initfn()
681 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ in aarch64_a53_initfn()
682 cpu->reset_sctlr = 0x00c50838; in aarch64_a53_initfn()
683 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a53_initfn()
684 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a53_initfn()
685 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a53_initfn()
686 cpu->id_afr0 = 0x00000000; in aarch64_a53_initfn()
687 cpu->isar.id_mmfr0 = 0x10101105; in aarch64_a53_initfn()
688 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a53_initfn()
689 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a53_initfn()
690 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a53_initfn()
691 cpu->isar.id_isar0 = 0x02101110; in aarch64_a53_initfn()
692 cpu->isar.id_isar1 = 0x13112111; in aarch64_a53_initfn()
693 cpu->isar.id_isar2 = 0x21232042; in aarch64_a53_initfn()
694 cpu->isar.id_isar3 = 0x01112131; in aarch64_a53_initfn()
695 cpu->isar.id_isar4 = 0x00011142; in aarch64_a53_initfn()
696 cpu->isar.id_isar5 = 0x00011121; in aarch64_a53_initfn()
697 cpu->isar.id_isar6 = 0; in aarch64_a53_initfn()
698 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a53_initfn()
699 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a53_initfn()
700 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a53_initfn()
701 cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */ in aarch64_a53_initfn()
702 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a53_initfn()
703 cpu->isar.dbgdevid = 0x00110f13; in aarch64_a53_initfn()
704 cpu->isar.dbgdevid1 = 0x1; in aarch64_a53_initfn()
705 cpu->isar.reset_pmcr_el0 = 0x41033000; in aarch64_a53_initfn()
706 cpu->clidr = 0x0a200023; in aarch64_a53_initfn()
708 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a53_initfn()
710 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2); in aarch64_a53_initfn()
712 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); in aarch64_a53_initfn()
713 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a53_initfn()
714 cpu->gic_num_lrs = 4; in aarch64_a53_initfn()
715 cpu->gic_vpribits = 5; in aarch64_a53_initfn()
716 cpu->gic_vprebits = 5; in aarch64_a53_initfn()
717 cpu->gic_pribits = 5; in aarch64_a53_initfn()
718 define_cortex_a72_a57_a53_cp_reginfo(cpu); in aarch64_a53_initfn()
724 ARMCPU *cpu = ARM_CPU(obj); in aarch64_host_initfn() local
725 kvm_arm_set_cpu_features_from_host(cpu); in aarch64_host_initfn()
726 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { in aarch64_host_initfn()
731 ARMCPU *cpu = ARM_CPU(obj); in aarch64_host_initfn()
732 hvf_arm_set_cpu_features_from_host(cpu); in aarch64_host_initfn()
742 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ in aarch64_max_initfn()
751 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */ in aarch64_max_initfn()
768 ARMCPU *cpu = ARM_CPU(obj); in aarch64_cpu_get_aarch64() local
770 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_cpu_get_aarch64()
775 ARMCPU *cpu = ARM_CPU(obj); in aarch64_cpu_set_aarch64() local
788 unset_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_cpu_set_aarch64()
790 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_cpu_set_aarch64()