Lines Matching full:cpu
23 #include "cpu.h"
29 #include "cpu-features.h"
34 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
36 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
37 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
38 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
39 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
40 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
41 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a35_initfn()
42 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a35_initfn()
43 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a35_initfn()
44 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a35_initfn()
45 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a35_initfn()
48 cpu->midr = 0x411fd040; in aarch64_a35_initfn()
49 cpu->revidr = 0; in aarch64_a35_initfn()
50 cpu->ctr = 0x84448004; in aarch64_a35_initfn()
51 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a35_initfn()
52 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a35_initfn()
53 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a35_initfn()
54 cpu->id_afr0 = 0; in aarch64_a35_initfn()
55 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a35_initfn()
56 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a35_initfn()
57 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a35_initfn()
58 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a35_initfn()
59 cpu->isar.id_isar0 = 0x02101110; in aarch64_a35_initfn()
60 cpu->isar.id_isar1 = 0x13112111; in aarch64_a35_initfn()
61 cpu->isar.id_isar2 = 0x21232042; in aarch64_a35_initfn()
62 cpu->isar.id_isar3 = 0x01112131; in aarch64_a35_initfn()
63 cpu->isar.id_isar4 = 0x00011142; in aarch64_a35_initfn()
64 cpu->isar.id_isar5 = 0x00011121; in aarch64_a35_initfn()
65 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a35_initfn()
66 cpu->isar.id_aa64pfr1 = 0; in aarch64_a35_initfn()
67 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a35_initfn()
68 cpu->isar.id_aa64dfr1 = 0; in aarch64_a35_initfn()
69 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a35_initfn()
70 cpu->isar.id_aa64isar1 = 0; in aarch64_a35_initfn()
71 cpu->isar.id_aa64mmfr0 = 0x00101122; in aarch64_a35_initfn()
72 cpu->isar.id_aa64mmfr1 = 0; in aarch64_a35_initfn()
73 cpu->clidr = 0x0a200023; in aarch64_a35_initfn()
74 cpu->dcz_blocksize = 4; in aarch64_a35_initfn()
77 cpu->reset_sctlr = 0x00c50838; in aarch64_a35_initfn()
80 cpu->isar.reset_pmcr_el0 = 0x410a3000; in aarch64_a35_initfn()
84 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a35_initfn()
86 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); in aarch64_a35_initfn()
88 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); in aarch64_a35_initfn()
91 cpu->gic_num_lrs = 4; in aarch64_a35_initfn()
92 cpu->gic_vpribits = 5; in aarch64_a35_initfn()
93 cpu->gic_vprebits = 5; in aarch64_a35_initfn()
94 cpu->gic_pribits = 5; in aarch64_a35_initfn()
97 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a35_initfn()
99 cpu->isar.dbgdevid = 0x00110f13; in aarch64_a35_initfn()
101 cpu->isar.dbgdevid1 = 0x2; in aarch64_a35_initfn()
105 cpu->reset_fpsid = 0x41034043; in aarch64_a35_initfn()
108 cpu->isar.mvfr0 = 0x10110222; in aarch64_a35_initfn()
109 cpu->isar.mvfr1 = 0x12111111; in aarch64_a35_initfn()
110 cpu->isar.mvfr2 = 0x00000043; in aarch64_a35_initfn()
113 define_cortex_a72_a57_a53_cp_reginfo(cpu); in aarch64_a35_initfn()
119 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_get_sve_max_vq() local
123 if (!cpu_isar_feature(aa64_sve, cpu)) { in cpu_max_get_sve_max_vq()
126 value = cpu->sve_max_vq; in cpu_max_get_sve_max_vq()
134 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_set_sve_max_vq() local
148 cpu->sve_max_vq = max_vq; in cpu_max_set_sve_max_vq()
153 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_get_rme() local
154 return cpu_isar_feature(aa64_rme, cpu); in cpu_arm_get_rme()
159 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_set_rme() local
162 t = cpu->isar.id_aa64pfr0; in cpu_arm_set_rme()
164 cpu->isar.id_aa64pfr0 = t; in cpu_arm_set_rme()
170 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_set_l0gptsz() local
183 cpu->reset_l0gptsz = value - 30; in cpu_max_set_l0gptsz()
195 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_get_l0gptsz() local
196 uint32_t value = cpu->reset_l0gptsz + 30; in cpu_max_get_l0gptsz()
206 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a55_initfn() local
208 cpu->dtb_compatible = "arm,cortex-a55"; in aarch64_a55_initfn()
209 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a55_initfn()
210 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a55_initfn()
211 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a55_initfn()
212 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a55_initfn()
213 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a55_initfn()
214 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a55_initfn()
215 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a55_initfn()
216 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a55_initfn()
217 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a55_initfn()
220 cpu->clidr = 0x82000023; in aarch64_a55_initfn()
221 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ in aarch64_a55_initfn()
222 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a55_initfn()
223 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; in aarch64_a55_initfn()
224 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_a55_initfn()
225 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_a55_initfn()
226 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; in aarch64_a55_initfn()
227 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a55_initfn()
228 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_a55_initfn()
229 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; in aarch64_a55_initfn()
230 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; in aarch64_a55_initfn()
231 cpu->id_afr0 = 0x00000000; in aarch64_a55_initfn()
232 cpu->isar.id_dfr0 = 0x04010088; in aarch64_a55_initfn()
233 cpu->isar.id_isar0 = 0x02101110; in aarch64_a55_initfn()
234 cpu->isar.id_isar1 = 0x13112111; in aarch64_a55_initfn()
235 cpu->isar.id_isar2 = 0x21232042; in aarch64_a55_initfn()
236 cpu->isar.id_isar3 = 0x01112131; in aarch64_a55_initfn()
237 cpu->isar.id_isar4 = 0x00011142; in aarch64_a55_initfn()
238 cpu->isar.id_isar5 = 0x01011121; in aarch64_a55_initfn()
239 cpu->isar.id_isar6 = 0x00000010; in aarch64_a55_initfn()
240 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a55_initfn()
241 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a55_initfn()
242 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a55_initfn()
243 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a55_initfn()
244 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_a55_initfn()
245 cpu->isar.id_pfr0 = 0x10010131; in aarch64_a55_initfn()
246 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a55_initfn()
247 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a55_initfn()
248 cpu->midr = 0x412FD050; /* r2p0 */ in aarch64_a55_initfn()
249 cpu->revidr = 0; in aarch64_a55_initfn()
253 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a55_initfn()
255 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 2); in aarch64_a55_initfn()
257 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 512 * KiB, 7); in aarch64_a55_initfn()
260 cpu->reset_sctlr = 0x30c50838; in aarch64_a55_initfn()
263 cpu->gic_num_lrs = 4; in aarch64_a55_initfn()
264 cpu->gic_vpribits = 5; in aarch64_a55_initfn()
265 cpu->gic_vprebits = 5; in aarch64_a55_initfn()
266 cpu->gic_pribits = 5; in aarch64_a55_initfn()
268 cpu->isar.mvfr0 = 0x10110222; in aarch64_a55_initfn()
269 cpu->isar.mvfr1 = 0x13211111; in aarch64_a55_initfn()
270 cpu->isar.mvfr2 = 0x00000043; in aarch64_a55_initfn()
273 cpu->isar.reset_pmcr_el0 = 0x410b3000; in aarch64_a55_initfn()
278 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a72_initfn() local
280 cpu->dtb_compatible = "arm,cortex-a72"; in aarch64_a72_initfn()
281 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a72_initfn()
282 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a72_initfn()
283 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a72_initfn()
284 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a72_initfn()
285 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a72_initfn()
286 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a72_initfn()
287 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a72_initfn()
288 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a72_initfn()
289 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a72_initfn()
290 cpu->midr = 0x410fd083; in aarch64_a72_initfn()
291 cpu->revidr = 0x00000000; in aarch64_a72_initfn()
292 cpu->reset_fpsid = 0x41034080; in aarch64_a72_initfn()
293 cpu->isar.mvfr0 = 0x10110222; in aarch64_a72_initfn()
294 cpu->isar.mvfr1 = 0x12111111; in aarch64_a72_initfn()
295 cpu->isar.mvfr2 = 0x00000043; in aarch64_a72_initfn()
296 cpu->ctr = 0x8444c004; in aarch64_a72_initfn()
297 cpu->reset_sctlr = 0x00c50838; in aarch64_a72_initfn()
298 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a72_initfn()
299 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a72_initfn()
300 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a72_initfn()
301 cpu->id_afr0 = 0x00000000; in aarch64_a72_initfn()
302 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a72_initfn()
303 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a72_initfn()
304 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a72_initfn()
305 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a72_initfn()
306 cpu->isar.id_isar0 = 0x02101110; in aarch64_a72_initfn()
307 cpu->isar.id_isar1 = 0x13112111; in aarch64_a72_initfn()
308 cpu->isar.id_isar2 = 0x21232042; in aarch64_a72_initfn()
309 cpu->isar.id_isar3 = 0x01112131; in aarch64_a72_initfn()
310 cpu->isar.id_isar4 = 0x00011142; in aarch64_a72_initfn()
311 cpu->isar.id_isar5 = 0x00011121; in aarch64_a72_initfn()
312 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a72_initfn()
313 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a72_initfn()
314 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a72_initfn()
315 cpu->isar.id_aa64mmfr0 = 0x00001124; in aarch64_a72_initfn()
316 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a72_initfn()
317 cpu->isar.dbgdevid = 0x01110f13; in aarch64_a72_initfn()
318 cpu->isar.dbgdevid1 = 0x2; in aarch64_a72_initfn()
319 cpu->isar.reset_pmcr_el0 = 0x41023000; in aarch64_a72_initfn()
320 cpu->clidr = 0x0a200023; in aarch64_a72_initfn()
322 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7); in aarch64_a72_initfn()
324 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2); in aarch64_a72_initfn()
326 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7); in aarch64_a72_initfn()
327 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a72_initfn()
328 cpu->gic_num_lrs = 4; in aarch64_a72_initfn()
329 cpu->gic_vpribits = 5; in aarch64_a72_initfn()
330 cpu->gic_vprebits = 5; in aarch64_a72_initfn()
331 cpu->gic_pribits = 5; in aarch64_a72_initfn()
332 define_cortex_a72_a57_a53_cp_reginfo(cpu); in aarch64_a72_initfn()
337 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a76_initfn() local
339 cpu->dtb_compatible = "arm,cortex-a76"; in aarch64_a76_initfn()
340 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a76_initfn()
341 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a76_initfn()
342 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a76_initfn()
343 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a76_initfn()
344 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a76_initfn()
345 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a76_initfn()
346 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a76_initfn()
347 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a76_initfn()
348 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a76_initfn()
351 cpu->clidr = 0x82000023; in aarch64_a76_initfn()
352 cpu->ctr = 0x8444C004; in aarch64_a76_initfn()
353 cpu->dcz_blocksize = 4; in aarch64_a76_initfn()
354 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; in aarch64_a76_initfn()
355 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_a76_initfn()
356 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_a76_initfn()
357 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; in aarch64_a76_initfn()
358 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a76_initfn()
359 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_a76_initfn()
360 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ in aarch64_a76_initfn()
361 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; in aarch64_a76_initfn()
362 cpu->id_afr0 = 0x00000000; in aarch64_a76_initfn()
363 cpu->isar.id_dfr0 = 0x04010088; in aarch64_a76_initfn()
364 cpu->isar.id_isar0 = 0x02101110; in aarch64_a76_initfn()
365 cpu->isar.id_isar1 = 0x13112111; in aarch64_a76_initfn()
366 cpu->isar.id_isar2 = 0x21232042; in aarch64_a76_initfn()
367 cpu->isar.id_isar3 = 0x01112131; in aarch64_a76_initfn()
368 cpu->isar.id_isar4 = 0x00010142; in aarch64_a76_initfn()
369 cpu->isar.id_isar5 = 0x01011121; in aarch64_a76_initfn()
370 cpu->isar.id_isar6 = 0x00000010; in aarch64_a76_initfn()
371 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a76_initfn()
372 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a76_initfn()
373 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a76_initfn()
374 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a76_initfn()
375 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_a76_initfn()
376 cpu->isar.id_pfr0 = 0x10010131; in aarch64_a76_initfn()
377 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_a76_initfn()
378 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a76_initfn()
379 cpu->midr = 0x414fd0b1; /* r4p1 */ in aarch64_a76_initfn()
380 cpu->revidr = 0; in aarch64_a76_initfn()
384 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); in aarch64_a76_initfn()
386 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); in aarch64_a76_initfn()
388 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB, 7); in aarch64_a76_initfn()
391 cpu->reset_sctlr = 0x30c50838; in aarch64_a76_initfn()
394 cpu->gic_num_lrs = 4; in aarch64_a76_initfn()
395 cpu->gic_vpribits = 5; in aarch64_a76_initfn()
396 cpu->gic_vprebits = 5; in aarch64_a76_initfn()
397 cpu->gic_pribits = 5; in aarch64_a76_initfn()
400 cpu->isar.mvfr0 = 0x10110222; in aarch64_a76_initfn()
401 cpu->isar.mvfr1 = 0x13211111; in aarch64_a76_initfn()
402 cpu->isar.mvfr2 = 0x00000043; in aarch64_a76_initfn()
405 cpu->isar.reset_pmcr_el0 = 0x410b3000; in aarch64_a76_initfn()
410 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a64fx_initfn() local
412 cpu->dtb_compatible = "arm,a64fx"; in aarch64_a64fx_initfn()
413 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a64fx_initfn()
414 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a64fx_initfn()
415 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a64fx_initfn()
416 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a64fx_initfn()
417 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a64fx_initfn()
418 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a64fx_initfn()
419 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a64fx_initfn()
420 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a64fx_initfn()
421 cpu->midr = 0x461f0010; in aarch64_a64fx_initfn()
422 cpu->revidr = 0x00000000; in aarch64_a64fx_initfn()
423 cpu->ctr = 0x86668006; in aarch64_a64fx_initfn()
424 cpu->reset_sctlr = 0x30000180; in aarch64_a64fx_initfn()
425 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ in aarch64_a64fx_initfn()
426 cpu->isar.id_aa64pfr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
427 cpu->isar.id_aa64dfr0 = 0x0000000010305408; in aarch64_a64fx_initfn()
428 cpu->isar.id_aa64dfr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
429 cpu->id_aa64afr0 = 0x0000000000000000; in aarch64_a64fx_initfn()
430 cpu->id_aa64afr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
431 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; in aarch64_a64fx_initfn()
432 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; in aarch64_a64fx_initfn()
433 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; in aarch64_a64fx_initfn()
434 cpu->isar.id_aa64isar0 = 0x0000000010211120; in aarch64_a64fx_initfn()
435 cpu->isar.id_aa64isar1 = 0x0000000000010001; in aarch64_a64fx_initfn()
436 cpu->isar.id_aa64zfr0 = 0x0000000000000000; in aarch64_a64fx_initfn()
437 cpu->clidr = 0x0000000080000023; in aarch64_a64fx_initfn()
439 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7); in aarch64_a64fx_initfn()
441 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 2); in aarch64_a64fx_initfn()
443 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 256, 8 * MiB, 7); in aarch64_a64fx_initfn()
444 cpu->dcz_blocksize = 6; /* 256 bytes */ in aarch64_a64fx_initfn()
445 cpu->gic_num_lrs = 4; in aarch64_a64fx_initfn()
446 cpu->gic_vpribits = 5; in aarch64_a64fx_initfn()
447 cpu->gic_vprebits = 5; in aarch64_a64fx_initfn()
448 cpu->gic_pribits = 5; in aarch64_a64fx_initfn()
452 cpu->sve_vq.supported = (1 << 0) /* 128bit */ in aarch64_a64fx_initfn()
456 cpu->isar.reset_pmcr_el0 = 0x46014040; in aarch64_a64fx_initfn()
550 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) in define_neoverse_n1_cp_reginfo() argument
552 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); in define_neoverse_n1_cp_reginfo()
571 static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) in define_neoverse_v1_cp_reginfo() argument
577 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); in define_neoverse_v1_cp_reginfo()
578 define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); in define_neoverse_v1_cp_reginfo()
583 ARMCPU *cpu = ARM_CPU(obj); in aarch64_neoverse_n1_initfn() local
585 cpu->dtb_compatible = "arm,neoverse-n1"; in aarch64_neoverse_n1_initfn()
586 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_neoverse_n1_initfn()
587 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_neoverse_n1_initfn()
588 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_neoverse_n1_initfn()
589 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_neoverse_n1_initfn()
590 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_neoverse_n1_initfn()
591 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_neoverse_n1_initfn()
592 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_neoverse_n1_initfn()
593 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_n1_initfn()
594 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_neoverse_n1_initfn()
597 cpu->clidr = 0x82000023; in aarch64_neoverse_n1_initfn()
598 cpu->ctr = 0x8444c004; in aarch64_neoverse_n1_initfn()
599 cpu->dcz_blocksize = 4; in aarch64_neoverse_n1_initfn()
600 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; in aarch64_neoverse_n1_initfn()
601 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_neoverse_n1_initfn()
602 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_neoverse_n1_initfn()
603 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; in aarch64_neoverse_n1_initfn()
604 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_n1_initfn()
605 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_neoverse_n1_initfn()
606 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ in aarch64_neoverse_n1_initfn()
607 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; in aarch64_neoverse_n1_initfn()
608 cpu->id_afr0 = 0x00000000; in aarch64_neoverse_n1_initfn()
609 cpu->isar.id_dfr0 = 0x04010088; in aarch64_neoverse_n1_initfn()
610 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_n1_initfn()
611 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_n1_initfn()
612 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_n1_initfn()
613 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_n1_initfn()
614 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_n1_initfn()
615 cpu->isar.id_isar5 = 0x01011121; in aarch64_neoverse_n1_initfn()
616 cpu->isar.id_isar6 = 0x00000010; in aarch64_neoverse_n1_initfn()
617 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_n1_initfn()
618 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_n1_initfn()
619 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_n1_initfn()
620 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_n1_initfn()
621 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_neoverse_n1_initfn()
622 cpu->isar.id_pfr0 = 0x10010131; in aarch64_neoverse_n1_initfn()
623 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_n1_initfn()
624 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_n1_initfn()
625 cpu->midr = 0x414fd0c1; /* r4p1 */ in aarch64_neoverse_n1_initfn()
626 cpu->revidr = 0; in aarch64_neoverse_n1_initfn()
630 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 7); in aarch64_neoverse_n1_initfn()
632 cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, 2); in aarch64_neoverse_n1_initfn()
634 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 1 * MiB, 7); in aarch64_neoverse_n1_initfn()
637 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_n1_initfn()
640 cpu->gic_num_lrs = 4; in aarch64_neoverse_n1_initfn()
641 cpu->gic_vpribits = 5; in aarch64_neoverse_n1_initfn()
642 cpu->gic_vprebits = 5; in aarch64_neoverse_n1_initfn()
643 cpu->gic_pribits = 5; in aarch64_neoverse_n1_initfn()
646 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_n1_initfn()
647 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_n1_initfn()
648 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_n1_initfn()
651 cpu->isar.reset_pmcr_el0 = 0x410c3000; in aarch64_neoverse_n1_initfn()
653 define_neoverse_n1_cp_reginfo(cpu); in aarch64_neoverse_n1_initfn()
658 ARMCPU *cpu = ARM_CPU(obj); in aarch64_neoverse_v1_initfn() local
660 cpu->dtb_compatible = "arm,neoverse-v1"; in aarch64_neoverse_v1_initfn()
661 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_neoverse_v1_initfn()
662 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_neoverse_v1_initfn()
663 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_neoverse_v1_initfn()
664 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_neoverse_v1_initfn()
665 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_neoverse_v1_initfn()
666 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_neoverse_v1_initfn()
667 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_neoverse_v1_initfn()
668 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_v1_initfn()
669 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_neoverse_v1_initfn()
672 cpu->clidr = 0x82000023; in aarch64_neoverse_v1_initfn()
673 cpu->ctr = 0xb444c004; /* With DIC and IDC set */ in aarch64_neoverse_v1_initfn()
674 cpu->dcz_blocksize = 4; in aarch64_neoverse_v1_initfn()
675 cpu->id_aa64afr0 = 0x00000000; in aarch64_neoverse_v1_initfn()
676 cpu->id_aa64afr1 = 0x00000000; in aarch64_neoverse_v1_initfn()
677 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; in aarch64_neoverse_v1_initfn()
678 cpu->isar.id_aa64dfr1 = 0x00000000; in aarch64_neoverse_v1_initfn()
679 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ in aarch64_neoverse_v1_initfn()
680 cpu->isar.id_aa64isar1 = 0x0011100001211032ull; in aarch64_neoverse_v1_initfn()
681 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; in aarch64_neoverse_v1_initfn()
682 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_v1_initfn()
683 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull; in aarch64_neoverse_v1_initfn()
684 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ in aarch64_neoverse_v1_initfn()
685 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; in aarch64_neoverse_v1_initfn()
686 cpu->id_afr0 = 0x00000000; in aarch64_neoverse_v1_initfn()
687 cpu->isar.id_dfr0 = 0x15011099; in aarch64_neoverse_v1_initfn()
688 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_v1_initfn()
689 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_v1_initfn()
690 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_v1_initfn()
691 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_v1_initfn()
692 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_v1_initfn()
693 cpu->isar.id_isar5 = 0x11011121; in aarch64_neoverse_v1_initfn()
694 cpu->isar.id_isar6 = 0x01100111; in aarch64_neoverse_v1_initfn()
695 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_v1_initfn()
696 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_v1_initfn()
697 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_v1_initfn()
698 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_v1_initfn()
699 cpu->isar.id_mmfr4 = 0x01021110; in aarch64_neoverse_v1_initfn()
700 cpu->isar.id_pfr0 = 0x21110131; in aarch64_neoverse_v1_initfn()
701 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_v1_initfn()
702 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_v1_initfn()
703 cpu->midr = 0x411FD402; /* r1p2 */ in aarch64_neoverse_v1_initfn()
704 cpu->revidr = 0; in aarch64_neoverse_v1_initfn()
717 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); in aarch64_neoverse_v1_initfn()
719 cpu->ccsidr[1] = cpu->ccsidr[0]; in aarch64_neoverse_v1_initfn()
721 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 1 * MiB, 0); in aarch64_neoverse_v1_initfn()
724 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_v1_initfn()
727 cpu->gic_num_lrs = 4; in aarch64_neoverse_v1_initfn()
728 cpu->gic_vpribits = 5; in aarch64_neoverse_v1_initfn()
729 cpu->gic_vprebits = 5; in aarch64_neoverse_v1_initfn()
730 cpu->gic_pribits = 5; in aarch64_neoverse_v1_initfn()
733 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_v1_initfn()
734 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_v1_initfn()
735 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_v1_initfn()
738 cpu->isar.id_aa64zfr0 = 0x0000100000100000; in aarch64_neoverse_v1_initfn()
739 cpu->sve_vq.supported = (1 << 0) /* 128bit */ in aarch64_neoverse_v1_initfn()
743 cpu->isar.reset_pmcr_el0 = 0x41213000; in aarch64_neoverse_v1_initfn()
745 define_neoverse_v1_cp_reginfo(cpu); in aarch64_neoverse_v1_initfn()
856 * or anything else with cpu internal memory.
884 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a710_initfn() local
886 cpu->dtb_compatible = "arm,cortex-a710"; in aarch64_a710_initfn()
887 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a710_initfn()
888 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a710_initfn()
889 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a710_initfn()
890 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a710_initfn()
891 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a710_initfn()
892 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a710_initfn()
893 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a710_initfn()
894 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a710_initfn()
895 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a710_initfn()
898 cpu->midr = 0x412FD471; /* r2p1 */ in aarch64_a710_initfn()
899 cpu->revidr = 0; in aarch64_a710_initfn()
900 cpu->isar.id_pfr0 = 0x21110131; in aarch64_a710_initfn()
901 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_a710_initfn()
902 cpu->isar.id_dfr0 = 0x16011099; in aarch64_a710_initfn()
903 cpu->id_afr0 = 0; in aarch64_a710_initfn()
904 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a710_initfn()
905 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a710_initfn()
906 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a710_initfn()
907 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a710_initfn()
908 cpu->isar.id_isar0 = 0x02101110; in aarch64_a710_initfn()
909 cpu->isar.id_isar1 = 0x13112111; in aarch64_a710_initfn()
910 cpu->isar.id_isar2 = 0x21232042; in aarch64_a710_initfn()
911 cpu->isar.id_isar3 = 0x01112131; in aarch64_a710_initfn()
912 cpu->isar.id_isar4 = 0x00010142; in aarch64_a710_initfn()
913 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ in aarch64_a710_initfn()
914 cpu->isar.id_mmfr4 = 0x21021110; in aarch64_a710_initfn()
915 cpu->isar.id_isar6 = 0x01111111; in aarch64_a710_initfn()
916 cpu->isar.mvfr0 = 0x10110222; in aarch64_a710_initfn()
917 cpu->isar.mvfr1 = 0x13211111; in aarch64_a710_initfn()
918 cpu->isar.mvfr2 = 0x00000043; in aarch64_a710_initfn()
919 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a710_initfn()
920 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ in aarch64_a710_initfn()
921 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; in aarch64_a710_initfn()
922 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ in aarch64_a710_initfn()
923 cpu->isar.id_aa64dfr0 = 0x000011f010305619ull; in aarch64_a710_initfn()
924 cpu->isar.id_aa64dfr1 = 0; in aarch64_a710_initfn()
925 cpu->id_aa64afr0 = 0; in aarch64_a710_initfn()
926 cpu->id_aa64afr1 = 0; in aarch64_a710_initfn()
927 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ in aarch64_a710_initfn()
928 cpu->isar.id_aa64isar1 = 0x0010111101211052ull; in aarch64_a710_initfn()
929 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; in aarch64_a710_initfn()
930 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a710_initfn()
931 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; in aarch64_a710_initfn()
932 cpu->clidr = 0x0000001482000023ull; in aarch64_a710_initfn()
933 cpu->gm_blocksize = 4; in aarch64_a710_initfn()
934 cpu->ctr = 0x000000049444c004ull; in aarch64_a710_initfn()
935 cpu->dcz_blocksize = 4; in aarch64_a710_initfn()
939 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ in aarch64_a710_initfn()
942 cpu->gic_num_lrs = 4; in aarch64_a710_initfn()
943 cpu->gic_vpribits = 5; in aarch64_a710_initfn()
944 cpu->gic_vprebits = 5; in aarch64_a710_initfn()
945 cpu->gic_pribits = 5; in aarch64_a710_initfn()
948 cpu->sve_vq.supported = 1 << 0; /* 128bit */ in aarch64_a710_initfn()
958 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); in aarch64_a710_initfn()
960 cpu->ccsidr[1] = cpu->ccsidr[0]; in aarch64_a710_initfn()
962 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); in aarch64_a710_initfn()
965 cpu->reset_sctlr = 0x30c50838; in aarch64_a710_initfn()
967 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); in aarch64_a710_initfn()
985 ARMCPU *cpu = ARM_CPU(obj); in aarch64_neoverse_n2_initfn() local
987 cpu->dtb_compatible = "arm,neoverse-n2"; in aarch64_neoverse_n2_initfn()
988 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_neoverse_n2_initfn()
989 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_neoverse_n2_initfn()
990 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_neoverse_n2_initfn()
991 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_neoverse_n2_initfn()
992 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_neoverse_n2_initfn()
993 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_neoverse_n2_initfn()
994 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_neoverse_n2_initfn()
995 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_n2_initfn()
996 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_neoverse_n2_initfn()
999 cpu->midr = 0x410FD493; /* r0p3 */ in aarch64_neoverse_n2_initfn()
1000 cpu->revidr = 0; in aarch64_neoverse_n2_initfn()
1001 cpu->isar.id_pfr0 = 0x21110131; in aarch64_neoverse_n2_initfn()
1002 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_n2_initfn()
1003 cpu->isar.id_dfr0 = 0x16011099; in aarch64_neoverse_n2_initfn()
1004 cpu->id_afr0 = 0; in aarch64_neoverse_n2_initfn()
1005 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_n2_initfn()
1006 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_n2_initfn()
1007 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_n2_initfn()
1008 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_n2_initfn()
1009 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_n2_initfn()
1010 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_n2_initfn()
1011 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_n2_initfn()
1012 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_n2_initfn()
1013 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_n2_initfn()
1014 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ in aarch64_neoverse_n2_initfn()
1015 cpu->isar.id_mmfr4 = 0x01021110; in aarch64_neoverse_n2_initfn()
1016 cpu->isar.id_isar6 = 0x01111111; in aarch64_neoverse_n2_initfn()
1017 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_n2_initfn()
1018 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_n2_initfn()
1019 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_n2_initfn()
1020 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_n2_initfn()
1021 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ in aarch64_neoverse_n2_initfn()
1022 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; in aarch64_neoverse_n2_initfn()
1023 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ in aarch64_neoverse_n2_initfn()
1024 cpu->isar.id_aa64dfr0 = 0x000011f210305619ull; in aarch64_neoverse_n2_initfn()
1025 cpu->isar.id_aa64dfr1 = 0; in aarch64_neoverse_n2_initfn()
1026 cpu->id_aa64afr0 = 0; in aarch64_neoverse_n2_initfn()
1027 cpu->id_aa64afr1 = 0; in aarch64_neoverse_n2_initfn()
1028 cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */ in aarch64_neoverse_n2_initfn()
1029 cpu->isar.id_aa64isar1 = 0x0011111101211052ull; in aarch64_neoverse_n2_initfn()
1030 cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull; in aarch64_neoverse_n2_initfn()
1031 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_n2_initfn()
1032 cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull; in aarch64_neoverse_n2_initfn()
1033 cpu->clidr = 0x0000001482000023ull; in aarch64_neoverse_n2_initfn()
1034 cpu->gm_blocksize = 4; in aarch64_neoverse_n2_initfn()
1035 cpu->ctr = 0x00000004b444c004ull; in aarch64_neoverse_n2_initfn()
1036 cpu->dcz_blocksize = 4; in aarch64_neoverse_n2_initfn()
1040 cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */ in aarch64_neoverse_n2_initfn()
1043 cpu->gic_num_lrs = 4; in aarch64_neoverse_n2_initfn()
1044 cpu->gic_vpribits = 5; in aarch64_neoverse_n2_initfn()
1045 cpu->gic_vprebits = 5; in aarch64_neoverse_n2_initfn()
1046 cpu->gic_pribits = 5; in aarch64_neoverse_n2_initfn()
1049 cpu->sve_vq.supported = 1 << 0; /* 128bit */ in aarch64_neoverse_n2_initfn()
1059 cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 4, 64, 64 * KiB, 0); in aarch64_neoverse_n2_initfn()
1061 cpu->ccsidr[1] = cpu->ccsidr[0]; in aarch64_neoverse_n2_initfn()
1063 cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_CCIDX, 8, 64, 512 * KiB, 0); in aarch64_neoverse_n2_initfn()
1065 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_n2_initfn()
1071 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); in aarch64_neoverse_n2_initfn()
1072 define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo); in aarch64_neoverse_n2_initfn()
1079 * -cpu max: a CPU with as many features enabled as our emulation supports.
1080 * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
1085 ARMCPU *cpu = ARM_CPU(obj); in aarch64_max_tcg_initfn() local
1091 * to because we started with aarch64_a57_initfn(). A 'max' CPU might in aarch64_max_tcg_initfn()
1093 * because it is our "may change" CPU type we are OK with it not being in aarch64_max_tcg_initfn()
1096 unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_max_tcg_initfn()
1099 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real in aarch64_max_tcg_initfn()
1107 * code needs to distinguish this QEMU CPU from other software in aarch64_max_tcg_initfn()
1115 cpu->midr = t; in aarch64_max_tcg_initfn()
1121 u = cpu->clidr; in aarch64_max_tcg_initfn()
1124 cpu->clidr = u; in aarch64_max_tcg_initfn()
1131 t = cpu->ctr; in aarch64_max_tcg_initfn()
1134 cpu->ctr = t; in aarch64_max_tcg_initfn()
1136 t = cpu->isar.id_aa64isar0; in aarch64_max_tcg_initfn()
1151 cpu->isar.id_aa64isar0 = t; in aarch64_max_tcg_initfn()
1153 t = cpu->isar.id_aa64isar1; in aarch64_max_tcg_initfn()
1166 cpu->isar.id_aa64isar1 = t; in aarch64_max_tcg_initfn()
1168 t = cpu->isar.id_aa64isar2; in aarch64_max_tcg_initfn()
1172 cpu->isar.id_aa64isar2 = t; in aarch64_max_tcg_initfn()
1174 t = cpu->isar.id_aa64pfr0; in aarch64_max_tcg_initfn()
1183 cpu->isar.id_aa64pfr0 = t; in aarch64_max_tcg_initfn()
1185 t = cpu->isar.id_aa64pfr1; in aarch64_max_tcg_initfn()
1198 cpu->isar.id_aa64pfr1 = t; in aarch64_max_tcg_initfn()
1200 t = cpu->isar.id_aa64mmfr0; in aarch64_max_tcg_initfn()
1208 cpu->isar.id_aa64mmfr0 = t; in aarch64_max_tcg_initfn()
1210 t = cpu->isar.id_aa64mmfr1; in aarch64_max_tcg_initfn()
1222 cpu->isar.id_aa64mmfr1 = t; in aarch64_max_tcg_initfn()
1224 t = cpu->isar.id_aa64mmfr2; in aarch64_max_tcg_initfn()
1238 cpu->isar.id_aa64mmfr2 = t; in aarch64_max_tcg_initfn()
1240 t = cpu->isar.id_aa64mmfr3; in aarch64_max_tcg_initfn()
1242 cpu->isar.id_aa64mmfr3 = t; in aarch64_max_tcg_initfn()
1244 t = cpu->isar.id_aa64zfr0; in aarch64_max_tcg_initfn()
1254 cpu->isar.id_aa64zfr0 = t; in aarch64_max_tcg_initfn()
1256 t = cpu->isar.id_aa64dfr0; in aarch64_max_tcg_initfn()
1260 cpu->isar.id_aa64dfr0 = t; in aarch64_max_tcg_initfn()
1262 t = cpu->isar.id_aa64smfr0; in aarch64_max_tcg_initfn()
1270 cpu->isar.id_aa64smfr0 = t; in aarch64_max_tcg_initfn()
1273 aa32_max_features(cpu); in aarch64_max_tcg_initfn()
1277 * For usermode -cpu max we can use a larger and more efficient DCZ in aarch64_max_tcg_initfn()
1280 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ in aarch64_max_tcg_initfn()
1281 cpu->dcz_blocksize = 7; /* 512 bytes */ in aarch64_max_tcg_initfn()
1283 cpu->gm_blocksize = 6; /* 256 bytes */ in aarch64_max_tcg_initfn()
1285 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); in aarch64_max_tcg_initfn()
1286 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; in aarch64_max_tcg_initfn()