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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmediatek-dwmac.yaml54 - description: RMII reference clock provided by MAC
81 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
91 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
96 mediatek,rmii-rxc:
99 If present, indicates that the RMII reference clock, which is from external
102 mediatek,rmii-clk-from-mac:
105 If present, indicates that MAC provides the RMII reference clock, which
114 which is from external PHYs in RMII case, and it rarely happen.
[all …]
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
H A Dnxp,tja11xx.yaml34 nxp,rmii-refclk-in:
38 in RMII mode. This clock signal is provided by the PHY and is
45 interface reference clock input when RMII mode enabled.
47 reference clock output when RMII mode enabled.
63 nxp,rmii-refclk-in;
H A Dactions,owl-emac.yaml14 It provides the RMII and SMII interfaces and is compliant with the
44 - const: rmii
81 clock-names = "eth", "rmii";
83 phy-mode = "rmii";
H A Dcpsw-phy-sel.txt13 -rmii-clock-ext : If present, the driver will configure the RMII
29 rmii-clock-ext;
H A Dfaraday,ftgmac100.yaml36 - description: RMII RCLK gate for AST2500/2600
47 - rmii
54 rmii (100bT) but kept as a separate property in case NC-SI grows support
H A Dmediatek,star-emac.yaml51 mediatek,rmii-rxc:
54 If present, indicates that the RMII reference clock, which is from external
97 phy-mode = "rmii";
H A Dlpc-eth.txt10 absent, "rmii" is assumed.
26 phy-mode = "rmii";
H A Ddavinci_emac.txt23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
/openbmc/openbmc/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/
H A Dibm.json84 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
85 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
101 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
102 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
H A Dips.json91 "MAC 1 RMII mode": { "value": "RMII/NCSI" },
92 "MAC 2 RMII mode": { "value": "RMII/NCSI" },
108 "MAC 3 RMII mode": { "value": "RMII/NCSI" },
109 "MAC 4 RMII mode": { "value": "RMII/NCSI" },
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-mediatek.c149 /* 550ps per stage for MII/RMII */ in mt2712_delay_ps2stage()
174 /* 550ps per stage for MII/RMII */ in mt2712_delay_stage2ps()
211 /* case 1: mac provides the rmii reference clock, in mt2712_set_delay()
224 /* case 2: the rmii reference clock is from external phy, in mt2712_set_delay()
231 /* the rmii reference clock from outside is connected in mt2712_set_delay()
239 /* the rmii reference clock from outside is connected in mt2712_set_delay()
362 /* case 1: mac provides the rmii reference clock, in mt8195_set_delay()
381 /* case 2: the rmii reference clock is from external phy, in mt8195_set_delay()
388 /* the rmii reference clock from outside is connected in mt8195_set_delay()
399 /* the rmii reference clock from outside is connected in mt8195_set_delay()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
358 phy-connection-type = "rmii";
362 /* Eth-1 (UCC5, MDIO 0x08, RMII) */
374 phy-connection-type = "rmii";
378 /* Eth-2 (UCC6, MDIO 0x09, RMII) */
390 phy-connection-type = "rmii";
394 /* Eth-3 (UCC7, MDIO 0x0a, RMII) */
406 phy-connection-type = "rmii";
410 /* Eth-4 (UCC8, MDIO 0x0b, RMII) */
422 phy-connection-type = "rmii";
[all …]
/openbmc/u-boot/board/freescale/mpc832xemds/
H A DREADME46 ENET3/4 RMII mode settings:
48 J2 1-2 (RMII mode)
49 J3 1-2 (RMII mode)
54 JP2 removed (ETH4/2 RMII)
55 JP3 removed (ETH3 RMII)
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dboard_common.c18 * RMII daughtercard workaround
24 * @brief workaround for RMII daughtercard, reset PHY manually
26 * workaround for Aspeed RMII daughtercard, reset Eth PHY by GPO F0 and F2
27 * Where GPO F0 controls the reset signal of RMII PHY 1 and 2.
28 * Where GPO F2 controls the reset signal of RMII PHY 3 and 4.
38 debug("RMII workaround: reset PHY manually\n"); in reset_eth_phy()
/openbmc/u-boot/include/configs/
H A DMPC8569MDS.h284 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
304 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
306 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
325 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
327 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
346 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
348 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
367 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
369 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
/openbmc/linux/drivers/pinctrl/qcom/
H A Dpinctrl-ipq4019.c509 QCA_PIN_FUNCTION(rmii),
587 PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
589 PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA,
591 PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
593 PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
595 PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA,
597 PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA,
599 PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
601 PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
603 PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-kontron-sl-common.dtsi37 phy-mode = "rmii";
49 clock-names = "rmii-ref";
55 phy-mode = "rmii";
H A Dimx53-kp-hsc.dts18 fixed-link { /* RMII fixed link to LAN9303 */
35 port@0 { /* RMII fixed link to master */
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
38 - description: GMAC0 RMII reference
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x25ek.dts20 phy-mode = "rmii";
25 phy-mode = "rmii";
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x25ek.dts22 phy-mode = "rmii";
27 phy-mode = "rmii";
/openbmc/linux/drivers/net/ethernet/arc/
H A Demac_rockchip.c120 /* RK3036/RK3066/RK3188 SoCs only support RMII */ in emac_rockchip_probe()
183 /* Set RMII mode */ in emac_rockchip_probe()
194 /* RMII interface needs always a rate of 50MHz */ in emac_rockchip_probe()
217 /* RMII TX/RX needs always a rate of 25MHz */ in emac_rockchip_probe()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-gmii-sel.yaml15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
31 | | | RMII <------->
154 - RMII refclk mode
/openbmc/linux/Documentation/networking/dsa/
H A Dsja1105.rst329 RMII PHY role and out-of-band signaling
332 In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by
337 On the other hand, the SJA1105 is only binary configurable - when in the RMII
339 happening it must be put in RMII PHY role.
341 In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0].
344 mechanism defined by the RMII spec.
346 clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105
355 The take-away is that in RMII mode, the SJA1105 must be let to drive the

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