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/openbmc/linux/drivers/staging/rtl8712/
H A Drtl8712_fifoctrl_bitdef.h11 #define _PSTX_MSK 0xF0
13 #define _PSRX_MSK 0x0F
14 #define _PSRX_SHT 0
27 #define _RXFF0_EMPTY BIT(0)
30 #define _BKQ_EMPTY_TH_MSK 0x0F0000
32 #define _BEQ_EMPTY_TH_MSK 0x00F000
34 #define _VIQ_EMPTY_TH_MSK 0x000F00
36 #define _VOQ_EMPTY_TH_MSK 0x0000F0
38 #define _BMCQ_EMPTY_TH_MSK 0x00000F
39 #define _BMCQ_EMPTY_TH_SHT 0
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
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H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
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/openbmc/linux/arch/mips/lantiq/
H A Dearly_printk.c12 #define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))
14 #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
16 #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))
18 #define TXMASK 0x3F00
/openbmc/u-boot/board/toradex/apalis-tk1/
H A Das3722_init.h8 #define AS3722_I2C_ADDR 0x80
10 #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
11 #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
12 #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
13 #define AS3722_SDCONTROL_REG 0x4D
15 #define AS3722_LDO1VOLTAGE_REG 0x11 /* VDD_SDMMC1 */
16 #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC3 */
18 #define AS3722_LDCONTROL_REG 0x4E
20 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
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/openbmc/u-boot/board/nvidia/venice2/
H A Das3722_init.h9 #define AS3722_I2C_ADDR 0x80
11 #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
12 #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
13 #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
14 #define AS3722_SDCONTROL_REG 0x4D
16 #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
17 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
18 #define AS3722_LDCONTROL_REG 0x4E
21 #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
23 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
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/openbmc/qemu/hw/misc/
H A Darm_sysctl.c23 #define LOCK_VALUE 0xa05f
84 #define BOARD_ID_PB926 0x100
85 #define BOARD_ID_EB 0x140
86 #define BOARD_ID_PBA8 0x178
87 #define BOARD_ID_PBX 0x182
88 #define BOARD_ID_VEXPRESS 0x190
93 return (s->sys_id >> 16) & 0xfff; in board_id()
101 s->leds = 0; in arm_sysctl_reset()
102 s->lockval = 0; in arm_sysctl_reset()
103 s->cfgdata1 = 0; in arm_sysctl_reset()
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
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/openbmc/linux/drivers/mmc/host/
H A Dcb710-mmc.h35 #define CB710_MMC_DATA_PORT 0x00
37 #define CB710_MMC_CONFIG_PORT 0x04
38 #define CB710_MMC_CONFIG0_PORT 0x04
39 #define CB710_MMC_CONFIG1_PORT 0x05
40 #define CB710_MMC_C1_4BIT_DATA_BUS 0x40
41 #define CB710_MMC_CONFIG2_PORT 0x06
42 #define CB710_MMC_C2_READ_PIO_SIZE_MASK 0x0F /* N-1 */
43 #define CB710_MMC_CONFIG3_PORT 0x07
45 #define CB710_MMC_CONFIGB_PORT 0x08
47 #define CB710_MMC_IRQ_ENABLE_PORT 0x0C
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igbvf/
H A Ddefines.h12 #define E1000_IVAR_VALID 0x80
15 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
16 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
17 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
18 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
19 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
20 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
21 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
22 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
23 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/linux/arch/mips/sgi-ip22/
H A Dip22-berr.c39 sgimc->cstat = sgimc->gstat = 0; in save_and_clear_buserr()
42 #define GIO_ERRMASK 0xff00
43 #define CPU_ERRMASK 0x3f00
50 printk(KERN_ERR "HPC3 Bus Error 0x%x:<id=0x%x,%s,lane=0x%x>\n", in print_buserr()
59 printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n", in print_buserr()
69 printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n", in print_buserr()
96 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", in ip22_be_interrupt()
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/openbmc/u-boot/drivers/spi/
H A Dich.h24 uint32_t bfpr; /* 0x00 */
29 uint32_t fdata[16]; /* 0x10 */
30 uint32_t frap; /* 0x50 */
33 uint32_t pr[5]; /* 0x74 */
35 uint8_t ssfs; /* 0x90 */
37 uint16_t preop; /* 0x94 */
39 uint8_t opmenu[8]; /* 0x98 */
42 uint32_t fdoc; /* 0xb0 */
45 uint32_t afc; /* 0xc0 */
49 uint32_t fpb; /* 0xd0 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml60 const: 0
63 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
70 minimum: 0
125 reg = <0xa60 0x20>,
126 <0x3f00 0xc0>,
127 <0x2000 0x1000>;
133 #size-cells = <0>;
142 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
143 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
151 fsl,tx-ts-mask = <0x00000000 0x00000055>;
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/openbmc/u-boot/board/lego/ev3/
H A Dlegoev3.c37 #define EEPROM_I2C_ADDR 0x50
38 #define EEPROM_REV_OFFSET 0x3F00
39 #define EEPROM_MAC_OFFSET 0x3F06
53 /* Add slot-0 to mmc subsystem */ in board_mmc_init()
89 if ((buf[0] ^ buf[1]) == 0xFF) in get_board_rev()
90 board_rev = buf[0]; in get_board_rev()
119 nr[0] = buf[5]; in get_board_serial()
124 nr[0] = buf[1]; in get_board_serial()
125 nr[1] = buf[0]; in get_board_serial()
126 nr[2] = 0; in get_board_serial()
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dlantiq.c34 #define LTQ_ASC_TBUF (0x0020 + 3)
35 #define LTQ_ASC_RBUF (0x0024 + 3)
37 #define LTQ_ASC_TBUF 0x0020
38 #define LTQ_ASC_RBUF 0x0024
40 #define LTQ_ASC_FSTAT 0x0048
41 #define LTQ_ASC_WHBSTATE 0x0018
42 #define LTQ_ASC_STATE 0x0014
43 #define LTQ_ASC_IRNCR 0x00F8
44 #define LTQ_ASC_CLC 0x0000
45 #define LTQ_ASC_ID 0x0008
[all …]
/openbmc/linux/include/linux/mfd/wm8350/
H A Drtc.h16 #define WM8350_RTC_SECONDS_MINUTES 0x10
17 #define WM8350_RTC_HOURS_DAY 0x11
18 #define WM8350_RTC_DATE_MONTH 0x12
19 #define WM8350_RTC_YEAR 0x13
20 #define WM8350_ALARM_SECONDS_MINUTES 0x14
21 #define WM8350_ALARM_HOURS_DAY 0x15
22 #define WM8350_ALARM_DATE_MONTH 0x16
23 #define WM8350_RTC_TIME_CONTROL 0x17
26 * R16 (0x10) - RTC Seconds/Minutes
28 #define WM8350_RTC_MINS_MASK 0x7F00
[all …]
/openbmc/linux/sound/soc/samsung/
H A Di2s-regs.h12 #define I2SCON 0x0
13 #define I2SMOD 0x4
14 #define I2SFIC 0x8
15 #define I2SPSR 0xc
16 #define I2STXD 0x10
17 #define I2SRXD 0x14
18 #define I2SFICS 0x18
19 #define I2STXDS 0x1c
20 #define I2SAHB 0x20
21 #define I2SSTR0 0x24
[all …]

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