1*a9b12132SHerve Codina# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*a9b12132SHerve Codina%YAML 1.2 3*a9b12132SHerve Codina--- 4*a9b12132SHerve Codina$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml# 5*a9b12132SHerve Codina$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a9b12132SHerve Codina 7*a9b12132SHerve Codinatitle: PowerQUICC CPM QUICC Multichannel Controller (QMC) 8*a9b12132SHerve Codina 9*a9b12132SHerve Codinamaintainers: 10*a9b12132SHerve Codina - Herve Codina <herve.codina@bootlin.com> 11*a9b12132SHerve Codina 12*a9b12132SHerve Codinadescription: 13*a9b12132SHerve Codina The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one 14*a9b12132SHerve Codina serial controller using the same TDM physical interface routed from TSA. 15*a9b12132SHerve Codina 16*a9b12132SHerve Codinaproperties: 17*a9b12132SHerve Codina compatible: 18*a9b12132SHerve Codina items: 19*a9b12132SHerve Codina - enum: 20*a9b12132SHerve Codina - fsl,mpc885-scc-qmc 21*a9b12132SHerve Codina - fsl,mpc866-scc-qmc 22*a9b12132SHerve Codina - const: fsl,cpm1-scc-qmc 23*a9b12132SHerve Codina 24*a9b12132SHerve Codina reg: 25*a9b12132SHerve Codina items: 26*a9b12132SHerve Codina - description: SCC (Serial communication controller) register base 27*a9b12132SHerve Codina - description: SCC parameter ram base 28*a9b12132SHerve Codina - description: Dual port ram base 29*a9b12132SHerve Codina 30*a9b12132SHerve Codina reg-names: 31*a9b12132SHerve Codina items: 32*a9b12132SHerve Codina - const: scc_regs 33*a9b12132SHerve Codina - const: scc_pram 34*a9b12132SHerve Codina - const: dpram 35*a9b12132SHerve Codina 36*a9b12132SHerve Codina interrupts: 37*a9b12132SHerve Codina maxItems: 1 38*a9b12132SHerve Codina description: SCC interrupt line in the CPM interrupt controller 39*a9b12132SHerve Codina 40*a9b12132SHerve Codina fsl,tsa-serial: 41*a9b12132SHerve Codina $ref: /schemas/types.yaml#/definitions/phandle-array 42*a9b12132SHerve Codina items: 43*a9b12132SHerve Codina - items: 44*a9b12132SHerve Codina - description: phandle to TSA node 45*a9b12132SHerve Codina - enum: [1, 2, 3] 46*a9b12132SHerve Codina description: | 47*a9b12132SHerve Codina TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these 48*a9b12132SHerve Codina values) 49*a9b12132SHerve Codina - 1: SCC2 50*a9b12132SHerve Codina - 2: SCC3 51*a9b12132SHerve Codina - 3: SCC4 52*a9b12132SHerve Codina description: 53*a9b12132SHerve Codina Should be a phandle/number pair. The phandle to TSA node and the TSA 54*a9b12132SHerve Codina serial interface to use. 55*a9b12132SHerve Codina 56*a9b12132SHerve Codina '#address-cells': 57*a9b12132SHerve Codina const: 1 58*a9b12132SHerve Codina 59*a9b12132SHerve Codina '#size-cells': 60*a9b12132SHerve Codina const: 0 61*a9b12132SHerve Codina 62*a9b12132SHerve CodinapatternProperties: 63*a9b12132SHerve Codina '^channel@([0-9]|[1-5][0-9]|6[0-3])$': 64*a9b12132SHerve Codina description: 65*a9b12132SHerve Codina A channel managed by this controller 66*a9b12132SHerve Codina type: object 67*a9b12132SHerve Codina 68*a9b12132SHerve Codina properties: 69*a9b12132SHerve Codina reg: 70*a9b12132SHerve Codina minimum: 0 71*a9b12132SHerve Codina maximum: 63 72*a9b12132SHerve Codina description: 73*a9b12132SHerve Codina The channel number 74*a9b12132SHerve Codina 75*a9b12132SHerve Codina fsl,operational-mode: 76*a9b12132SHerve Codina $ref: /schemas/types.yaml#/definitions/string 77*a9b12132SHerve Codina enum: [transparent, hdlc] 78*a9b12132SHerve Codina default: transparent 79*a9b12132SHerve Codina description: | 80*a9b12132SHerve Codina The channel operational mode 81*a9b12132SHerve Codina - hdlc: The channel handles HDLC frames 82*a9b12132SHerve Codina - transparent: The channel handles raw data without any processing 83*a9b12132SHerve Codina 84*a9b12132SHerve Codina fsl,reverse-data: 85*a9b12132SHerve Codina $ref: /schemas/types.yaml#/definitions/flag 86*a9b12132SHerve Codina description: 87*a9b12132SHerve Codina The bit order as seen on the channels is reversed, 88*a9b12132SHerve Codina transmitting/receiving the MSB of each octet first. 89*a9b12132SHerve Codina This flag is used only in 'transparent' mode. 90*a9b12132SHerve Codina 91*a9b12132SHerve Codina fsl,tx-ts-mask: 92*a9b12132SHerve Codina $ref: /schemas/types.yaml#/definitions/uint64 93*a9b12132SHerve Codina description: 94*a9b12132SHerve Codina Channel assigned Tx time-slots within the Tx time-slots routed by the 95*a9b12132SHerve Codina TSA to this cell. 96*a9b12132SHerve Codina 97*a9b12132SHerve Codina fsl,rx-ts-mask: 98*a9b12132SHerve Codina $ref: /schemas/types.yaml#/definitions/uint64 99*a9b12132SHerve Codina description: 100*a9b12132SHerve Codina Channel assigned Rx time-slots within the Rx time-slots routed by the 101*a9b12132SHerve Codina TSA to this cell. 102*a9b12132SHerve Codina 103*a9b12132SHerve Codina required: 104*a9b12132SHerve Codina - reg 105*a9b12132SHerve Codina - fsl,tx-ts-mask 106*a9b12132SHerve Codina - fsl,rx-ts-mask 107*a9b12132SHerve Codina 108*a9b12132SHerve Codinarequired: 109*a9b12132SHerve Codina - compatible 110*a9b12132SHerve Codina - reg 111*a9b12132SHerve Codina - reg-names 112*a9b12132SHerve Codina - interrupts 113*a9b12132SHerve Codina - fsl,tsa-serial 114*a9b12132SHerve Codina - '#address-cells' 115*a9b12132SHerve Codina - '#size-cells' 116*a9b12132SHerve Codina 117*a9b12132SHerve CodinaadditionalProperties: false 118*a9b12132SHerve Codina 119*a9b12132SHerve Codinaexamples: 120*a9b12132SHerve Codina - | 121*a9b12132SHerve Codina #include <dt-bindings/soc/cpm1-fsl,tsa.h> 122*a9b12132SHerve Codina 123*a9b12132SHerve Codina qmc@a60 { 124*a9b12132SHerve Codina compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc"; 125*a9b12132SHerve Codina reg = <0xa60 0x20>, 126*a9b12132SHerve Codina <0x3f00 0xc0>, 127*a9b12132SHerve Codina <0x2000 0x1000>; 128*a9b12132SHerve Codina reg-names = "scc_regs", "scc_pram", "dpram"; 129*a9b12132SHerve Codina interrupts = <27>; 130*a9b12132SHerve Codina interrupt-parent = <&CPM_PIC>; 131*a9b12132SHerve Codina 132*a9b12132SHerve Codina #address-cells = <1>; 133*a9b12132SHerve Codina #size-cells = <0>; 134*a9b12132SHerve Codina 135*a9b12132SHerve Codina fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>; 136*a9b12132SHerve Codina 137*a9b12132SHerve Codina channel@16 { 138*a9b12132SHerve Codina /* Ch16 : First 4 even TS from all routed from TSA */ 139*a9b12132SHerve Codina reg = <16>; 140*a9b12132SHerve Codina fsl,mode = "transparent"; 141*a9b12132SHerve Codina fsl,reverse-data; 142*a9b12132SHerve Codina fsl,tx-ts-mask = <0x00000000 0x000000aa>; 143*a9b12132SHerve Codina fsl,rx-ts-mask = <0x00000000 0x000000aa>; 144*a9b12132SHerve Codina }; 145*a9b12132SHerve Codina 146*a9b12132SHerve Codina channel@17 { 147*a9b12132SHerve Codina /* Ch17 : First 4 odd TS from all routed from TSA */ 148*a9b12132SHerve Codina reg = <17>; 149*a9b12132SHerve Codina fsl,mode = "transparent"; 150*a9b12132SHerve Codina fsl,reverse-data; 151*a9b12132SHerve Codina fsl,tx-ts-mask = <0x00000000 0x00000055>; 152*a9b12132SHerve Codina fsl,rx-ts-mask = <0x00000000 0x00000055>; 153*a9b12132SHerve Codina }; 154*a9b12132SHerve Codina 155*a9b12132SHerve Codina channel@19 { 156*a9b12132SHerve Codina /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */ 157*a9b12132SHerve Codina reg = <19>; 158*a9b12132SHerve Codina fsl,mode = "hdlc"; 159*a9b12132SHerve Codina fsl,tx-ts-mask = <0x00000000 0x0000ff00>; 160*a9b12132SHerve Codina fsl,rx-ts-mask = <0x00000000 0x0000ff00>; 161*a9b12132SHerve Codina }; 162*a9b12132SHerve Codina }; 163