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/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/openbmc/linux/drivers/net/ethernet/qualcomm/
H A Dqca_7k.h35 #define QCA7K_SPI_WRITE (0 << 15)
37 #define QCA7K_SPI_EXTERNAL (0 << 14)
41 #define QCASPI_HW_BUF_LEN 0xC5B
44 #define SPI_REG_BFR_SIZE 0x0100
45 #define SPI_REG_WRBUF_SPC_AVA 0x0200
46 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
47 #define SPI_REG_SPI_CONFIG 0x0400
48 #define SPI_REG_SPI_STATUS 0x0500
49 #define SPI_REG_INTR_CAUSE 0x0C00
50 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dctrl_pex.h12 #define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
17 #define MISC_REGS_OFFSET 0x18200
19 #define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
21 #define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
22 (0x40000 + ((if) - 1) * 0x4000) : \
23 0x80000)
25 #define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
26 #define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
27 #define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
28 #define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
/openbmc/linux/drivers/block/
H A Dswim_asm.S17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_5_4_sm6125.h13 .max_mixer_blendstages = 0x6,
24 .base = 0x0, .len = 0x45c,
25 .features = 0,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
36 .base = 0x1000, .len = 0x1e0,
41 .base = 0x1200, .len = 0x1e0,
46 .base = 0x1400, .len = 0x1e0,
51 .base = 0x1600, .len = 0x1e0,
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c103 .id = 0,
109 .offset = 0xc00,
115 .offset = 0xd00,
121 .offset = 0xe00,
146 .base = 0x1c00,
162 .base = 0x1e00,
175 .base = 0x1a00,
188 .base = 0x1800,
198 .base = 0x1000,
202 .layer_sel_id = 0,
[all …]
/openbmc/qemu/scsi/
H A Dutils.c23 if ((buf[0] >> 5) == 0 && buf[4] == 0) { in scsi_data_cdb_xfer()
32 switch (buf[0] >> 5) { in scsi_cdb_xfer()
33 case 0: in scsi_cdb_xfer()
39 return ldl_be_p(&buf[10]) & 0xffffffffULL; in scsi_cdb_xfer()
41 return ldl_be_p(&buf[6]) & 0xffffffffULL; in scsi_cdb_xfer()
52 switch (buf[0] >> 5) { in scsi_cmd_lba()
53 case 0: in scsi_cmd_lba()
54 lba = ldl_be_p(&buf[0]) & 0x1fffff; in scsi_cmd_lba()
59 lba = ldl_be_p(&buf[2]) & 0xffffffffULL; in scsi_cmd_lba()
75 switch (buf[0] >> 5) { in scsi_cdb_length()
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/openbmc/linux/sound/soc/amd/acp/
H A Dacp-rembrandt.c29 #define MP1_C2PMSG_69 0x3B10A14
30 #define MP1_C2PMSG_85 0x3B10A54
31 #define MP1_C2PMSG_93 0x3B10A74
32 #define HOST_BRIDGE_ID 0x14B5
35 .offset = 0,
39 .irq_reg_offset = 0x1a00,
40 .i2s_pin_cfg_offset = 0x1440,
41 .i2s_mode = 0x0a,
42 .scratch_reg_offset = 0x12800,
43 .sram_pte_offset = 0x03802800,
[all …]
/openbmc/linux/arch/x86/boot/
H A Dvideo-vga.c18 { VIDEO_80x25, 80, 25, 0 },
19 { VIDEO_8POINT, 80, 50, 0 },
20 { VIDEO_80x43, 80, 43, 0 },
21 { VIDEO_80x28, 80, 28, 0 },
22 { VIDEO_80x30, 80, 30, 0 },
23 { VIDEO_80x34, 80, 34, 0 },
24 { VIDEO_80x60, 80, 60, 0 },
28 { VIDEO_80x25, 80, 25, 0 },
29 { VIDEO_8POINT, 80, 43, 0 },
33 { VIDEO_80x25, 80, 25, 0 },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/openbmc/qemu/hw/display/
H A Dati_dbg.c11 {"MM_INDEX", 0x0000},
12 {"MM_DATA", 0x0004},
13 {"CLOCK_CNTL_INDEX", 0x0008},
14 {"CLOCK_CNTL_DATA", 0x000c},
15 {"BIOS_0_SCRATCH", 0x0010},
16 {"BUS_CNTL", 0x0030},
17 {"BUS_CNTL1", 0x0034},
18 {"GEN_INT_CNTL", 0x0040},
19 {"GEN_INT_STATUS", 0x0044},
20 {"CRTC_GEN_CNTL", 0x0050},
[all …]
H A Dati_regs.h17 * 0x0000-0x00ff Misc regs also accessible via io and mmio space
18 * 0x0100-0x0eff Misc regs only accessible via mmio
19 * 0x0f00-0x0fff Read-only copy of PCI config regs
20 * 0x1000-0x13ff Concurrent Command Engine (CCE) regs
21 * 0x1400-0x1fff GUI (drawing engine) regs
29 #define MM_INDEX 0x0000
30 #define MM_DATA 0x0004
31 #define CLOCK_CNTL_INDEX 0x0008
32 #define CLOCK_CNTL_DATA 0x000c
33 #define BIOS_0_SCRATCH 0x0010
[all …]
/openbmc/linux/arch/arm/plat-orion/
H A Dpcie.c22 #define PCIE_DEV_ID_OFF 0x0000
23 #define PCIE_CMD_OFF 0x0004
24 #define PCIE_DEV_REV_OFF 0x0008
25 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
26 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
27 #define PCIE_HEADER_LOG_4_OFF 0x0128
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
29 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
30 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
31 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_catalog.c264 .base = 0xa00, .len = 0xa0,}, \
267 .base = 0x1a00, .len = 0x100,}, \
283 .base = 0xa00, .len = 0xa0,}, \
286 .base = 0x1a00, .len = 0x100,}, \
306 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
309 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
312 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
315 _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3,
357 SSPP_SCALER_VER(3, 0));
361 SSPP_SCALER_VER(3, 0),
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dboard_env_spec.h12 #define MV_6710_DEV_ID 0x6710
14 #define MV_6710_Z1_REV 0x0
19 #define MV_78130_DEV_ID 0x7813
20 #define MV_78160_DEV_ID 0x7816
21 #define MV_78230_DEV_ID 0x7823
22 #define MV_78260_DEV_ID 0x7826
23 #define MV_78460_DEV_ID 0x7846
24 #define MV_78000_DEV_ID 0x7888
26 #define MV_FPGA_DEV_ID 0x2107
28 #define MV_78XX0_Z1_REV 0x0
[all …]
/openbmc/linux/include/video/
H A Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/
H A Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/openbmc/linux/drivers/net/ethernet/sis/
H A Dsis190.c40 #define PHY_ID_ANY 0x1f
41 #define MII_REG_ANY 0x1f
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
84 TxControl = 0x00,
85 TxDescStartAddr = 0x04,
[all …]

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