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Searched defs:mask2 (Results 1 – 25 of 58) sorted by relevance

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/openbmc/linux/tools/testing/selftests/bpf/progs/
H A Dcpumask_success.c27 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
181 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
245 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
292 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
334 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
467 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
/openbmc/linux/arch/mips/sgi-ip22/
H A Dip22-int.c114 u8 mask2; in indy_local0_irqdispatch() local
136 u8 mask2; in indy_local1_irqdispatch() local
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c290 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2()
300 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3()
312 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4()
326 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5()
342 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6()
360 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get7()
380 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get8()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
213 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c210 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
224 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
222 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
223 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
234 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
229 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/net/hamradio/
H A Dhdlcdrv.c159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
/openbmc/linux/lib/
H A Dcpumask_kunit.c26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ argument
/openbmc/linux/include/linux/
H A Dcpumask.h332 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
350 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
367 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
758 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
H A Dar9003_mac.c187 u32 mask2 = 0; in ar9003_hw_get_isr() local
/openbmc/linux/fs/affs/
H A Dbitmap.c122 u32 blk, bmap, bit, mask, mask2, tmp; in affs_alloc_block() local
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/
H A Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/
H A Dirq_service_dcn303.c119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/
H A Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/
H A Dirq_service_dcn20.c205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c152 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
/openbmc/linux/sound/soc/codecs/
H A Dcs35l33.c271 unsigned int mask2 = CS35L33_SDOUT_3ST_TDM; in cs35l33_sdout_event() local
964 unsigned int sticky_val1, sticky_val2, current_val, mask1, mask2; in cs35l33_irq_thread() local
/openbmc/linux/arch/alpha/kernel/
H A Dsys_titan.c69 unsigned long mask0, mask1, mask2, mask3, dummy; in titan_update_irq_hw() local
/openbmc/linux/drivers/media/test-drivers/vidtv/
H A Dvidtv_pes.c89 u64 mask2; in vidtv_pes_write_pts_dts() local
/openbmc/linux/drivers/soc/fsl/qe/
H A Dgpio.c242 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local

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