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Searched refs:tx_fifo (Results 1 – 25 of 38) sorted by relevance

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/openbmc/qemu/hw/ssi/
H A Dpl022.c102 val = s->tx_fifo[i]; in pl022_xfer()
184 s->tx_fifo[s->tx_fifo_head] = value & s->bitmask; in pl022_write()
239 s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) || in pl022_post_load()
264 VMSTATE_UINT16(tx_fifo[0], PL022State),
266 VMSTATE_UINT16(tx_fifo[1], PL022State),
268 VMSTATE_UINT16(tx_fifo[2], PL022State),
270 VMSTATE_UINT16(tx_fifo[3], PL022State),
272 VMSTATE_UINT16(tx_fifo[4], PL022State),
274 VMSTATE_UINT16(tx_fifo[5], PL022State),
276 VMSTATE_UINT16(tx_fifo[6], PL022State),
[all …]
H A Dimx_spi.c66 VMSTATE_FIFO32(tx_fifo, IMXSPIState),
76 fifo32_reset(&s->tx_fifo); in imx_spi_txfifo_reset()
105 if (fifo32_is_empty(&s->tx_fifo)) { in imx_spi_update_irq()
111 if (fifo32_is_full(&s->tx_fifo)) { in imx_spi_update_irq()
168 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
170 while (!fifo32_is_empty(&s->tx_fifo)) { in imx_spi_flush_txfifo()
183 tx = fifo32_pop(&s->tx_fifo); in imx_spi_flush_txfifo()
224 if (fifo32_is_empty(&s->tx_fifo)) { in imx_spi_flush_txfifo()
232 fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo)); in imx_spi_flush_txfifo()
362 if (fifo32_is_full(&s->tx_fifo)) { in imx_spi_write()
[all …]
H A Dbcm2835_spi.c74 if (fifo8_is_full(&s->tx_fifo)) { in bcm2835_spi_update_tx_flags()
81 if (fifo8_is_empty(&s->tx_fifo) && s->cs & BCM2835_SPI_CS_TA) { in bcm2835_spi_update_tx_flags()
92 while (!fifo8_is_empty(&s->tx_fifo) && !fifo8_is_full(&s->rx_fifo)) { in bcm2835_spi_flush_tx_fifo()
93 tx_byte = fifo8_pop(&s->tx_fifo); in bcm2835_spi_flush_tx_fifo()
161 fifo8_reset(&s->tx_fifo); in bcm2835_spi_write()
191 fifo8_push(&s->tx_fifo, value & 0xff); in bcm2835_spi_write()
233 fifo8_create(&s->tx_fifo, FIFO_SIZE); in bcm2835_spi_realize()
240 fifo8_reset(&s->tx_fifo); in bcm2835_spi_reset()
256 VMSTATE_FIFO8(tx_fifo, BCM2835SPIState),
H A Dallwinner-a10-spi.c175 fifo8_reset(&s->tx_fifo); in allwinner_a10_spi_txfifo_reset()
248 if (fifo8_is_empty(&s->tx_fifo)) { in allwinner_a10_spi_update_irq()
254 if (fifo8_num_free(&s->tx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 2)) { in allwinner_a10_spi_update_irq()
260 if (fifo8_num_free(&s->tx_fifo) >= (AW_A10_SPI_FIFO_SIZE >> 1)) { in allwinner_a10_spi_update_irq()
266 if (fifo8_num_used(&s->tx_fifo) <= (AW_A10_SPI_FIFO_SIZE >> 2)) { in allwinner_a10_spi_update_irq()
292 trace_allwinner_a10_spi_flush_txfifo_begin(fifo8_num_used(&s->tx_fifo), in allwinner_a10_spi_flush_txfifo()
295 while (!fifo8_is_empty(&s->tx_fifo)) { in allwinner_a10_spi_flush_txfifo()
296 uint8_t tx = fifo8_pop(&s->tx_fifo); in allwinner_a10_spi_flush_txfifo()
335 if (fifo8_is_empty(&s->tx_fifo)) { in allwinner_a10_spi_flush_txfifo()
340 trace_allwinner_a10_spi_flush_txfifo_end(fifo8_num_used(&s->tx_fifo), in allwinner_a10_spi_flush_txfifo()
[all …]
H A Dsifive_spi.c64 fifo8_reset(&s->tx_fifo); in sifive_spi_txfifo_reset()
93 if (fifo8_num_used(&s->tx_fifo) < s->regs[R_TXMARK]) { in sifive_spi_update_irq()
135 while (!fifo8_is_empty(&s->tx_fifo)) { in sifive_spi_flush_txfifo()
136 tx = fifo8_pop(&s->tx_fifo); in sifive_spi_flush_txfifo()
194 if (fifo8_is_full(&s->tx_fifo)) { in sifive_spi_read()
261 if (!fifo8_is_full(&s->tx_fifo)) { in sifive_spi_write()
262 fifo8_push(&s->tx_fifo, (uint8_t)value); in sifive_spi_write()
327 fifo8_create(&s->tx_fifo, FIFO_CAPACITY); in sifive_spi_realize()
H A Dmss-spi.c89 fifo32_reset(&s->tx_fifo); in txfifo_reset()
230 while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) { in spi_flush_txfifo()
235 tx = fifo32_pop(&s->tx_fifo); in spi_flush_txfifo()
279 if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { in spi_write()
283 fifo32_push(&s->tx_fifo, value); in spi_write()
284 if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) { in spi_write()
286 } else if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) { in spi_write()
385 fifo32_create(&s->tx_fifo, FIFO_CAPACITY); in mss_spi_realize()
394 VMSTATE_FIFO32(tx_fifo, MSSSpiState),
H A Dxilinx_spi.c100 Fifo8 tx_fifo; member
107 fifo8_reset(&s->tx_fifo); in txfifo_reset()
182 while (!fifo8_is_empty(&s->tx_fifo)) { in spi_flush_txfifo()
183 tx = (uint32_t)fifo8_pop(&s->tx_fifo); in spi_flush_txfifo()
264 fifo8_push(&s->tx_fifo, (uint8_t)value); in spi_write()
265 if (fifo8_is_full(&s->tx_fifo)) { in spi_write()
361 fifo8_create(&s->tx_fifo, FIFO_CAPACITY); in xilinx_spi_realize()
370 VMSTATE_FIFO8(tx_fifo, XilinxSPI),
H A Dxilinx_spips.c308 fifo8_is_empty(&s->tx_fifo)) { in xilinx_spips_update_cs_lines()
322 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) | in xilinx_spips_update_ixr()
323 (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) | in xilinx_spips_update_ixr()
324 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0); in xilinx_spips_update_ixr()
617 if (fifo8_is_empty(&s->tx_fifo)) { in xilinx_spips_flush_txfifo()
623 if (!fifo8_is_empty(&s->tx_fifo)) { in xilinx_spips_flush_txfifo()
624 tx_rx[i] = fifo8_pop(&s->tx_fifo); in xilinx_spips_flush_txfifo()
629 tx = fifo8_pop(&s->tx_fifo); in xilinx_spips_flush_txfifo()
638 tx = fifo8_pop(&s->tx_fifo); in xilinx_spips_flush_txfifo()
764 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) { in xilinx_spips_check_zero_pump()
[all …]
H A Dpnv_spi.c199 payload_len = fifo8_num_used(&s->tx_fifo); in transfer()
205 } else if (!fifo8_is_empty(&s->tx_fifo)) { in transfer()
206 tx = (tx << 8) | fifo8_pop(&s->tx_fifo); in transfer()
227 fifo8_reset(&s->tx_fifo); in transfer()
377 if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn1()
379 fifo8_push(&s->tx_fifo, n1_byte); in operation_shiftn1()
409 } else if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn1()
411 fifo8_push(&s->tx_fifo, 0xff); in operation_shiftn1()
455 trace_pnv_spi_tx_request("Shifting N1 frame", fifo8_num_used(&s->tx_fifo)); in operation_shiftn1()
594 if (!fifo8_is_full(&s->tx_fifo)) { in operation_shiftn2()
[all …]
H A Dxlnx-versal-ospi.c633 while (!fifo8_is_empty(&s->tx_fifo)) { in ospi_flush_txfifo()
634 uint32_t tx_rx = fifo8_pop(&s->tx_fifo); in ospi_flush_txfifo()
647 fifo8_push(&s->tx_fifo, flash_addr >> 24); in ospi_tx_fifo_push_address_raw()
650 fifo8_push(&s->tx_fifo, flash_addr >> 16); in ospi_tx_fifo_push_address_raw()
653 fifo8_push(&s->tx_fifo, flash_addr >> 8); in ospi_tx_fifo_push_address_raw()
655 fifo8_push(&s->tx_fifo, flash_addr); in ospi_tx_fifo_push_address_raw()
678 fifo8_reset(&s->tx_fifo); in ospi_tx_fifo_push_rd_op_addr()
681 fifo8_push(&s->tx_fifo, inst_code); in ospi_tx_fifo_push_rd_op_addr()
696 fifo8_push(&s->tx_fifo, data >> shift); in ospi_tx_fifo_push_stig_wr_data()
713 fifo8_push(&s->tx_fifo, 0); in ospi_tx_fifo_push_stig_rd_data()
[all …]
H A Dibex_spi_host.c124 fifo8_reset(&s->tx_fifo); in ibex_spi_txfifo_reset()
245 if (fifo8_is_empty(&s->tx_fifo)) { in ibex_spi_host_transfer()
254 tx = fifo8_pop(&s->tx_fifo); in ibex_spi_host_transfer()
276 data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4); in ibex_spi_host_transfer()
462 if (fifo8_is_full(&s->tx_fifo)) { in ibex_spi_host_write()
481 fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); in ibex_spi_host_write()
576 VMSTATE_FIFO8(tx_fifo, IbexSPIHostState),
609 fifo8_create(&s->tx_fifo, IBEX_SPI_HOST_TXFIFO_LEN); in ibex_spi_host_realize()
/openbmc/qemu/hw/net/
H A Dstellaris_enet.c75 uint8_t tx_fifo[2048]; member
124 if (s->tx_fifo_len > ARRAY_SIZE(s->tx_fifo)) { in stellaris_enet_post_load()
148 VMSTATE_UINT8_ARRAY(tx_fifo, stellaris_enet_state, 2048),
167 return s->tx_fifo[0] | (s->tx_fifo[1] << 8); in stellaris_txpacket_datalen()
186 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo)); in stellaris_txpacket_complete()
210 memset(&s->tx_fifo[framelen + 2], 0, 60 - framelen); in stellaris_enet_send()
219 framelen = MIN(framelen, ARRAY_SIZE(s->tx_fifo) - 2); in stellaris_enet_send()
220 qemu_send_packet(qemu_get_queue(s->nic), s->tx_fifo + 2, framelen); in stellaris_enet_send()
402 if (s->tx_fifo_len + 4 <= ARRAY_SIZE(s->tx_fifo)) { in stellaris_enet_write()
403 s->tx_fifo[s->tx_fifo_len++] = value; in stellaris_enet_write()
[all …]
H A Dallwinner_emac.c149 fifo8_reset(&s->tx_fifo[chan]); in aw_emac_tx_reset()
343 fifo = &s->tx_fifo[chan]; in aw_emac_write()
376 fifo = &s->tx_fifo[s->tx_channel]; in aw_emac_write()
461 fifo8_create(&s->tx_fifo[0], TX_FIFO_SIZE); in aw_emac_realize()
462 fifo8_create(&s->tx_fifo[1], TX_FIFO_SIZE); in aw_emac_realize()
509 VMSTATE_STRUCT_ARRAY(tx_fifo, AwEmacState, NUM_TX_FIFOS, 1,
/openbmc/qemu/hw/i3c/
H A Dremote-i3c.c
/openbmc/u-boot/drivers/serial/
H A Dserial_xuartlite.c27 unsigned int tx_fifo; member
44 out_be32(&regs->tx_fifo, ch & 0xff); in uartlite_serial_putc()
134 out_be32(&regs->tx_fifo, ch & 0xff); in _debug_uart_putc()
/openbmc/u-boot/drivers/spi/
H A Dpic32_spi.c79 void (*tx_fifo)(struct pic32_spi_priv *); member
167 priv->tx_fifo = pic32_spi_tx_byte; in pic32_spi_set_word_size()
172 priv->tx_fifo = pic32_spi_tx_word; in pic32_spi_set_word_size()
177 priv->tx_fifo = pic32_spi_tx_dword; in pic32_spi_set_word_size()
266 priv->tx_fifo(priv); in pic32_spi_xfer()
/openbmc/qemu/include/hw/ssi/
H A Dmss-spi.h50 Fifo32 tx_fifo; member
H A Dsifive_spi.h44 Fifo8 tx_fifo; member
H A Dallwinner-a10-spi.h54 Fifo8 tx_fifo; member
H A Dpl022.h47 uint16_t tx_fifo[8]; member
H A Dxlnx-versal-ospi.h88 Fifo8 tx_fifo; member
H A Dibex_spi_host.h79 Fifo8 tx_fifo; member
/openbmc/qemu/include/hw/net/
H A Dxlnx-zynqmp-can.h73 Fifo32 tx_fifo; member
/openbmc/qemu/hw/char/
H A Dibex_uart.c162 ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); in ibex_uart_xmit()
166 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level); in ibex_uart_xmit()
210 memcpy(s->tx_fifo + s->tx_level, buf, size); in uart_write_tx_fifo()
492 VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,
/openbmc/u-boot/drivers/i2c/
H A Dtegra_i2c.c153 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
158 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
171 writel(data, &i2c_bus->control->tx_fifo); in send_packet_headers()
266 writel(local, &control->tx_fifo); in send_recv_packets()

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