308         fifo8_is_empty(&s->tx_fifo)) {  in xilinx_spips_update_cs_lines()
322             (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |  in xilinx_spips_update_ixr()
323             (fifo8_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) |  in xilinx_spips_update_ixr()
324             (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);  in xilinx_spips_update_ixr()
617         if (fifo8_is_empty(&s->tx_fifo)) {  in xilinx_spips_flush_txfifo()
623                 tx_rx[i] = fifo8_pop(&s->tx_fifo);  in xilinx_spips_flush_txfifo()
627             tx = fifo8_pop(&s->tx_fifo);  in xilinx_spips_flush_txfifo()
636             tx = fifo8_pop(&s->tx_fifo);  in xilinx_spips_flush_txfifo()
762     if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {  in xilinx_spips_check_zero_pump()
770            s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {  in xilinx_spips_check_zero_pump()
772         tx_data_bytes(&s->tx_fifo, 0, 4, false);  in xilinx_spips_check_zero_pump()
781         (!fifo8_is_empty(&s->tx_fifo) &&  in xilinx_spips_check_flush()
786     if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {  in xilinx_spips_check_flush()
1009         tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,  in xilinx_spips_write()
1013         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1,  in xilinx_spips_write()
1017         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2,  in xilinx_spips_write()
1021         tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,  in xilinx_spips_write()
1167         fifo8_reset(&s->tx_fifo);  in lqspi_load_cache()
1174         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);  in lqspi_load_cache()
1178             fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));  in lqspi_load_cache()
1180         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));  in lqspi_load_cache()
1181         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));  in lqspi_load_cache()
1182         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);  in lqspi_load_cache()
1185             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],  in lqspi_load_cache()
1193             fifo8_push(&s->tx_fifo, 0);  in lqspi_load_cache()
1203                 tx_data_bytes(&s->tx_fifo, 0, 1, false);  in lqspi_load_cache()
1310     fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);  in xilinx_spips_realize()
1373         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
1387         fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) {  in xlnx_zynqmp_qspips_post_load()