| /openbmc/linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 56 .twr = 10,
65 .twr = 8,
74 .twr = 9,
82 .twr = 10,
91 .twr = 16, /* Trdl: 2 CLKs */
100 .twr = 8,
109 .twr = 8,
146 u_int mem_khz, sd_khz, trp, twr; in sdram_calculate_timing() local
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
175 sd->mdcnfg |= twr << 14; in sdram_calculate_timing()
[all …]
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| /openbmc/u-boot/board/work-microwave/work_92105/ |
| H A D | work_92105_spl.c | 26 .twr = 66666666,
46 .twr = 66666666,
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| /openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
| H A D | ddr2_v3s.c | 18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
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| H A D | lpddr3_stock.c | 18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params() local
43 u8 twtp = tcwl + 4 + twr + 1; in mctl_set_timing_params()
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| H A D | ddr3_1333.c | 18 u8 twr = max(ns_to_t(15), 3); in mctl_set_timing_params() local
43 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in mctl_set_timing_params()
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| /openbmc/linux/arch/arm/boot/dts/nxp/ls/ |
| H A D | Makefile | 8 ls1021a-twr.dtb
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | ls1021a-twr-lpuart.dts | 9 #include "ls1021a-twr.dtsi"
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| H A D | ls1021a-twr-duart.dts | 9 #include "ls1021a-twr.dtsi"
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| H A D | vf610-twr.dts | 11 compatible = "fsl,vf610-twr", "fsl,vf610";
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| /openbmc/u-boot/board/timll/devkit3250/ |
| H A D | devkit3250_spl.c | 33 .twr = 83000000, /* tWR = tRDL = 2 CLK */
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| /openbmc/openbmc/meta-security/recipes-ids/tripwire/files/ |
| H A D | twcfg.txt | 4 REPORTFILE =/var/lib/tripwire/report/$(HOSTNAME)-$(DATE).twr
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| /openbmc/linux/arch/arm/boot/dts/nxp/vf/ |
| H A D | Makefile | 9 vf610-twr.dtb \
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| /openbmc/u-boot/arch/arm/mach-imx/mx6/ |
| H A D | ddr.c | 1000 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr; in mx6_lpddr2_cfg() local
1052 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_lpddr2_cfg()
1089 debug("twr=%d\n", twr); in mx6_lpddr2_cfg()
1142 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl; in mx6_lpddr2_cfg()
1231 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr; in mx6_ddr3_cfg() local
1332 twr = DIV_ROUND_UP(15000, clkper) - 1; in mx6_ddr3_cfg()
1365 debug("twr=%d\n", twr); in mx6_ddr3_cfg()
1378 debug("twr=%d\n", twr); in mx6_ddr3_cfg()
1436 (twr << 9) | (tmrd << 5) | tcwl; in mx6_ddr3_cfg()
1490 ((twr - 3) << 9) | /* Write Recovery */ in mx6_ddr3_cfg()
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| /openbmc/u-boot/include/ |
| H A D | spd.h | 51 unsigned char twr; /* 36 Write Recovery time tWR */ member
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| /openbmc/u-boot/drivers/ram/ |
| H A D | stm32_sdram.c | 125 u8 twr; member
198 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
208 | timing->twr << FMC_SDTR_TWR_SHIFT in stm32_sdram_init()
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| /openbmc/u-boot/configs/ |
| H A D | vf610twr_nand_defconfig | 30 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
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| H A D | vf610twr_defconfig | 30 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
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| H A D | ls1021atwr_nor_defconfig | 29 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
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| H A D | ls1021atwr_nor_SECURE_BOOT_defconfig | 31 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
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| H A D | ls1021atwr_nor_lpuart_defconfig | 31 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
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| H A D | ls1021atwr_qspi_defconfig | 32 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 100 u8 twr = max(ns_to_t(15), 3); in auto_set_timing_para() local
126 u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ in auto_set_timing_para()
165 twtp = tcwl + 4 + twr + 1; /* CWL + BL/2 + tWR */ in auto_set_timing_para()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 61 u32 twr; member
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | dram.c | 44 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | emc.h | 87 u32 twr; member
|