| /openbmc/u-boot/board/freescale/corenet_ds/ |
| H A D | p4080ds_ddr.c | 90 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
122 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
154 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
186 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_900,
218 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
250 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1000,
282 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
314 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1200,
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | mpc85xx_ddr_gen3.c | 117 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
203 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); in fsl_ddr_set_memctl_regs()
328 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
459 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
461 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
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| H A D | mpc85xx_ddr_gen1.c | 46 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| H A D | mpc86xx_ddr.c | 54 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| H A D | mpc85xx_ddr_gen2.c | 69 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| H A D | arm_ddr_gen3.c | 94 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
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| /openbmc/u-boot/board/freescale/bsc9132qds/ |
| H A D | spl_minimal.c | 31 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
51 __raw_writel(CONFIG_SYS_DDR_TIMING_2_1333, &ddr->timing_cfg_2); in sdram_init()
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| H A D | ddr.c | 24 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
51 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
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| /openbmc/u-boot/board/sbc8641d/ |
| H A D | sbc8641d.c | 112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
143 ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; in fixed_sdram()
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | ddr.c | 27 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
54 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
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| /openbmc/u-boot/board/freescale/mpc8349emds/ |
| H A D | mpc8349emds.c | 105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
130 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /openbmc/u-boot/board/freescale/mpc8349itx/ |
| H A D | mpc8349itx.c | 60 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */ in fixed_sdram()
74 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2); in fixed_sdram()
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| /openbmc/u-boot/board/freescale/p1_twr/ |
| H A D | ddr.c | 33 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, in fixed_sdram()
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| /openbmc/u-boot/board/socrates/ |
| H A D | sdram.c | 39 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /openbmc/u-boot/board/freescale/ls1043ardb/ |
| H A D | ddr.h | 62 .timing_cfg_2 = 0x0048C111,
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| /openbmc/u-boot/board/freescale/mpc8308rdb/ |
| H A D | sdram.c | 49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /openbmc/u-boot/board/sbc8548/ |
| H A D | ddr.c | 107 out_be32(&ddr->timing_cfg_2, 0x0fa044C7); in fixed_sdram()
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| /openbmc/u-boot/board/mpc8308_p1m/ |
| H A D | sdram.c | 45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /openbmc/u-boot/board/gdsys/mpc8308/ |
| H A D | sdram.c | 50 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /openbmc/u-boot/board/freescale/mpc8315erdb/ |
| H A D | sdram.c | 66 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /openbmc/u-boot/board/freescale/bsc9131rdb/ |
| H A D | spl_minimal.c | 34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); in sdram_init()
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| /openbmc/u-boot/board/freescale/mpc832xemds/ |
| H A D | mpc832xemds.c | 138 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /openbmc/u-boot/board/freescale/mpc8313erdb/ |
| H A D | sdram.c | 75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /openbmc/u-boot/drivers/ram/ |
| H A D | mpc83xx_sdram.c | 338 u32 timing_cfg_2; in mpc83xx_sdram_probe() local
777 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT | in mpc83xx_sdram_probe()
785 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2); in mpc83xx_sdram_probe()
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| /openbmc/u-boot/board/Arcturus/ucp1020/ |
| H A D | ddr.c | 93 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, in fixed_sdram()
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