183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e58fe957SKim Phillips /*
3e58fe957SKim Phillips * (C) Copyright 2006
4e58fe957SKim Phillips * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5e58fe957SKim Phillips */
6e58fe957SKim Phillips
7e58fe957SKim Phillips #include <common.h>
8e58fe957SKim Phillips #include <ioports.h>
9e58fe957SKim Phillips #include <mpc83xx.h>
10e58fe957SKim Phillips #include <asm/mpc8349_pci.h>
11e58fe957SKim Phillips #include <i2c.h>
1280ddd226SBen Warren #include <spi.h>
13e58fe957SKim Phillips #include <miiphy.h>
145614e71bSYork Sun #ifdef CONFIG_SYS_FSL_DDR2
155614e71bSYork Sun #include <fsl_ddr_sdram.h>
16d4b91066SYork Sun #else
17e58fe957SKim Phillips #include <spd_sdram.h>
18d4b91066SYork Sun #endif
19a30a549aSJon Loeliger
20b3458d2cSKim Phillips #if defined(CONFIG_OF_LIBFDT)
21b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
22e58fe957SKim Phillips #endif
23e58fe957SKim Phillips
24088454cdSSimon Glass DECLARE_GLOBAL_DATA_PTR;
25088454cdSSimon Glass
26e58fe957SKim Phillips int fixed_sdram(void);
27e58fe957SKim Phillips void sdram_init(void);
28e58fe957SKim Phillips
290f898604SPeter Tyser #if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
30e58fe957SKim Phillips void ddr_enable_ecc(unsigned int dram_size);
31e58fe957SKim Phillips #endif
32e58fe957SKim Phillips
board_early_init_f(void)33e58fe957SKim Phillips int board_early_init_f (void)
34e58fe957SKim Phillips {
356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
36e58fe957SKim Phillips
37e58fe957SKim Phillips /* Enable flash write */
38e58fe957SKim Phillips bcsr[1] &= ~0x01;
39e58fe957SKim Phillips
406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
41e58fe957SKim Phillips /* Use USB PHY on SYS board */
42e58fe957SKim Phillips bcsr[5] |= 0x02;
43e58fe957SKim Phillips #endif
44e58fe957SKim Phillips
45e58fe957SKim Phillips return 0;
46e58fe957SKim Phillips }
47e58fe957SKim Phillips
48e58fe957SKim Phillips #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
49e58fe957SKim Phillips
dram_init(void)50f1683aa7SSimon Glass int dram_init(void)
51e58fe957SKim Phillips {
526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
53d4b91066SYork Sun phys_size_t msize = 0;
54e58fe957SKim Phillips
55e58fe957SKim Phillips if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
56088454cdSSimon Glass return -ENXIO;
57e58fe957SKim Phillips
58e58fe957SKim Phillips /* DDR SDRAM - Main SODIMM */
596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
60e58fe957SKim Phillips #if defined(CONFIG_SPD_EEPROM)
615614e71bSYork Sun #ifndef CONFIG_SYS_FSL_DDR2
62d4b91066SYork Sun msize = spd_sdram() * 1024 * 1024;
63d4b91066SYork Sun #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
64d4b91066SYork Sun ddr_enable_ecc(msize);
65d4b91066SYork Sun #endif
66e58fe957SKim Phillips #else
67d4b91066SYork Sun msize = fsl_ddr_sdram();
68d4b91066SYork Sun #endif
69d4b91066SYork Sun #else
70d4b91066SYork Sun msize = fixed_sdram() * 1024 * 1024;
71e58fe957SKim Phillips #endif
72e58fe957SKim Phillips /*
73e58fe957SKim Phillips * Initialize SDRAM if it is on local bus.
74e58fe957SKim Phillips */
75e58fe957SKim Phillips sdram_init();
76e58fe957SKim Phillips
77088454cdSSimon Glass /* set total bus SDRAM size(bytes) -- DDR */
78088454cdSSimon Glass gd->ram_size = msize;
79088454cdSSimon Glass
80088454cdSSimon Glass return 0;
81e58fe957SKim Phillips }
82e58fe957SKim Phillips
83e58fe957SKim Phillips #if !defined(CONFIG_SPD_EEPROM)
84e58fe957SKim Phillips /*************************************************************************
85e58fe957SKim Phillips * fixed sdram init -- doesn't use serial presence detect.
86e58fe957SKim Phillips ************************************************************************/
fixed_sdram(void)87e58fe957SKim Phillips int fixed_sdram(void)
88e58fe957SKim Phillips {
896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
902e651b24SJoe Hershberger u32 msize = CONFIG_SYS_DDR_SIZE;
912e651b24SJoe Hershberger u32 ddr_size = msize << 20; /* DDR size in bytes */
922e651b24SJoe Hershberger u32 ddr_size_log2 = __ilog2(ddr_size);
93e58fe957SKim Phillips
946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
95e58fe957SKim Phillips im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
96e58fe957SKim Phillips
976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if (CONFIG_SYS_DDR_SIZE != 256)
98e58fe957SKim Phillips #warning Currenly any ddr size other than 256 is not supported
99e58fe957SKim Phillips #endif
100e58fe957SKim Phillips #ifdef CONFIG_DDR_II
1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
113e58fe957SKim Phillips #else
1142e651b24SJoe Hershberger
1152e651b24SJoe Hershberger #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
1162e651b24SJoe Hershberger #warning Chip select bounds is only configurable in 16MB increments
1172e651b24SJoe Hershberger #endif
1182e651b24SJoe Hershberger im->ddr.csbnds[2].csbnds =
1192e651b24SJoe Hershberger ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
1202e651b24SJoe Hershberger (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
1212e651b24SJoe Hershberger CSBNDS_EA_SHIFT) & CSBNDS_EA);
1222e651b24SJoe Hershberger im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
123e58fe957SKim Phillips
124e58fe957SKim Phillips /* currently we use only one CS, so disable the other banks */
125e58fe957SKim Phillips im->ddr.cs_config[0] = 0;
126e58fe957SKim Phillips im->ddr.cs_config[1] = 0;
127e58fe957SKim Phillips im->ddr.cs_config[3] = 0;
128e58fe957SKim Phillips
1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
131e58fe957SKim Phillips
132e58fe957SKim Phillips im->ddr.sdram_cfg =
133e58fe957SKim Phillips SDRAM_CFG_SREN
134e58fe957SKim Phillips #if defined(CONFIG_DDR_2T_TIMING)
135e58fe957SKim Phillips | SDRAM_CFG_2T_EN
136e58fe957SKim Phillips #endif
137e58fe957SKim Phillips | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
138e58fe957SKim Phillips #if defined (CONFIG_DDR_32BIT)
139e58fe957SKim Phillips /* for 32-bit mode burst length is 8 */
140e58fe957SKim Phillips im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
141e58fe957SKim Phillips #endif
1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
143e58fe957SKim Phillips
1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
145e58fe957SKim Phillips #endif
146e58fe957SKim Phillips udelay(200);
147e58fe957SKim Phillips
148e58fe957SKim Phillips /* enable DDR controller */
149e58fe957SKim Phillips im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
150e58fe957SKim Phillips return msize;
151e58fe957SKim Phillips }
1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #endif/*!CONFIG_SYS_SPD_EEPROM*/
153e58fe957SKim Phillips
154e58fe957SKim Phillips
checkboard(void)155e58fe957SKim Phillips int checkboard (void)
156e58fe957SKim Phillips {
157447ad576SIra W. Snyder /*
158447ad576SIra W. Snyder * Warning: do not read the BCSR registers here
159447ad576SIra W. Snyder *
160447ad576SIra W. Snyder * There is a timing bug in the 8349E and 8349EA BCSR code
161447ad576SIra W. Snyder * version 1.2 (read from BCSR 11) that will cause the CFI
162447ad576SIra W. Snyder * flash initialization code to overwrite BCSR 0, disabling
163447ad576SIra W. Snyder * the serial ports and gigabit ethernet
164447ad576SIra W. Snyder */
165447ad576SIra W. Snyder
166e58fe957SKim Phillips puts("Board: Freescale MPC8349EMDS\n");
167e58fe957SKim Phillips return 0;
168e58fe957SKim Phillips }
169e58fe957SKim Phillips
170e58fe957SKim Phillips /*
171e58fe957SKim Phillips * if MPC8349EMDS is soldered with SDRAM
172e58fe957SKim Phillips */
1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_BR2_PRELIM) \
1746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD && defined(CONFIG_SYS_OR2_PRELIM) \
1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
177e58fe957SKim Phillips /*
178e58fe957SKim Phillips * Initialize SDRAM memory on the Local Bus.
179e58fe957SKim Phillips */
180e58fe957SKim Phillips
sdram_init(void)181e58fe957SKim Phillips void sdram_init(void)
182e58fe957SKim Phillips {
1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
184f51cdaf1SBecky Bruce volatile fsl_lbc_t *lbc = &immap->im_lbc;
1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
186e58fe957SKim Phillips
187e58fe957SKim Phillips /*
188e58fe957SKim Phillips * Setup SDRAM Base and Option Registers, already done in cpu_init.c
189e58fe957SKim Phillips */
190e58fe957SKim Phillips
191e58fe957SKim Phillips /* setup mtrpt, lsrt and lbcr for LB bus */
1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lbcr = CONFIG_SYS_LBC_LBCR;
1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsrt = CONFIG_SYS_LBC_LSRT;
195e58fe957SKim Phillips asm("sync");
196e58fe957SKim Phillips
197e58fe957SKim Phillips /*
198e58fe957SKim Phillips * Configure the SDRAM controller Machine Mode Register.
199e58fe957SKim Phillips */
2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
201e58fe957SKim Phillips
2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
203e58fe957SKim Phillips asm("sync");
204e58fe957SKim Phillips *sdram_addr = 0xff;
205e58fe957SKim Phillips udelay(100);
206e58fe957SKim Phillips
2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
208e58fe957SKim Phillips asm("sync");
209e58fe957SKim Phillips /*1 times*/
210e58fe957SKim Phillips *sdram_addr = 0xff;
211e58fe957SKim Phillips udelay(100);
212e58fe957SKim Phillips /*2 times*/
213e58fe957SKim Phillips *sdram_addr = 0xff;
214e58fe957SKim Phillips udelay(100);
215e58fe957SKim Phillips /*3 times*/
216e58fe957SKim Phillips *sdram_addr = 0xff;
217e58fe957SKim Phillips udelay(100);
218e58fe957SKim Phillips /*4 times*/
219e58fe957SKim Phillips *sdram_addr = 0xff;
220e58fe957SKim Phillips udelay(100);
221e58fe957SKim Phillips /*5 times*/
222e58fe957SKim Phillips *sdram_addr = 0xff;
223e58fe957SKim Phillips udelay(100);
224e58fe957SKim Phillips /*6 times*/
225e58fe957SKim Phillips *sdram_addr = 0xff;
226e58fe957SKim Phillips udelay(100);
227e58fe957SKim Phillips /*7 times*/
228e58fe957SKim Phillips *sdram_addr = 0xff;
229e58fe957SKim Phillips udelay(100);
230e58fe957SKim Phillips /*8 times*/
231e58fe957SKim Phillips *sdram_addr = 0xff;
232e58fe957SKim Phillips udelay(100);
233e58fe957SKim Phillips
234e58fe957SKim Phillips /* 0x58636733; mode register write operation */
2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
236e58fe957SKim Phillips asm("sync");
237e58fe957SKim Phillips *sdram_addr = 0xff;
238e58fe957SKim Phillips udelay(100);
239e58fe957SKim Phillips
2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
241e58fe957SKim Phillips asm("sync");
242e58fe957SKim Phillips *sdram_addr = 0xff;
243e58fe957SKim Phillips udelay(100);
244e58fe957SKim Phillips }
245e58fe957SKim Phillips #else
sdram_init(void)246e58fe957SKim Phillips void sdram_init(void)
247e58fe957SKim Phillips {
248e58fe957SKim Phillips }
249e58fe957SKim Phillips #endif
250e58fe957SKim Phillips
25180ddd226SBen Warren /*
25280ddd226SBen Warren * The following are used to control the SPI chip selects for the SPI command.
25380ddd226SBen Warren */
254f8cc312bSBen Warren #ifdef CONFIG_MPC8XXX_SPI
25580ddd226SBen Warren
25680ddd226SBen Warren #define SPI_CS_MASK 0x80000000
25780ddd226SBen Warren
spi_cs_is_valid(unsigned int bus,unsigned int cs)258d255bb0eSHaavard Skinnemoen int spi_cs_is_valid(unsigned int bus, unsigned int cs)
259d255bb0eSHaavard Skinnemoen {
260d255bb0eSHaavard Skinnemoen return bus == 0 && cs == 0;
261d255bb0eSHaavard Skinnemoen }
262d255bb0eSHaavard Skinnemoen
spi_cs_activate(struct spi_slave * slave)263d255bb0eSHaavard Skinnemoen void spi_cs_activate(struct spi_slave *slave)
26480ddd226SBen Warren {
2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
26680ddd226SBen Warren
26780ddd226SBen Warren iopd->dat &= ~SPI_CS_MASK;
26880ddd226SBen Warren }
26980ddd226SBen Warren
spi_cs_deactivate(struct spi_slave * slave)270d255bb0eSHaavard Skinnemoen void spi_cs_deactivate(struct spi_slave *slave)
271d255bb0eSHaavard Skinnemoen {
2726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
27380ddd226SBen Warren
274d255bb0eSHaavard Skinnemoen iopd->dat |= SPI_CS_MASK;
275d255bb0eSHaavard Skinnemoen }
276*35f9d9bdSJagan Teki #endif
27780ddd226SBen Warren
278e58fe957SKim Phillips #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)279e895a4b0SSimon Glass int ft_board_setup(void *blob, bd_t *bd)
280e58fe957SKim Phillips {
281e58fe957SKim Phillips ft_cpu_setup(blob, bd);
282e58fe957SKim Phillips #ifdef CONFIG_PCI
283e58fe957SKim Phillips ft_pci_setup(blob, bd);
284e58fe957SKim Phillips #endif
285e895a4b0SSimon Glass
286e895a4b0SSimon Glass return 0;
287e58fe957SKim Phillips }
288e58fe957SKim Phillips #endif
289