| /openbmc/qemu/target/sh4/ |
| H A D | translate.c | 723 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
726 tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
729 tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
732 tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
735 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
1522 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, tmp, cpu_lock_value); in _decode_opc()
2146 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(ld_dst), op_arg); in decode_gusa()
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| /openbmc/qemu/target/microblaze/ |
| H A D | translate.c | 423 tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); in DO_TYPEA0_CFG()
432 tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); in gen_cmpu()
526 tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); in DO_TYPEA_CFG()
531 tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb); in gen_pcmpne()
541 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); in DO_TYPEA_CFG()
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| /openbmc/qemu/include/tcg/ |
| H A D | tcg-op.h | 319 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
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| H A D | tcg-op-common.h | 124 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
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| /openbmc/qemu/target/m68k/ |
| H A D | translate.c | 575 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V); in gen_flush_flags()
1302 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); in gen_cc_cond()
1798 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src); in DISAS_INSN()
1801 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src); in DISAS_INSN()
2244 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im); in DISAS_INSN()
2253 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im); in DISAS_INSN()
2922 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); in DISAS_INSN()
2927 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val); in DISAS_INSN()
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| /openbmc/qemu/tcg/ |
| H A D | tcg-op.c | 524 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, in tcg_gen_setcond_i32() function
539 tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); in tcg_gen_setcondi_i32()
552 tcg_gen_setcond_i32(cond, ret, arg1, arg2); in tcg_gen_negsetcond_i32()
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| /openbmc/qemu/target/ppc/ |
| H A D | translate.c | 1544 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); in gen_cmprb()
1545 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); in gen_cmprb()
1553 tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); in gen_cmprb()
1554 tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); in gen_cmprb()
2031 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); in gen_mullwo()
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| /openbmc/qemu/target/s390x/tcg/ |
| H A D | translate_vx.c.inc | 1336 tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b);
2302 tcg_gen_setcond_i32(TCG_COND_GEU, d, a, b);
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| H A D | translate.c | 1259 tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); in help_branch()
2922 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b); in op_loc()
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| /openbmc/qemu/target/rx/ |
| H A D | translate.c | 1042 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); in rx_sub()
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | vmx-impl.c.inc | 2922 tcg_gen_setcond_i32(TCG_COND_LTU, t, a, b);
2933 tcg_gen_setcond_i32(TCG_COND_GEU, t, a, b);
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| /openbmc/qemu/target/xtensa/ |
| H A D | translate.c | 2245 tcg_gen_setcond_i32(TCG_COND_EQ, res, prev, cpu_exclusive_val); in translate_s32ex()
2257 tcg_gen_setcond_i32(par[0], in translate_salt()
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | translate.c | 521 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0, t1); in gen_sub_CC()
4947 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2); in gen_store_exclusive()
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| H A D | translate-a64.c | 872 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); in gen_sub32_CC()
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