1c9274b6bSCho, Yu-Chen /*
2c9274b6bSCho, Yu-Chen * S/390 translation
3c9274b6bSCho, Yu-Chen *
4c9274b6bSCho, Yu-Chen * Copyright (c) 2009 Ulrich Hecht
5c9274b6bSCho, Yu-Chen * Copyright (c) 2010 Alexander Graf
6c9274b6bSCho, Yu-Chen *
7c9274b6bSCho, Yu-Chen * This library is free software; you can redistribute it and/or
8c9274b6bSCho, Yu-Chen * modify it under the terms of the GNU Lesser General Public
9c9274b6bSCho, Yu-Chen * License as published by the Free Software Foundation; either
10c9274b6bSCho, Yu-Chen * version 2.1 of the License, or (at your option) any later version.
11c9274b6bSCho, Yu-Chen *
12c9274b6bSCho, Yu-Chen * This library is distributed in the hope that it will be useful,
13c9274b6bSCho, Yu-Chen * but WITHOUT ANY WARRANTY; without even the implied warranty of
14c9274b6bSCho, Yu-Chen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15c9274b6bSCho, Yu-Chen * Lesser General Public License for more details.
16c9274b6bSCho, Yu-Chen *
17c9274b6bSCho, Yu-Chen * You should have received a copy of the GNU Lesser General Public
18c9274b6bSCho, Yu-Chen * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19c9274b6bSCho, Yu-Chen */
20c9274b6bSCho, Yu-Chen
21c9274b6bSCho, Yu-Chen /* #define DEBUG_INLINE_BRANCHES */
22c9274b6bSCho, Yu-Chen #define S390X_DEBUG_DISAS
23c9274b6bSCho, Yu-Chen /* #define S390X_DEBUG_DISAS_VERBOSE */
24c9274b6bSCho, Yu-Chen
25c9274b6bSCho, Yu-Chen #ifdef S390X_DEBUG_DISAS_VERBOSE
26c9274b6bSCho, Yu-Chen # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
27c9274b6bSCho, Yu-Chen #else
28c9274b6bSCho, Yu-Chen # define LOG_DISAS(...) do { } while (0)
29c9274b6bSCho, Yu-Chen #endif
30c9274b6bSCho, Yu-Chen
31c9274b6bSCho, Yu-Chen #include "qemu/osdep.h"
32c9274b6bSCho, Yu-Chen #include "cpu.h"
33c9274b6bSCho, Yu-Chen #include "s390x-internal.h"
34c9274b6bSCho, Yu-Chen #include "exec/exec-all.h"
35c9274b6bSCho, Yu-Chen #include "tcg/tcg-op.h"
36c9274b6bSCho, Yu-Chen #include "tcg/tcg-op-gvec.h"
37c9274b6bSCho, Yu-Chen #include "qemu/log.h"
38c9274b6bSCho, Yu-Chen #include "qemu/host-utils.h"
39c9274b6bSCho, Yu-Chen #include "exec/helper-proto.h"
40c9274b6bSCho, Yu-Chen #include "exec/helper-gen.h"
41c9274b6bSCho, Yu-Chen
42c9274b6bSCho, Yu-Chen #include "exec/translator.h"
43c9274b6bSCho, Yu-Chen #include "exec/log.h"
44c9274b6bSCho, Yu-Chen #include "qemu/atomic128.h"
45c9274b6bSCho, Yu-Chen
46d53106c9SRichard Henderson #define HELPER_H "helper.h"
47d53106c9SRichard Henderson #include "exec/helper-info.c.inc"
48d53106c9SRichard Henderson #undef HELPER_H
49d53106c9SRichard Henderson
50c9274b6bSCho, Yu-Chen
51c9274b6bSCho, Yu-Chen /* Information that (most) every instruction needs to manipulate. */
52c9274b6bSCho, Yu-Chen typedef struct DisasContext DisasContext;
53c9274b6bSCho, Yu-Chen typedef struct DisasInsn DisasInsn;
54c9274b6bSCho, Yu-Chen typedef struct DisasFields DisasFields;
55c9274b6bSCho, Yu-Chen
56c9274b6bSCho, Yu-Chen /*
57c9274b6bSCho, Yu-Chen * Define a structure to hold the decoded fields. We'll store each inside
58c9274b6bSCho, Yu-Chen * an array indexed by an enum. In order to conserve memory, we'll arrange
59c9274b6bSCho, Yu-Chen * for fields that do not exist at the same time to overlap, thus the "C"
60c9274b6bSCho, Yu-Chen * for compact. For checking purposes there is an "O" for original index
61c9274b6bSCho, Yu-Chen * as well that will be applied to availability bitmaps.
62c9274b6bSCho, Yu-Chen */
63c9274b6bSCho, Yu-Chen
64c9274b6bSCho, Yu-Chen enum DisasFieldIndexO {
65c9274b6bSCho, Yu-Chen FLD_O_r1,
66c9274b6bSCho, Yu-Chen FLD_O_r2,
67c9274b6bSCho, Yu-Chen FLD_O_r3,
68c9274b6bSCho, Yu-Chen FLD_O_m1,
69c9274b6bSCho, Yu-Chen FLD_O_m3,
70c9274b6bSCho, Yu-Chen FLD_O_m4,
71c9274b6bSCho, Yu-Chen FLD_O_m5,
72c9274b6bSCho, Yu-Chen FLD_O_m6,
73c9274b6bSCho, Yu-Chen FLD_O_b1,
74c9274b6bSCho, Yu-Chen FLD_O_b2,
75c9274b6bSCho, Yu-Chen FLD_O_b4,
76c9274b6bSCho, Yu-Chen FLD_O_d1,
77c9274b6bSCho, Yu-Chen FLD_O_d2,
78c9274b6bSCho, Yu-Chen FLD_O_d4,
79c9274b6bSCho, Yu-Chen FLD_O_x2,
80c9274b6bSCho, Yu-Chen FLD_O_l1,
81c9274b6bSCho, Yu-Chen FLD_O_l2,
82c9274b6bSCho, Yu-Chen FLD_O_i1,
83c9274b6bSCho, Yu-Chen FLD_O_i2,
84c9274b6bSCho, Yu-Chen FLD_O_i3,
85c9274b6bSCho, Yu-Chen FLD_O_i4,
86c9274b6bSCho, Yu-Chen FLD_O_i5,
87c9274b6bSCho, Yu-Chen FLD_O_v1,
88c9274b6bSCho, Yu-Chen FLD_O_v2,
89c9274b6bSCho, Yu-Chen FLD_O_v3,
90c9274b6bSCho, Yu-Chen FLD_O_v4,
91c9274b6bSCho, Yu-Chen };
92c9274b6bSCho, Yu-Chen
93c9274b6bSCho, Yu-Chen enum DisasFieldIndexC {
94c9274b6bSCho, Yu-Chen FLD_C_r1 = 0,
95c9274b6bSCho, Yu-Chen FLD_C_m1 = 0,
96c9274b6bSCho, Yu-Chen FLD_C_b1 = 0,
97c9274b6bSCho, Yu-Chen FLD_C_i1 = 0,
98c9274b6bSCho, Yu-Chen FLD_C_v1 = 0,
99c9274b6bSCho, Yu-Chen
100c9274b6bSCho, Yu-Chen FLD_C_r2 = 1,
101c9274b6bSCho, Yu-Chen FLD_C_b2 = 1,
102c9274b6bSCho, Yu-Chen FLD_C_i2 = 1,
103c9274b6bSCho, Yu-Chen
104c9274b6bSCho, Yu-Chen FLD_C_r3 = 2,
105c9274b6bSCho, Yu-Chen FLD_C_m3 = 2,
106c9274b6bSCho, Yu-Chen FLD_C_i3 = 2,
107c9274b6bSCho, Yu-Chen FLD_C_v3 = 2,
108c9274b6bSCho, Yu-Chen
109c9274b6bSCho, Yu-Chen FLD_C_m4 = 3,
110c9274b6bSCho, Yu-Chen FLD_C_b4 = 3,
111c9274b6bSCho, Yu-Chen FLD_C_i4 = 3,
112c9274b6bSCho, Yu-Chen FLD_C_l1 = 3,
113c9274b6bSCho, Yu-Chen FLD_C_v4 = 3,
114c9274b6bSCho, Yu-Chen
115c9274b6bSCho, Yu-Chen FLD_C_i5 = 4,
116c9274b6bSCho, Yu-Chen FLD_C_d1 = 4,
117c9274b6bSCho, Yu-Chen FLD_C_m5 = 4,
118c9274b6bSCho, Yu-Chen
119c9274b6bSCho, Yu-Chen FLD_C_d2 = 5,
120c9274b6bSCho, Yu-Chen FLD_C_m6 = 5,
121c9274b6bSCho, Yu-Chen
122c9274b6bSCho, Yu-Chen FLD_C_d4 = 6,
123c9274b6bSCho, Yu-Chen FLD_C_x2 = 6,
124c9274b6bSCho, Yu-Chen FLD_C_l2 = 6,
125c9274b6bSCho, Yu-Chen FLD_C_v2 = 6,
126c9274b6bSCho, Yu-Chen
127c9274b6bSCho, Yu-Chen NUM_C_FIELD = 7
128c9274b6bSCho, Yu-Chen };
129c9274b6bSCho, Yu-Chen
130c9274b6bSCho, Yu-Chen struct DisasFields {
131c9274b6bSCho, Yu-Chen uint64_t raw_insn;
132c9274b6bSCho, Yu-Chen unsigned op:8;
133c9274b6bSCho, Yu-Chen unsigned op2:8;
134c9274b6bSCho, Yu-Chen unsigned presentC:16;
135c9274b6bSCho, Yu-Chen unsigned int presentO;
136c9274b6bSCho, Yu-Chen int c[NUM_C_FIELD];
137c9274b6bSCho, Yu-Chen };
138c9274b6bSCho, Yu-Chen
139c9274b6bSCho, Yu-Chen struct DisasContext {
140c9274b6bSCho, Yu-Chen DisasContextBase base;
141c9274b6bSCho, Yu-Chen const DisasInsn *insn;
142c9274b6bSCho, Yu-Chen DisasFields fields;
143c9274b6bSCho, Yu-Chen uint64_t ex_value;
144c9274b6bSCho, Yu-Chen /*
145c9274b6bSCho, Yu-Chen * During translate_one(), pc_tmp is used to determine the instruction
146c9274b6bSCho, Yu-Chen * to be executed after base.pc_next - e.g. next sequential instruction
147c9274b6bSCho, Yu-Chen * or a branch target.
148c9274b6bSCho, Yu-Chen */
149c9274b6bSCho, Yu-Chen uint64_t pc_tmp;
150c9274b6bSCho, Yu-Chen uint32_t ilen;
151c9274b6bSCho, Yu-Chen enum cc_op cc_op;
152872e1379SRichard Henderson bool exit_to_mainloop;
153c9274b6bSCho, Yu-Chen };
154c9274b6bSCho, Yu-Chen
155c9274b6bSCho, Yu-Chen /* Information carried about a condition to be evaluated. */
156c9274b6bSCho, Yu-Chen typedef struct {
157c9274b6bSCho, Yu-Chen TCGCond cond:8;
158c9274b6bSCho, Yu-Chen bool is_64;
159c9274b6bSCho, Yu-Chen union {
160c9274b6bSCho, Yu-Chen struct { TCGv_i64 a, b; } s64;
161c9274b6bSCho, Yu-Chen struct { TCGv_i32 a, b; } s32;
162c9274b6bSCho, Yu-Chen } u;
163c9274b6bSCho, Yu-Chen } DisasCompare;
164c9274b6bSCho, Yu-Chen
165c9274b6bSCho, Yu-Chen #ifdef DEBUG_INLINE_BRANCHES
166c9274b6bSCho, Yu-Chen static uint64_t inline_branch_hit[CC_OP_MAX];
167c9274b6bSCho, Yu-Chen static uint64_t inline_branch_miss[CC_OP_MAX];
168c9274b6bSCho, Yu-Chen #endif
169c9274b6bSCho, Yu-Chen
pc_to_link_info(TCGv_i64 out,DisasContext * s,uint64_t pc)170c9274b6bSCho, Yu-Chen static void pc_to_link_info(TCGv_i64 out, DisasContext *s, uint64_t pc)
171c9274b6bSCho, Yu-Chen {
172c9274b6bSCho, Yu-Chen if (s->base.tb->flags & FLAG_MASK_32) {
173c9274b6bSCho, Yu-Chen if (s->base.tb->flags & FLAG_MASK_64) {
174c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(out, pc);
175c9274b6bSCho, Yu-Chen return;
176c9274b6bSCho, Yu-Chen }
177c9274b6bSCho, Yu-Chen pc |= 0x80000000;
178c9274b6bSCho, Yu-Chen }
179c9274b6bSCho, Yu-Chen assert(!(s->base.tb->flags & FLAG_MASK_64));
180f1ea739bSRichard Henderson tcg_gen_deposit_i64(out, out, tcg_constant_i64(pc), 0, 32);
181c9274b6bSCho, Yu-Chen }
182c9274b6bSCho, Yu-Chen
183c9274b6bSCho, Yu-Chen static TCGv_i64 psw_addr;
184c9274b6bSCho, Yu-Chen static TCGv_i64 psw_mask;
185c9274b6bSCho, Yu-Chen static TCGv_i64 gbea;
186c9274b6bSCho, Yu-Chen
187c9274b6bSCho, Yu-Chen static TCGv_i32 cc_op;
188c9274b6bSCho, Yu-Chen static TCGv_i64 cc_src;
189c9274b6bSCho, Yu-Chen static TCGv_i64 cc_dst;
190c9274b6bSCho, Yu-Chen static TCGv_i64 cc_vr;
191c9274b6bSCho, Yu-Chen
192c9274b6bSCho, Yu-Chen static char cpu_reg_names[16][4];
193c9274b6bSCho, Yu-Chen static TCGv_i64 regs[16];
194c9274b6bSCho, Yu-Chen
s390x_translate_init(void)195c9274b6bSCho, Yu-Chen void s390x_translate_init(void)
196c9274b6bSCho, Yu-Chen {
197c9274b6bSCho, Yu-Chen int i;
198c9274b6bSCho, Yu-Chen
199ad75a51eSRichard Henderson psw_addr = tcg_global_mem_new_i64(tcg_env,
200c9274b6bSCho, Yu-Chen offsetof(CPUS390XState, psw.addr),
201c9274b6bSCho, Yu-Chen "psw_addr");
202ad75a51eSRichard Henderson psw_mask = tcg_global_mem_new_i64(tcg_env,
203c9274b6bSCho, Yu-Chen offsetof(CPUS390XState, psw.mask),
204c9274b6bSCho, Yu-Chen "psw_mask");
205ad75a51eSRichard Henderson gbea = tcg_global_mem_new_i64(tcg_env,
206c9274b6bSCho, Yu-Chen offsetof(CPUS390XState, gbea),
207c9274b6bSCho, Yu-Chen "gbea");
208c9274b6bSCho, Yu-Chen
209ad75a51eSRichard Henderson cc_op = tcg_global_mem_new_i32(tcg_env, offsetof(CPUS390XState, cc_op),
210c9274b6bSCho, Yu-Chen "cc_op");
211ad75a51eSRichard Henderson cc_src = tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_src),
212c9274b6bSCho, Yu-Chen "cc_src");
213ad75a51eSRichard Henderson cc_dst = tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_dst),
214c9274b6bSCho, Yu-Chen "cc_dst");
215ad75a51eSRichard Henderson cc_vr = tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_vr),
216c9274b6bSCho, Yu-Chen "cc_vr");
217c9274b6bSCho, Yu-Chen
218c9274b6bSCho, Yu-Chen for (i = 0; i < 16; i++) {
219c9274b6bSCho, Yu-Chen snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i);
220ad75a51eSRichard Henderson regs[i] = tcg_global_mem_new(tcg_env,
221c9274b6bSCho, Yu-Chen offsetof(CPUS390XState, regs[i]),
222c9274b6bSCho, Yu-Chen cpu_reg_names[i]);
223c9274b6bSCho, Yu-Chen }
224c9274b6bSCho, Yu-Chen }
225c9274b6bSCho, Yu-Chen
vec_full_reg_offset(uint8_t reg)226c9274b6bSCho, Yu-Chen static inline int vec_full_reg_offset(uint8_t reg)
227c9274b6bSCho, Yu-Chen {
228c9274b6bSCho, Yu-Chen g_assert(reg < 32);
229c9274b6bSCho, Yu-Chen return offsetof(CPUS390XState, vregs[reg][0]);
230c9274b6bSCho, Yu-Chen }
231c9274b6bSCho, Yu-Chen
vec_reg_offset(uint8_t reg,uint8_t enr,MemOp es)232c9274b6bSCho, Yu-Chen static inline int vec_reg_offset(uint8_t reg, uint8_t enr, MemOp es)
233c9274b6bSCho, Yu-Chen {
234c9274b6bSCho, Yu-Chen /* Convert element size (es) - e.g. MO_8 - to bytes */
235c9274b6bSCho, Yu-Chen const uint8_t bytes = 1 << es;
236c9274b6bSCho, Yu-Chen int offs = enr * bytes;
237c9274b6bSCho, Yu-Chen
238c9274b6bSCho, Yu-Chen /*
239c9274b6bSCho, Yu-Chen * vregs[n][0] is the lowest 8 byte and vregs[n][1] the highest 8 byte
240c9274b6bSCho, Yu-Chen * of the 16 byte vector, on both, little and big endian systems.
241c9274b6bSCho, Yu-Chen *
242c9274b6bSCho, Yu-Chen * Big Endian (target/possible host)
243c9274b6bSCho, Yu-Chen * B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15]
244c9274b6bSCho, Yu-Chen * HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7]
245c9274b6bSCho, Yu-Chen * W: [ 0][ 1] - [ 2][ 3]
246c9274b6bSCho, Yu-Chen * DW: [ 0] - [ 1]
247c9274b6bSCho, Yu-Chen *
248c9274b6bSCho, Yu-Chen * Little Endian (possible host)
249c9274b6bSCho, Yu-Chen * B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8]
250c9274b6bSCho, Yu-Chen * HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4]
251c9274b6bSCho, Yu-Chen * W: [ 1][ 0] - [ 3][ 2]
252c9274b6bSCho, Yu-Chen * DW: [ 0] - [ 1]
253c9274b6bSCho, Yu-Chen *
254c9274b6bSCho, Yu-Chen * For 16 byte elements, the two 8 byte halves will not form a host
255c9274b6bSCho, Yu-Chen * int128 if the host is little endian, since they're in the wrong order.
256c9274b6bSCho, Yu-Chen * Some operations (e.g. xor) do not care. For operations like addition,
257c9274b6bSCho, Yu-Chen * the two 8 byte elements have to be loaded separately. Let's force all
258c9274b6bSCho, Yu-Chen * 16 byte operations to handle it in a special way.
259c9274b6bSCho, Yu-Chen */
260c9274b6bSCho, Yu-Chen g_assert(es <= MO_64);
261e03b5686SMarc-André Lureau #if !HOST_BIG_ENDIAN
262c9274b6bSCho, Yu-Chen offs ^= (8 - bytes);
263c9274b6bSCho, Yu-Chen #endif
264c9274b6bSCho, Yu-Chen return offs + vec_full_reg_offset(reg);
265c9274b6bSCho, Yu-Chen }
266c9274b6bSCho, Yu-Chen
freg64_offset(uint8_t reg)267c9274b6bSCho, Yu-Chen static inline int freg64_offset(uint8_t reg)
268c9274b6bSCho, Yu-Chen {
269c9274b6bSCho, Yu-Chen g_assert(reg < 16);
270c9274b6bSCho, Yu-Chen return vec_reg_offset(reg, 0, MO_64);
271c9274b6bSCho, Yu-Chen }
272c9274b6bSCho, Yu-Chen
freg32_offset(uint8_t reg)273c9274b6bSCho, Yu-Chen static inline int freg32_offset(uint8_t reg)
274c9274b6bSCho, Yu-Chen {
275c9274b6bSCho, Yu-Chen g_assert(reg < 16);
276c9274b6bSCho, Yu-Chen return vec_reg_offset(reg, 0, MO_32);
277c9274b6bSCho, Yu-Chen }
278c9274b6bSCho, Yu-Chen
load_reg(int reg)279c9274b6bSCho, Yu-Chen static TCGv_i64 load_reg(int reg)
280c9274b6bSCho, Yu-Chen {
281c9274b6bSCho, Yu-Chen TCGv_i64 r = tcg_temp_new_i64();
282c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(r, regs[reg]);
283c9274b6bSCho, Yu-Chen return r;
284c9274b6bSCho, Yu-Chen }
285c9274b6bSCho, Yu-Chen
load_freg(int reg)286c9274b6bSCho, Yu-Chen static TCGv_i64 load_freg(int reg)
287c9274b6bSCho, Yu-Chen {
288c9274b6bSCho, Yu-Chen TCGv_i64 r = tcg_temp_new_i64();
289c9274b6bSCho, Yu-Chen
290ad75a51eSRichard Henderson tcg_gen_ld_i64(r, tcg_env, freg64_offset(reg));
291c9274b6bSCho, Yu-Chen return r;
292c9274b6bSCho, Yu-Chen }
293c9274b6bSCho, Yu-Chen
load_freg32_i64(int reg)294c9274b6bSCho, Yu-Chen static TCGv_i64 load_freg32_i64(int reg)
295c9274b6bSCho, Yu-Chen {
296c9274b6bSCho, Yu-Chen TCGv_i64 r = tcg_temp_new_i64();
297c9274b6bSCho, Yu-Chen
298ad75a51eSRichard Henderson tcg_gen_ld32u_i64(r, tcg_env, freg32_offset(reg));
299c9274b6bSCho, Yu-Chen return r;
300c9274b6bSCho, Yu-Chen }
301c9274b6bSCho, Yu-Chen
load_freg_128(int reg)3022b91240fSRichard Henderson static TCGv_i128 load_freg_128(int reg)
3032b91240fSRichard Henderson {
3042b91240fSRichard Henderson TCGv_i64 h = load_freg(reg);
3052b91240fSRichard Henderson TCGv_i64 l = load_freg(reg + 2);
3062b91240fSRichard Henderson TCGv_i128 r = tcg_temp_new_i128();
3072b91240fSRichard Henderson
3082b91240fSRichard Henderson tcg_gen_concat_i64_i128(r, l, h);
3092b91240fSRichard Henderson return r;
3102b91240fSRichard Henderson }
3112b91240fSRichard Henderson
store_reg(int reg,TCGv_i64 v)312c9274b6bSCho, Yu-Chen static void store_reg(int reg, TCGv_i64 v)
313c9274b6bSCho, Yu-Chen {
314c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(regs[reg], v);
315c9274b6bSCho, Yu-Chen }
316c9274b6bSCho, Yu-Chen
store_freg(int reg,TCGv_i64 v)317c9274b6bSCho, Yu-Chen static void store_freg(int reg, TCGv_i64 v)
318c9274b6bSCho, Yu-Chen {
319ad75a51eSRichard Henderson tcg_gen_st_i64(v, tcg_env, freg64_offset(reg));
320c9274b6bSCho, Yu-Chen }
321c9274b6bSCho, Yu-Chen
store_reg32_i64(int reg,TCGv_i64 v)322c9274b6bSCho, Yu-Chen static void store_reg32_i64(int reg, TCGv_i64 v)
323c9274b6bSCho, Yu-Chen {
324c9274b6bSCho, Yu-Chen /* 32 bit register writes keep the upper half */
325c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
326c9274b6bSCho, Yu-Chen }
327c9274b6bSCho, Yu-Chen
store_reg32h_i64(int reg,TCGv_i64 v)328c9274b6bSCho, Yu-Chen static void store_reg32h_i64(int reg, TCGv_i64 v)
329c9274b6bSCho, Yu-Chen {
330c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(regs[reg], regs[reg], v, 32, 32);
331c9274b6bSCho, Yu-Chen }
332c9274b6bSCho, Yu-Chen
store_freg32_i64(int reg,TCGv_i64 v)333c9274b6bSCho, Yu-Chen static void store_freg32_i64(int reg, TCGv_i64 v)
334c9274b6bSCho, Yu-Chen {
335ad75a51eSRichard Henderson tcg_gen_st32_i64(v, tcg_env, freg32_offset(reg));
336c9274b6bSCho, Yu-Chen }
337c9274b6bSCho, Yu-Chen
update_psw_addr(DisasContext * s)338c9274b6bSCho, Yu-Chen static void update_psw_addr(DisasContext *s)
339c9274b6bSCho, Yu-Chen {
340c9274b6bSCho, Yu-Chen /* psw.addr */
341c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(psw_addr, s->base.pc_next);
342c9274b6bSCho, Yu-Chen }
343c9274b6bSCho, Yu-Chen
per_branch(DisasContext * s,TCGv_i64 dest)34453313396SRichard Henderson static void per_branch(DisasContext *s, TCGv_i64 dest)
345c9274b6bSCho, Yu-Chen {
346c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
34762613ca0SRichard Henderson if (s->base.tb->flags & FLAG_MASK_PER_BRANCH) {
34853313396SRichard Henderson gen_helper_per_branch(tcg_env, dest, tcg_constant_i32(s->ilen));
349c9274b6bSCho, Yu-Chen }
350c9274b6bSCho, Yu-Chen #endif
351c9274b6bSCho, Yu-Chen }
352c9274b6bSCho, Yu-Chen
per_breaking_event(DisasContext * s)353c9274b6bSCho, Yu-Chen static void per_breaking_event(DisasContext *s)
354c9274b6bSCho, Yu-Chen {
355c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(gbea, s->base.pc_next);
356c9274b6bSCho, Yu-Chen }
357c9274b6bSCho, Yu-Chen
update_cc_op(DisasContext * s)358c9274b6bSCho, Yu-Chen static void update_cc_op(DisasContext *s)
359c9274b6bSCho, Yu-Chen {
360c9274b6bSCho, Yu-Chen if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
361c9274b6bSCho, Yu-Chen tcg_gen_movi_i32(cc_op, s->cc_op);
362c9274b6bSCho, Yu-Chen }
363c9274b6bSCho, Yu-Chen }
364c9274b6bSCho, Yu-Chen
ld_code2(CPUS390XState * env,DisasContext * s,uint64_t pc)3654e116893SIlya Leoshkevich static inline uint64_t ld_code2(CPUS390XState *env, DisasContext *s,
3664e116893SIlya Leoshkevich uint64_t pc)
367c9274b6bSCho, Yu-Chen {
3684e116893SIlya Leoshkevich return (uint64_t)translator_lduw(env, &s->base, pc);
369c9274b6bSCho, Yu-Chen }
370c9274b6bSCho, Yu-Chen
ld_code4(CPUS390XState * env,DisasContext * s,uint64_t pc)3714e116893SIlya Leoshkevich static inline uint64_t ld_code4(CPUS390XState *env, DisasContext *s,
3724e116893SIlya Leoshkevich uint64_t pc)
373c9274b6bSCho, Yu-Chen {
3744e116893SIlya Leoshkevich return (uint64_t)(uint32_t)translator_ldl(env, &s->base, pc);
375c9274b6bSCho, Yu-Chen }
376c9274b6bSCho, Yu-Chen
get_mem_index(DisasContext * s)377c9274b6bSCho, Yu-Chen static int get_mem_index(DisasContext *s)
378c9274b6bSCho, Yu-Chen {
379c9274b6bSCho, Yu-Chen #ifdef CONFIG_USER_ONLY
380c9274b6bSCho, Yu-Chen return MMU_USER_IDX;
381c9274b6bSCho, Yu-Chen #else
382c9274b6bSCho, Yu-Chen if (!(s->base.tb->flags & FLAG_MASK_DAT)) {
383c9274b6bSCho, Yu-Chen return MMU_REAL_IDX;
384c9274b6bSCho, Yu-Chen }
385c9274b6bSCho, Yu-Chen
386c9274b6bSCho, Yu-Chen switch (s->base.tb->flags & FLAG_MASK_ASC) {
387c9274b6bSCho, Yu-Chen case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
388c9274b6bSCho, Yu-Chen return MMU_PRIMARY_IDX;
389c9274b6bSCho, Yu-Chen case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
390c9274b6bSCho, Yu-Chen return MMU_SECONDARY_IDX;
391c9274b6bSCho, Yu-Chen case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
392c9274b6bSCho, Yu-Chen return MMU_HOME_IDX;
393c9274b6bSCho, Yu-Chen default:
394732e89f4SRichard Henderson g_assert_not_reached();
395c9274b6bSCho, Yu-Chen }
396c9274b6bSCho, Yu-Chen #endif
397c9274b6bSCho, Yu-Chen }
398c9274b6bSCho, Yu-Chen
gen_exception(int excp)399c9274b6bSCho, Yu-Chen static void gen_exception(int excp)
400c9274b6bSCho, Yu-Chen {
401ad75a51eSRichard Henderson gen_helper_exception(tcg_env, tcg_constant_i32(excp));
402c9274b6bSCho, Yu-Chen }
403c9274b6bSCho, Yu-Chen
gen_program_exception(DisasContext * s,int code)404c9274b6bSCho, Yu-Chen static void gen_program_exception(DisasContext *s, int code)
405c9274b6bSCho, Yu-Chen {
406cced0d65SMichael Tokarev /* Remember what pgm exception this was. */
407ad75a51eSRichard Henderson tcg_gen_st_i32(tcg_constant_i32(code), tcg_env,
408f1ea739bSRichard Henderson offsetof(CPUS390XState, int_pgm_code));
409c9274b6bSCho, Yu-Chen
410ad75a51eSRichard Henderson tcg_gen_st_i32(tcg_constant_i32(s->ilen), tcg_env,
411f1ea739bSRichard Henderson offsetof(CPUS390XState, int_pgm_ilen));
412c9274b6bSCho, Yu-Chen
413c9274b6bSCho, Yu-Chen /* update the psw */
414c9274b6bSCho, Yu-Chen update_psw_addr(s);
415c9274b6bSCho, Yu-Chen
416c9274b6bSCho, Yu-Chen /* Save off cc. */
417c9274b6bSCho, Yu-Chen update_cc_op(s);
418c9274b6bSCho, Yu-Chen
419c9274b6bSCho, Yu-Chen /* Trigger exception. */
420c9274b6bSCho, Yu-Chen gen_exception(EXCP_PGM);
421c9274b6bSCho, Yu-Chen }
422c9274b6bSCho, Yu-Chen
gen_illegal_opcode(DisasContext * s)423c9274b6bSCho, Yu-Chen static inline void gen_illegal_opcode(DisasContext *s)
424c9274b6bSCho, Yu-Chen {
425c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_OPERATION);
426c9274b6bSCho, Yu-Chen }
427c9274b6bSCho, Yu-Chen
gen_data_exception(uint8_t dxc)428c9274b6bSCho, Yu-Chen static inline void gen_data_exception(uint8_t dxc)
429c9274b6bSCho, Yu-Chen {
430ad75a51eSRichard Henderson gen_helper_data_exception(tcg_env, tcg_constant_i32(dxc));
431c9274b6bSCho, Yu-Chen }
432c9274b6bSCho, Yu-Chen
gen_trap(DisasContext * s)433c9274b6bSCho, Yu-Chen static inline void gen_trap(DisasContext *s)
434c9274b6bSCho, Yu-Chen {
435c9274b6bSCho, Yu-Chen /* Set DXC to 0xff */
436c9274b6bSCho, Yu-Chen gen_data_exception(0xff);
437c9274b6bSCho, Yu-Chen }
438c9274b6bSCho, Yu-Chen
gen_addi_and_wrap_i64(DisasContext * s,TCGv_i64 dst,TCGv_i64 src,int64_t imm)439c9274b6bSCho, Yu-Chen static void gen_addi_and_wrap_i64(DisasContext *s, TCGv_i64 dst, TCGv_i64 src,
440c9274b6bSCho, Yu-Chen int64_t imm)
441c9274b6bSCho, Yu-Chen {
442c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(dst, src, imm);
443c9274b6bSCho, Yu-Chen if (!(s->base.tb->flags & FLAG_MASK_64)) {
444c9274b6bSCho, Yu-Chen if (s->base.tb->flags & FLAG_MASK_32) {
445c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(dst, dst, 0x7fffffff);
446c9274b6bSCho, Yu-Chen } else {
447c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(dst, dst, 0x00ffffff);
448c9274b6bSCho, Yu-Chen }
449c9274b6bSCho, Yu-Chen }
450c9274b6bSCho, Yu-Chen }
451c9274b6bSCho, Yu-Chen
get_address(DisasContext * s,int x2,int b2,int d2)452c9274b6bSCho, Yu-Chen static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
453c9274b6bSCho, Yu-Chen {
454c9274b6bSCho, Yu-Chen TCGv_i64 tmp = tcg_temp_new_i64();
455c9274b6bSCho, Yu-Chen
456c9274b6bSCho, Yu-Chen /*
457c9274b6bSCho, Yu-Chen * Note that d2 is limited to 20 bits, signed. If we crop negative
45844ee69eaSThomas Huth * displacements early we create larger immediate addends.
459c9274b6bSCho, Yu-Chen */
460c9274b6bSCho, Yu-Chen if (b2 && x2) {
461c9274b6bSCho, Yu-Chen tcg_gen_add_i64(tmp, regs[b2], regs[x2]);
462c9274b6bSCho, Yu-Chen gen_addi_and_wrap_i64(s, tmp, tmp, d2);
463c9274b6bSCho, Yu-Chen } else if (b2) {
464c9274b6bSCho, Yu-Chen gen_addi_and_wrap_i64(s, tmp, regs[b2], d2);
465c9274b6bSCho, Yu-Chen } else if (x2) {
466c9274b6bSCho, Yu-Chen gen_addi_and_wrap_i64(s, tmp, regs[x2], d2);
467c9274b6bSCho, Yu-Chen } else if (!(s->base.tb->flags & FLAG_MASK_64)) {
468c9274b6bSCho, Yu-Chen if (s->base.tb->flags & FLAG_MASK_32) {
469c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(tmp, d2 & 0x7fffffff);
470c9274b6bSCho, Yu-Chen } else {
471c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(tmp, d2 & 0x00ffffff);
472c9274b6bSCho, Yu-Chen }
473c9274b6bSCho, Yu-Chen } else {
474c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(tmp, d2);
475c9274b6bSCho, Yu-Chen }
476c9274b6bSCho, Yu-Chen
477c9274b6bSCho, Yu-Chen return tmp;
478c9274b6bSCho, Yu-Chen }
479c9274b6bSCho, Yu-Chen
live_cc_data(DisasContext * s)480c9274b6bSCho, Yu-Chen static inline bool live_cc_data(DisasContext *s)
481c9274b6bSCho, Yu-Chen {
482c9274b6bSCho, Yu-Chen return (s->cc_op != CC_OP_DYNAMIC
483c9274b6bSCho, Yu-Chen && s->cc_op != CC_OP_STATIC
484c9274b6bSCho, Yu-Chen && s->cc_op > 3);
485c9274b6bSCho, Yu-Chen }
486c9274b6bSCho, Yu-Chen
gen_op_movi_cc(DisasContext * s,uint32_t val)487c9274b6bSCho, Yu-Chen static inline void gen_op_movi_cc(DisasContext *s, uint32_t val)
488c9274b6bSCho, Yu-Chen {
489c9274b6bSCho, Yu-Chen if (live_cc_data(s)) {
490c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_src);
491c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_dst);
492c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_vr);
493c9274b6bSCho, Yu-Chen }
494c9274b6bSCho, Yu-Chen s->cc_op = CC_OP_CONST0 + val;
495c9274b6bSCho, Yu-Chen }
496c9274b6bSCho, Yu-Chen
gen_op_update1_cc_i64(DisasContext * s,enum cc_op op,TCGv_i64 dst)497c9274b6bSCho, Yu-Chen static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
498c9274b6bSCho, Yu-Chen {
499c9274b6bSCho, Yu-Chen if (live_cc_data(s)) {
500c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_src);
501c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_vr);
502c9274b6bSCho, Yu-Chen }
503c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(cc_dst, dst);
504c9274b6bSCho, Yu-Chen s->cc_op = op;
505c9274b6bSCho, Yu-Chen }
506c9274b6bSCho, Yu-Chen
gen_op_update2_cc_i64(DisasContext * s,enum cc_op op,TCGv_i64 src,TCGv_i64 dst)507c9274b6bSCho, Yu-Chen static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
508c9274b6bSCho, Yu-Chen TCGv_i64 dst)
509c9274b6bSCho, Yu-Chen {
510c9274b6bSCho, Yu-Chen if (live_cc_data(s)) {
511c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_vr);
512c9274b6bSCho, Yu-Chen }
513c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(cc_src, src);
514c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(cc_dst, dst);
515c9274b6bSCho, Yu-Chen s->cc_op = op;
516c9274b6bSCho, Yu-Chen }
517c9274b6bSCho, Yu-Chen
gen_op_update3_cc_i64(DisasContext * s,enum cc_op op,TCGv_i64 src,TCGv_i64 dst,TCGv_i64 vr)518c9274b6bSCho, Yu-Chen static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
519c9274b6bSCho, Yu-Chen TCGv_i64 dst, TCGv_i64 vr)
520c9274b6bSCho, Yu-Chen {
521c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(cc_src, src);
522c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(cc_dst, dst);
523c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(cc_vr, vr);
524c9274b6bSCho, Yu-Chen s->cc_op = op;
525c9274b6bSCho, Yu-Chen }
526c9274b6bSCho, Yu-Chen
set_cc_nz_u64(DisasContext * s,TCGv_i64 val)527c9274b6bSCho, Yu-Chen static void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
528c9274b6bSCho, Yu-Chen {
529c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NZ, val);
530c9274b6bSCho, Yu-Chen }
531c9274b6bSCho, Yu-Chen
532c9274b6bSCho, Yu-Chen /* CC value is in env->cc_op */
set_cc_static(DisasContext * s)533c9274b6bSCho, Yu-Chen static void set_cc_static(DisasContext *s)
534c9274b6bSCho, Yu-Chen {
535c9274b6bSCho, Yu-Chen if (live_cc_data(s)) {
536c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_src);
537c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_dst);
538c9274b6bSCho, Yu-Chen tcg_gen_discard_i64(cc_vr);
539c9274b6bSCho, Yu-Chen }
540c9274b6bSCho, Yu-Chen s->cc_op = CC_OP_STATIC;
541c9274b6bSCho, Yu-Chen }
542c9274b6bSCho, Yu-Chen
543c9274b6bSCho, Yu-Chen /* calculates cc into cc_op */
gen_op_calc_cc(DisasContext * s)544c9274b6bSCho, Yu-Chen static void gen_op_calc_cc(DisasContext *s)
545c9274b6bSCho, Yu-Chen {
546c9274b6bSCho, Yu-Chen TCGv_i32 local_cc_op = NULL;
547c9274b6bSCho, Yu-Chen TCGv_i64 dummy = NULL;
548c9274b6bSCho, Yu-Chen
549c9274b6bSCho, Yu-Chen switch (s->cc_op) {
550c9274b6bSCho, Yu-Chen default:
551f1ea739bSRichard Henderson dummy = tcg_constant_i64(0);
552c9274b6bSCho, Yu-Chen /* FALLTHRU */
553c9274b6bSCho, Yu-Chen case CC_OP_ADD_64:
554c9274b6bSCho, Yu-Chen case CC_OP_SUB_64:
555c9274b6bSCho, Yu-Chen case CC_OP_ADD_32:
556c9274b6bSCho, Yu-Chen case CC_OP_SUB_32:
557f1ea739bSRichard Henderson local_cc_op = tcg_constant_i32(s->cc_op);
558c9274b6bSCho, Yu-Chen break;
559c9274b6bSCho, Yu-Chen case CC_OP_CONST0:
560c9274b6bSCho, Yu-Chen case CC_OP_CONST1:
561c9274b6bSCho, Yu-Chen case CC_OP_CONST2:
562c9274b6bSCho, Yu-Chen case CC_OP_CONST3:
563c9274b6bSCho, Yu-Chen case CC_OP_STATIC:
564c9274b6bSCho, Yu-Chen case CC_OP_DYNAMIC:
565c9274b6bSCho, Yu-Chen break;
566c9274b6bSCho, Yu-Chen }
567c9274b6bSCho, Yu-Chen
568c9274b6bSCho, Yu-Chen switch (s->cc_op) {
569c9274b6bSCho, Yu-Chen case CC_OP_CONST0:
570c9274b6bSCho, Yu-Chen case CC_OP_CONST1:
571c9274b6bSCho, Yu-Chen case CC_OP_CONST2:
572c9274b6bSCho, Yu-Chen case CC_OP_CONST3:
573c9274b6bSCho, Yu-Chen /* s->cc_op is the cc value */
574c9274b6bSCho, Yu-Chen tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
575c9274b6bSCho, Yu-Chen break;
576c9274b6bSCho, Yu-Chen case CC_OP_STATIC:
577c9274b6bSCho, Yu-Chen /* env->cc_op already is the cc value */
578c9274b6bSCho, Yu-Chen break;
579c9274b6bSCho, Yu-Chen case CC_OP_NZ:
580b5deff74SRichard Henderson tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0);
581b5deff74SRichard Henderson tcg_gen_extrl_i64_i32(cc_op, cc_dst);
582b5deff74SRichard Henderson break;
583c9274b6bSCho, Yu-Chen case CC_OP_ABS_64:
584c9274b6bSCho, Yu-Chen case CC_OP_NABS_64:
585c9274b6bSCho, Yu-Chen case CC_OP_ABS_32:
586c9274b6bSCho, Yu-Chen case CC_OP_NABS_32:
587c9274b6bSCho, Yu-Chen case CC_OP_LTGT0_32:
588c9274b6bSCho, Yu-Chen case CC_OP_LTGT0_64:
589c9274b6bSCho, Yu-Chen case CC_OP_COMP_32:
590c9274b6bSCho, Yu-Chen case CC_OP_COMP_64:
591c9274b6bSCho, Yu-Chen case CC_OP_NZ_F32:
592c9274b6bSCho, Yu-Chen case CC_OP_NZ_F64:
593c9274b6bSCho, Yu-Chen case CC_OP_FLOGR:
594c9274b6bSCho, Yu-Chen case CC_OP_LCBB:
595c9274b6bSCho, Yu-Chen case CC_OP_MULS_32:
596c9274b6bSCho, Yu-Chen /* 1 argument */
597ad75a51eSRichard Henderson gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, dummy, cc_dst, dummy);
598c9274b6bSCho, Yu-Chen break;
599c9274b6bSCho, Yu-Chen case CC_OP_ADDU:
600c9274b6bSCho, Yu-Chen case CC_OP_ICM:
601c9274b6bSCho, Yu-Chen case CC_OP_LTGT_32:
602c9274b6bSCho, Yu-Chen case CC_OP_LTGT_64:
603c9274b6bSCho, Yu-Chen case CC_OP_LTUGTU_32:
604c9274b6bSCho, Yu-Chen case CC_OP_LTUGTU_64:
605c9274b6bSCho, Yu-Chen case CC_OP_TM_32:
606c9274b6bSCho, Yu-Chen case CC_OP_TM_64:
6076da170beSIlya Leoshkevich case CC_OP_SLA:
608c9274b6bSCho, Yu-Chen case CC_OP_SUBU:
609c9274b6bSCho, Yu-Chen case CC_OP_NZ_F128:
610c9274b6bSCho, Yu-Chen case CC_OP_VC:
611c9274b6bSCho, Yu-Chen case CC_OP_MULS_64:
612c9274b6bSCho, Yu-Chen /* 2 arguments */
613ad75a51eSRichard Henderson gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, dummy);
614c9274b6bSCho, Yu-Chen break;
615c9274b6bSCho, Yu-Chen case CC_OP_ADD_64:
616c9274b6bSCho, Yu-Chen case CC_OP_SUB_64:
617c9274b6bSCho, Yu-Chen case CC_OP_ADD_32:
618c9274b6bSCho, Yu-Chen case CC_OP_SUB_32:
619c9274b6bSCho, Yu-Chen /* 3 arguments */
620ad75a51eSRichard Henderson gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, cc_vr);
621c9274b6bSCho, Yu-Chen break;
622c9274b6bSCho, Yu-Chen case CC_OP_DYNAMIC:
623c9274b6bSCho, Yu-Chen /* unknown operation - assume 3 arguments and cc_op in env */
624ad75a51eSRichard Henderson gen_helper_calc_cc(cc_op, tcg_env, cc_op, cc_src, cc_dst, cc_vr);
625c9274b6bSCho, Yu-Chen break;
626c9274b6bSCho, Yu-Chen default:
627732e89f4SRichard Henderson g_assert_not_reached();
628c9274b6bSCho, Yu-Chen }
629c9274b6bSCho, Yu-Chen
630c9274b6bSCho, Yu-Chen /* We now have cc in cc_op as constant */
631c9274b6bSCho, Yu-Chen set_cc_static(s);
632c9274b6bSCho, Yu-Chen }
633c9274b6bSCho, Yu-Chen
use_goto_tb(DisasContext * s,uint64_t dest)634c9274b6bSCho, Yu-Chen static bool use_goto_tb(DisasContext *s, uint64_t dest)
635c9274b6bSCho, Yu-Chen {
63657e28d34SPeter Maydell return translator_use_goto_tb(&s->base, dest);
637c9274b6bSCho, Yu-Chen }
638c9274b6bSCho, Yu-Chen
account_noninline_branch(DisasContext * s,int cc_op)639c9274b6bSCho, Yu-Chen static void account_noninline_branch(DisasContext *s, int cc_op)
640c9274b6bSCho, Yu-Chen {
641c9274b6bSCho, Yu-Chen #ifdef DEBUG_INLINE_BRANCHES
642c9274b6bSCho, Yu-Chen inline_branch_miss[cc_op]++;
643c9274b6bSCho, Yu-Chen #endif
644c9274b6bSCho, Yu-Chen }
645c9274b6bSCho, Yu-Chen
account_inline_branch(DisasContext * s,int cc_op)646c9274b6bSCho, Yu-Chen static void account_inline_branch(DisasContext *s, int cc_op)
647c9274b6bSCho, Yu-Chen {
648c9274b6bSCho, Yu-Chen #ifdef DEBUG_INLINE_BRANCHES
649c9274b6bSCho, Yu-Chen inline_branch_hit[cc_op]++;
650c9274b6bSCho, Yu-Chen #endif
651c9274b6bSCho, Yu-Chen }
652c9274b6bSCho, Yu-Chen
653c9274b6bSCho, Yu-Chen /* Table of mask values to comparison codes, given a comparison as input.
654c9274b6bSCho, Yu-Chen For such, CC=3 should not be possible. */
655c9274b6bSCho, Yu-Chen static const TCGCond ltgt_cond[16] = {
656c9274b6bSCho, Yu-Chen TCG_COND_NEVER, TCG_COND_NEVER, /* | | | x */
657c9274b6bSCho, Yu-Chen TCG_COND_GT, TCG_COND_GT, /* | | GT | x */
658c9274b6bSCho, Yu-Chen TCG_COND_LT, TCG_COND_LT, /* | LT | | x */
659c9274b6bSCho, Yu-Chen TCG_COND_NE, TCG_COND_NE, /* | LT | GT | x */
660c9274b6bSCho, Yu-Chen TCG_COND_EQ, TCG_COND_EQ, /* EQ | | | x */
661c9274b6bSCho, Yu-Chen TCG_COND_GE, TCG_COND_GE, /* EQ | | GT | x */
662c9274b6bSCho, Yu-Chen TCG_COND_LE, TCG_COND_LE, /* EQ | LT | | x */
663c9274b6bSCho, Yu-Chen TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | LT | GT | x */
664c9274b6bSCho, Yu-Chen };
665c9274b6bSCho, Yu-Chen
666c9274b6bSCho, Yu-Chen /* Table of mask values to comparison codes, given a logic op as input.
667c9274b6bSCho, Yu-Chen For such, only CC=0 and CC=1 should be possible. */
668c9274b6bSCho, Yu-Chen static const TCGCond nz_cond[16] = {
669c9274b6bSCho, Yu-Chen TCG_COND_NEVER, TCG_COND_NEVER, /* | | x | x */
670c9274b6bSCho, Yu-Chen TCG_COND_NEVER, TCG_COND_NEVER,
671c9274b6bSCho, Yu-Chen TCG_COND_NE, TCG_COND_NE, /* | NE | x | x */
672c9274b6bSCho, Yu-Chen TCG_COND_NE, TCG_COND_NE,
673c9274b6bSCho, Yu-Chen TCG_COND_EQ, TCG_COND_EQ, /* EQ | | x | x */
674c9274b6bSCho, Yu-Chen TCG_COND_EQ, TCG_COND_EQ,
675c9274b6bSCho, Yu-Chen TCG_COND_ALWAYS, TCG_COND_ALWAYS, /* EQ | NE | x | x */
676c9274b6bSCho, Yu-Chen TCG_COND_ALWAYS, TCG_COND_ALWAYS,
677c9274b6bSCho, Yu-Chen };
678c9274b6bSCho, Yu-Chen
679c9274b6bSCho, Yu-Chen /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
680c9274b6bSCho, Yu-Chen details required to generate a TCG comparison. */
disas_jcc(DisasContext * s,DisasCompare * c,uint32_t mask)681c9274b6bSCho, Yu-Chen static void disas_jcc(DisasContext *s, DisasCompare *c, uint32_t mask)
682c9274b6bSCho, Yu-Chen {
683c9274b6bSCho, Yu-Chen TCGCond cond;
684c9274b6bSCho, Yu-Chen enum cc_op old_cc_op = s->cc_op;
685c9274b6bSCho, Yu-Chen
686c9274b6bSCho, Yu-Chen if (mask == 15 || mask == 0) {
687c9274b6bSCho, Yu-Chen c->cond = (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER);
688c9274b6bSCho, Yu-Chen c->u.s32.a = cc_op;
689c9274b6bSCho, Yu-Chen c->u.s32.b = cc_op;
690c9274b6bSCho, Yu-Chen c->is_64 = false;
691c9274b6bSCho, Yu-Chen return;
692c9274b6bSCho, Yu-Chen }
693c9274b6bSCho, Yu-Chen
694c9274b6bSCho, Yu-Chen /* Find the TCG condition for the mask + cc op. */
695c9274b6bSCho, Yu-Chen switch (old_cc_op) {
696c9274b6bSCho, Yu-Chen case CC_OP_LTGT0_32:
697c9274b6bSCho, Yu-Chen case CC_OP_LTGT0_64:
698c9274b6bSCho, Yu-Chen case CC_OP_LTGT_32:
699c9274b6bSCho, Yu-Chen case CC_OP_LTGT_64:
700c9274b6bSCho, Yu-Chen cond = ltgt_cond[mask];
701c9274b6bSCho, Yu-Chen if (cond == TCG_COND_NEVER) {
702c9274b6bSCho, Yu-Chen goto do_dynamic;
703c9274b6bSCho, Yu-Chen }
704c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
705c9274b6bSCho, Yu-Chen break;
706c9274b6bSCho, Yu-Chen
707c9274b6bSCho, Yu-Chen case CC_OP_LTUGTU_32:
708c9274b6bSCho, Yu-Chen case CC_OP_LTUGTU_64:
709c9274b6bSCho, Yu-Chen cond = tcg_unsigned_cond(ltgt_cond[mask]);
710c9274b6bSCho, Yu-Chen if (cond == TCG_COND_NEVER) {
711c9274b6bSCho, Yu-Chen goto do_dynamic;
712c9274b6bSCho, Yu-Chen }
713c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
714c9274b6bSCho, Yu-Chen break;
715c9274b6bSCho, Yu-Chen
716c9274b6bSCho, Yu-Chen case CC_OP_NZ:
717c9274b6bSCho, Yu-Chen cond = nz_cond[mask];
718c9274b6bSCho, Yu-Chen if (cond == TCG_COND_NEVER) {
719c9274b6bSCho, Yu-Chen goto do_dynamic;
720c9274b6bSCho, Yu-Chen }
721c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
722c9274b6bSCho, Yu-Chen break;
723c9274b6bSCho, Yu-Chen
724c9274b6bSCho, Yu-Chen case CC_OP_TM_32:
725c9274b6bSCho, Yu-Chen case CC_OP_TM_64:
726c9274b6bSCho, Yu-Chen switch (mask) {
727c9274b6bSCho, Yu-Chen case 8:
7287da3601eSRichard Henderson cond = TCG_COND_TSTEQ;
729c9274b6bSCho, Yu-Chen break;
730c9274b6bSCho, Yu-Chen case 4 | 2 | 1:
7317da3601eSRichard Henderson cond = TCG_COND_TSTNE;
732c9274b6bSCho, Yu-Chen break;
733c9274b6bSCho, Yu-Chen default:
734c9274b6bSCho, Yu-Chen goto do_dynamic;
735c9274b6bSCho, Yu-Chen }
736c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
737c9274b6bSCho, Yu-Chen break;
738c9274b6bSCho, Yu-Chen
739c9274b6bSCho, Yu-Chen case CC_OP_ICM:
740c9274b6bSCho, Yu-Chen switch (mask) {
741c9274b6bSCho, Yu-Chen case 8:
7427da3601eSRichard Henderson cond = TCG_COND_TSTEQ;
743c9274b6bSCho, Yu-Chen break;
744c9274b6bSCho, Yu-Chen case 4 | 2 | 1:
745c9274b6bSCho, Yu-Chen case 4 | 2:
7467da3601eSRichard Henderson cond = TCG_COND_TSTNE;
747c9274b6bSCho, Yu-Chen break;
748c9274b6bSCho, Yu-Chen default:
749c9274b6bSCho, Yu-Chen goto do_dynamic;
750c9274b6bSCho, Yu-Chen }
751c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
752c9274b6bSCho, Yu-Chen break;
753c9274b6bSCho, Yu-Chen
754c9274b6bSCho, Yu-Chen case CC_OP_FLOGR:
755c9274b6bSCho, Yu-Chen switch (mask & 0xa) {
756c9274b6bSCho, Yu-Chen case 8: /* src == 0 -> no one bit found */
757c9274b6bSCho, Yu-Chen cond = TCG_COND_EQ;
758c9274b6bSCho, Yu-Chen break;
759c9274b6bSCho, Yu-Chen case 2: /* src != 0 -> one bit found */
760c9274b6bSCho, Yu-Chen cond = TCG_COND_NE;
761c9274b6bSCho, Yu-Chen break;
762c9274b6bSCho, Yu-Chen default:
763c9274b6bSCho, Yu-Chen goto do_dynamic;
764c9274b6bSCho, Yu-Chen }
765c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
766c9274b6bSCho, Yu-Chen break;
767c9274b6bSCho, Yu-Chen
768c9274b6bSCho, Yu-Chen case CC_OP_ADDU:
769c9274b6bSCho, Yu-Chen case CC_OP_SUBU:
770c9274b6bSCho, Yu-Chen switch (mask) {
771c9274b6bSCho, Yu-Chen case 8 | 2: /* result == 0 */
772c9274b6bSCho, Yu-Chen cond = TCG_COND_EQ;
773c9274b6bSCho, Yu-Chen break;
774c9274b6bSCho, Yu-Chen case 4 | 1: /* result != 0 */
775c9274b6bSCho, Yu-Chen cond = TCG_COND_NE;
776c9274b6bSCho, Yu-Chen break;
777c9274b6bSCho, Yu-Chen case 8 | 4: /* !carry (borrow) */
778c9274b6bSCho, Yu-Chen cond = old_cc_op == CC_OP_ADDU ? TCG_COND_EQ : TCG_COND_NE;
779c9274b6bSCho, Yu-Chen break;
780c9274b6bSCho, Yu-Chen case 2 | 1: /* carry (!borrow) */
781c9274b6bSCho, Yu-Chen cond = old_cc_op == CC_OP_ADDU ? TCG_COND_NE : TCG_COND_EQ;
782c9274b6bSCho, Yu-Chen break;
783c9274b6bSCho, Yu-Chen default:
784c9274b6bSCho, Yu-Chen goto do_dynamic;
785c9274b6bSCho, Yu-Chen }
786c9274b6bSCho, Yu-Chen account_inline_branch(s, old_cc_op);
787c9274b6bSCho, Yu-Chen break;
788c9274b6bSCho, Yu-Chen
789c9274b6bSCho, Yu-Chen default:
790c9274b6bSCho, Yu-Chen do_dynamic:
791c9274b6bSCho, Yu-Chen /* Calculate cc value. */
792c9274b6bSCho, Yu-Chen gen_op_calc_cc(s);
793c9274b6bSCho, Yu-Chen /* FALLTHRU */
794c9274b6bSCho, Yu-Chen
795c9274b6bSCho, Yu-Chen case CC_OP_STATIC:
796c9274b6bSCho, Yu-Chen /* Jump based on CC. We'll load up the real cond below;
797c9274b6bSCho, Yu-Chen the assignment here merely avoids a compiler warning. */
798c9274b6bSCho, Yu-Chen account_noninline_branch(s, old_cc_op);
799c9274b6bSCho, Yu-Chen old_cc_op = CC_OP_STATIC;
800c9274b6bSCho, Yu-Chen cond = TCG_COND_NEVER;
801c9274b6bSCho, Yu-Chen break;
802c9274b6bSCho, Yu-Chen }
803c9274b6bSCho, Yu-Chen
804c9274b6bSCho, Yu-Chen /* Load up the arguments of the comparison. */
805c9274b6bSCho, Yu-Chen c->is_64 = true;
806c9274b6bSCho, Yu-Chen switch (old_cc_op) {
807c9274b6bSCho, Yu-Chen case CC_OP_LTGT0_32:
808c9274b6bSCho, Yu-Chen c->is_64 = false;
809c9274b6bSCho, Yu-Chen c->u.s32.a = tcg_temp_new_i32();
810c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst);
811f5d7b0e2SRichard Henderson c->u.s32.b = tcg_constant_i32(0);
812c9274b6bSCho, Yu-Chen break;
813c9274b6bSCho, Yu-Chen case CC_OP_LTGT_32:
814c9274b6bSCho, Yu-Chen case CC_OP_LTUGTU_32:
815c9274b6bSCho, Yu-Chen c->is_64 = false;
816c9274b6bSCho, Yu-Chen c->u.s32.a = tcg_temp_new_i32();
817c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c->u.s32.a, cc_src);
818c9274b6bSCho, Yu-Chen c->u.s32.b = tcg_temp_new_i32();
819c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c->u.s32.b, cc_dst);
820c9274b6bSCho, Yu-Chen break;
821c9274b6bSCho, Yu-Chen
822c9274b6bSCho, Yu-Chen case CC_OP_LTGT0_64:
823c9274b6bSCho, Yu-Chen case CC_OP_NZ:
824c9274b6bSCho, Yu-Chen case CC_OP_FLOGR:
825c9274b6bSCho, Yu-Chen c->u.s64.a = cc_dst;
826f5d7b0e2SRichard Henderson c->u.s64.b = tcg_constant_i64(0);
827c9274b6bSCho, Yu-Chen break;
8287da3601eSRichard Henderson
829c9274b6bSCho, Yu-Chen case CC_OP_LTGT_64:
830c9274b6bSCho, Yu-Chen case CC_OP_LTUGTU_64:
831c9274b6bSCho, Yu-Chen case CC_OP_TM_32:
832c9274b6bSCho, Yu-Chen case CC_OP_TM_64:
833c9274b6bSCho, Yu-Chen case CC_OP_ICM:
8347da3601eSRichard Henderson c->u.s64.a = cc_src;
8357da3601eSRichard Henderson c->u.s64.b = cc_dst;
836c9274b6bSCho, Yu-Chen break;
837c9274b6bSCho, Yu-Chen
838c9274b6bSCho, Yu-Chen case CC_OP_ADDU:
839c9274b6bSCho, Yu-Chen case CC_OP_SUBU:
840c9274b6bSCho, Yu-Chen c->is_64 = true;
841f5d7b0e2SRichard Henderson c->u.s64.b = tcg_constant_i64(0);
842c9274b6bSCho, Yu-Chen switch (mask) {
843c9274b6bSCho, Yu-Chen case 8 | 2:
844c9274b6bSCho, Yu-Chen case 4 | 1: /* result */
845c9274b6bSCho, Yu-Chen c->u.s64.a = cc_dst;
846c9274b6bSCho, Yu-Chen break;
847c9274b6bSCho, Yu-Chen case 8 | 4:
848c9274b6bSCho, Yu-Chen case 2 | 1: /* carry */
849c9274b6bSCho, Yu-Chen c->u.s64.a = cc_src;
850c9274b6bSCho, Yu-Chen break;
851c9274b6bSCho, Yu-Chen default:
852c9274b6bSCho, Yu-Chen g_assert_not_reached();
853c9274b6bSCho, Yu-Chen }
854c9274b6bSCho, Yu-Chen break;
855c9274b6bSCho, Yu-Chen
856c9274b6bSCho, Yu-Chen case CC_OP_STATIC:
857c9274b6bSCho, Yu-Chen c->is_64 = false;
858c9274b6bSCho, Yu-Chen c->u.s32.a = cc_op;
859f9ec459dSRichard Henderson
860f9ec459dSRichard Henderson /* Fold half of the cases using bit 3 to invert. */
861f9ec459dSRichard Henderson switch (mask & 8 ? mask ^ 0xf : mask) {
862f9ec459dSRichard Henderson case 0x1: /* cc == 3 */
863f9ec459dSRichard Henderson cond = TCG_COND_EQ;
864f5d7b0e2SRichard Henderson c->u.s32.b = tcg_constant_i32(3);
865c9274b6bSCho, Yu-Chen break;
866c9274b6bSCho, Yu-Chen case 0x2: /* cc == 2 */
867c9274b6bSCho, Yu-Chen cond = TCG_COND_EQ;
868f5d7b0e2SRichard Henderson c->u.s32.b = tcg_constant_i32(2);
869c9274b6bSCho, Yu-Chen break;
870f9ec459dSRichard Henderson case 0x4: /* cc == 1 */
871c9274b6bSCho, Yu-Chen cond = TCG_COND_EQ;
872f9ec459dSRichard Henderson c->u.s32.b = tcg_constant_i32(1);
873f9ec459dSRichard Henderson break;
874f9ec459dSRichard Henderson case 0x2 | 0x1: /* cc == 2 || cc == 3 => cc > 1 */
875f9ec459dSRichard Henderson cond = TCG_COND_GTU;
876f9ec459dSRichard Henderson c->u.s32.b = tcg_constant_i32(1);
877f9ec459dSRichard Henderson break;
878f9ec459dSRichard Henderson case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
879f9ec459dSRichard Henderson cond = TCG_COND_TSTNE;
880f9ec459dSRichard Henderson c->u.s32.b = tcg_constant_i32(1);
881f9ec459dSRichard Henderson break;
882f9ec459dSRichard Henderson case 0x4 | 0x2: /* cc == 1 || cc == 2 => (cc - 1) <= 1 */
883f9ec459dSRichard Henderson cond = TCG_COND_LEU;
884f9ec459dSRichard Henderson c->u.s32.a = tcg_temp_new_i32();
885f9ec459dSRichard Henderson c->u.s32.b = tcg_constant_i32(1);
886f9ec459dSRichard Henderson tcg_gen_addi_i32(c->u.s32.a, cc_op, -1);
887f9ec459dSRichard Henderson break;
888f9ec459dSRichard Henderson case 0x4 | 0x2 | 0x1: /* cc != 0 */
889f9ec459dSRichard Henderson cond = TCG_COND_NE;
890f9ec459dSRichard Henderson c->u.s32.b = tcg_constant_i32(0);
891c9274b6bSCho, Yu-Chen break;
892c9274b6bSCho, Yu-Chen default:
893f9ec459dSRichard Henderson /* case 0: never, handled above. */
894f9ec459dSRichard Henderson g_assert_not_reached();
895f9ec459dSRichard Henderson }
896f9ec459dSRichard Henderson if (mask & 8) {
897f9ec459dSRichard Henderson cond = tcg_invert_cond(cond);
898c9274b6bSCho, Yu-Chen }
899c9274b6bSCho, Yu-Chen break;
900c9274b6bSCho, Yu-Chen
901c9274b6bSCho, Yu-Chen default:
902c9274b6bSCho, Yu-Chen abort();
903c9274b6bSCho, Yu-Chen }
904c9274b6bSCho, Yu-Chen c->cond = cond;
905c9274b6bSCho, Yu-Chen }
906c9274b6bSCho, Yu-Chen
907c9274b6bSCho, Yu-Chen /* ====================================================================== */
908c9274b6bSCho, Yu-Chen /* Define the insn format enumeration. */
909c9274b6bSCho, Yu-Chen #define F0(N) FMT_##N,
910c9274b6bSCho, Yu-Chen #define F1(N, X1) F0(N)
911c9274b6bSCho, Yu-Chen #define F2(N, X1, X2) F0(N)
912c9274b6bSCho, Yu-Chen #define F3(N, X1, X2, X3) F0(N)
913c9274b6bSCho, Yu-Chen #define F4(N, X1, X2, X3, X4) F0(N)
914c9274b6bSCho, Yu-Chen #define F5(N, X1, X2, X3, X4, X5) F0(N)
915c9274b6bSCho, Yu-Chen #define F6(N, X1, X2, X3, X4, X5, X6) F0(N)
916c9274b6bSCho, Yu-Chen
917c9274b6bSCho, Yu-Chen typedef enum {
9189cef8d99SPhilippe Mathieu-Daudé #include "insn-format.h.inc"
919c9274b6bSCho, Yu-Chen } DisasFormat;
920c9274b6bSCho, Yu-Chen
921c9274b6bSCho, Yu-Chen #undef F0
922c9274b6bSCho, Yu-Chen #undef F1
923c9274b6bSCho, Yu-Chen #undef F2
924c9274b6bSCho, Yu-Chen #undef F3
925c9274b6bSCho, Yu-Chen #undef F4
926c9274b6bSCho, Yu-Chen #undef F5
927c9274b6bSCho, Yu-Chen #undef F6
928c9274b6bSCho, Yu-Chen
929c9274b6bSCho, Yu-Chen /* This is the way fields are to be accessed out of DisasFields. */
930c9274b6bSCho, Yu-Chen #define have_field(S, F) have_field1((S), FLD_O_##F)
931c9274b6bSCho, Yu-Chen #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
932c9274b6bSCho, Yu-Chen
have_field1(const DisasContext * s,enum DisasFieldIndexO c)933c9274b6bSCho, Yu-Chen static bool have_field1(const DisasContext *s, enum DisasFieldIndexO c)
934c9274b6bSCho, Yu-Chen {
935c9274b6bSCho, Yu-Chen return (s->fields.presentO >> c) & 1;
936c9274b6bSCho, Yu-Chen }
937c9274b6bSCho, Yu-Chen
get_field1(const DisasContext * s,enum DisasFieldIndexO o,enum DisasFieldIndexC c)938c9274b6bSCho, Yu-Chen static int get_field1(const DisasContext *s, enum DisasFieldIndexO o,
939c9274b6bSCho, Yu-Chen enum DisasFieldIndexC c)
940c9274b6bSCho, Yu-Chen {
941c9274b6bSCho, Yu-Chen assert(have_field1(s, o));
942c9274b6bSCho, Yu-Chen return s->fields.c[c];
943c9274b6bSCho, Yu-Chen }
944c9274b6bSCho, Yu-Chen
945c9274b6bSCho, Yu-Chen /* Describe the layout of each field in each format. */
946c9274b6bSCho, Yu-Chen typedef struct DisasField {
947c9274b6bSCho, Yu-Chen unsigned int beg:8;
948c9274b6bSCho, Yu-Chen unsigned int size:8;
949c9274b6bSCho, Yu-Chen unsigned int type:2;
950c9274b6bSCho, Yu-Chen unsigned int indexC:6;
951c9274b6bSCho, Yu-Chen enum DisasFieldIndexO indexO:8;
952c9274b6bSCho, Yu-Chen } DisasField;
953c9274b6bSCho, Yu-Chen
954c9274b6bSCho, Yu-Chen typedef struct DisasFormatInfo {
955c9274b6bSCho, Yu-Chen DisasField op[NUM_C_FIELD];
956c9274b6bSCho, Yu-Chen } DisasFormatInfo;
957c9274b6bSCho, Yu-Chen
958c9274b6bSCho, Yu-Chen #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
959c9274b6bSCho, Yu-Chen #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
960c9274b6bSCho, Yu-Chen #define V(N, B) { B, 4, 3, FLD_C_v##N, FLD_O_v##N }
961c9274b6bSCho, Yu-Chen #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
962c9274b6bSCho, Yu-Chen { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
963c9274b6bSCho, Yu-Chen #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
964c9274b6bSCho, Yu-Chen { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
965c9274b6bSCho, Yu-Chen { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
966c9274b6bSCho, Yu-Chen #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
967c9274b6bSCho, Yu-Chen { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
968c9274b6bSCho, Yu-Chen #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
969c9274b6bSCho, Yu-Chen { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
970c9274b6bSCho, Yu-Chen { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
971c9274b6bSCho, Yu-Chen #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
972c9274b6bSCho, Yu-Chen #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
973c9274b6bSCho, Yu-Chen
974c9274b6bSCho, Yu-Chen #define F0(N) { { } },
975c9274b6bSCho, Yu-Chen #define F1(N, X1) { { X1 } },
976c9274b6bSCho, Yu-Chen #define F2(N, X1, X2) { { X1, X2 } },
977c9274b6bSCho, Yu-Chen #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
978c9274b6bSCho, Yu-Chen #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
979c9274b6bSCho, Yu-Chen #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
980c9274b6bSCho, Yu-Chen #define F6(N, X1, X2, X3, X4, X5, X6) { { X1, X2, X3, X4, X5, X6 } },
981c9274b6bSCho, Yu-Chen
982c9274b6bSCho, Yu-Chen static const DisasFormatInfo format_info[] = {
9839cef8d99SPhilippe Mathieu-Daudé #include "insn-format.h.inc"
984c9274b6bSCho, Yu-Chen };
985c9274b6bSCho, Yu-Chen
986c9274b6bSCho, Yu-Chen #undef F0
987c9274b6bSCho, Yu-Chen #undef F1
988c9274b6bSCho, Yu-Chen #undef F2
989c9274b6bSCho, Yu-Chen #undef F3
990c9274b6bSCho, Yu-Chen #undef F4
991c9274b6bSCho, Yu-Chen #undef F5
992c9274b6bSCho, Yu-Chen #undef F6
993c9274b6bSCho, Yu-Chen #undef R
994c9274b6bSCho, Yu-Chen #undef M
995c9274b6bSCho, Yu-Chen #undef V
996c9274b6bSCho, Yu-Chen #undef BD
997c9274b6bSCho, Yu-Chen #undef BXD
998c9274b6bSCho, Yu-Chen #undef BDL
999c9274b6bSCho, Yu-Chen #undef BXDL
1000c9274b6bSCho, Yu-Chen #undef I
1001c9274b6bSCho, Yu-Chen #undef L
1002c9274b6bSCho, Yu-Chen
1003c9274b6bSCho, Yu-Chen /* Generally, we'll extract operands into this structures, operate upon
1004c9274b6bSCho, Yu-Chen them, and store them back. See the "in1", "in2", "prep", "wout" sets
1005c9274b6bSCho, Yu-Chen of routines below for more details. */
1006c9274b6bSCho, Yu-Chen typedef struct {
1007c9274b6bSCho, Yu-Chen TCGv_i64 out, out2, in1, in2;
1008c9274b6bSCho, Yu-Chen TCGv_i64 addr1;
10092b91240fSRichard Henderson TCGv_i128 out_128, in1_128, in2_128;
1010c9274b6bSCho, Yu-Chen } DisasOps;
1011c9274b6bSCho, Yu-Chen
1012c9274b6bSCho, Yu-Chen /* Instructions can place constraints on their operands, raising specification
1013c9274b6bSCho, Yu-Chen exceptions if they are violated. To make this easy to automate, each "in1",
1014c9274b6bSCho, Yu-Chen "in2", "prep", "wout" helper will have a SPEC_<name> define that equals one
1015c9274b6bSCho, Yu-Chen of the following, or 0. To make this easy to document, we'll put the
1016c9274b6bSCho, Yu-Chen SPEC_<name> defines next to <name>. */
1017c9274b6bSCho, Yu-Chen
1018c9274b6bSCho, Yu-Chen #define SPEC_r1_even 1
1019c9274b6bSCho, Yu-Chen #define SPEC_r2_even 2
1020c9274b6bSCho, Yu-Chen #define SPEC_r3_even 4
1021c9274b6bSCho, Yu-Chen #define SPEC_r1_f128 8
1022c9274b6bSCho, Yu-Chen #define SPEC_r2_f128 16
1023c9274b6bSCho, Yu-Chen
1024c9274b6bSCho, Yu-Chen /* Return values from translate_one, indicating the state of the TB. */
1025c9274b6bSCho, Yu-Chen
1026c9274b6bSCho, Yu-Chen /* We are not using a goto_tb (for whatever reason), but have updated
1027c9274b6bSCho, Yu-Chen the PC (for whatever reason), so there's no need to do it again on
1028c9274b6bSCho, Yu-Chen exiting the TB. */
1029c9274b6bSCho, Yu-Chen #define DISAS_PC_UPDATED DISAS_TARGET_0
1030c9274b6bSCho, Yu-Chen
1031c9274b6bSCho, Yu-Chen /* We have updated the PC and CC values. */
1032c9274b6bSCho, Yu-Chen #define DISAS_PC_CC_UPDATED DISAS_TARGET_2
1033c9274b6bSCho, Yu-Chen
1034c9274b6bSCho, Yu-Chen
1035c9274b6bSCho, Yu-Chen /* Instruction flags */
1036c9274b6bSCho, Yu-Chen #define IF_AFP1 0x0001 /* r1 is a fp reg for HFP/FPS instructions */
1037c9274b6bSCho, Yu-Chen #define IF_AFP2 0x0002 /* r2 is a fp reg for HFP/FPS instructions */
1038c9274b6bSCho, Yu-Chen #define IF_AFP3 0x0004 /* r3 is a fp reg for HFP/FPS instructions */
1039c9274b6bSCho, Yu-Chen #define IF_BFP 0x0008 /* binary floating point instruction */
1040c9274b6bSCho, Yu-Chen #define IF_DFP 0x0010 /* decimal floating point instruction */
1041c9274b6bSCho, Yu-Chen #define IF_PRIV 0x0020 /* privileged instruction */
1042c9274b6bSCho, Yu-Chen #define IF_VEC 0x0040 /* vector instruction */
1043c9274b6bSCho, Yu-Chen #define IF_IO 0x0080 /* input/output instruction */
1044c9274b6bSCho, Yu-Chen
1045c9274b6bSCho, Yu-Chen struct DisasInsn {
1046c9274b6bSCho, Yu-Chen unsigned opc:16;
1047c9274b6bSCho, Yu-Chen unsigned flags:16;
1048c9274b6bSCho, Yu-Chen DisasFormat fmt:8;
1049c9274b6bSCho, Yu-Chen unsigned fac:8;
1050c9274b6bSCho, Yu-Chen unsigned spec:8;
1051c9274b6bSCho, Yu-Chen
1052c9274b6bSCho, Yu-Chen const char *name;
1053c9274b6bSCho, Yu-Chen
1054c9274b6bSCho, Yu-Chen /* Pre-process arguments before HELP_OP. */
1055c9274b6bSCho, Yu-Chen void (*help_in1)(DisasContext *, DisasOps *);
1056c9274b6bSCho, Yu-Chen void (*help_in2)(DisasContext *, DisasOps *);
1057c9274b6bSCho, Yu-Chen void (*help_prep)(DisasContext *, DisasOps *);
1058c9274b6bSCho, Yu-Chen
1059c9274b6bSCho, Yu-Chen /*
1060c9274b6bSCho, Yu-Chen * Post-process output after HELP_OP.
1061c9274b6bSCho, Yu-Chen * Note that these are not called if HELP_OP returns DISAS_NORETURN.
1062c9274b6bSCho, Yu-Chen */
1063c9274b6bSCho, Yu-Chen void (*help_wout)(DisasContext *, DisasOps *);
1064c9274b6bSCho, Yu-Chen void (*help_cout)(DisasContext *, DisasOps *);
1065c9274b6bSCho, Yu-Chen
1066c9274b6bSCho, Yu-Chen /* Implement the operation itself. */
1067c9274b6bSCho, Yu-Chen DisasJumpType (*help_op)(DisasContext *, DisasOps *);
1068c9274b6bSCho, Yu-Chen
1069c9274b6bSCho, Yu-Chen uint64_t data;
1070c9274b6bSCho, Yu-Chen };
1071c9274b6bSCho, Yu-Chen
1072c9274b6bSCho, Yu-Chen /* ====================================================================== */
1073c9274b6bSCho, Yu-Chen /* Miscellaneous helpers, used by several operations. */
1074c9274b6bSCho, Yu-Chen
help_goto_direct(DisasContext * s,uint64_t dest)1075c9274b6bSCho, Yu-Chen static DisasJumpType help_goto_direct(DisasContext *s, uint64_t dest)
1076c9274b6bSCho, Yu-Chen {
107753313396SRichard Henderson update_cc_op(s);
1078619f6891SRichard Henderson per_breaking_event(s);
107953313396SRichard Henderson per_branch(s, tcg_constant_i64(dest));
108053313396SRichard Henderson
1081c9274b6bSCho, Yu-Chen if (dest == s->pc_tmp) {
1082c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1083c9274b6bSCho, Yu-Chen }
1084c9274b6bSCho, Yu-Chen if (use_goto_tb(s, dest)) {
1085c9274b6bSCho, Yu-Chen tcg_gen_goto_tb(0);
1086c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(psw_addr, dest);
1087c9274b6bSCho, Yu-Chen tcg_gen_exit_tb(s->base.tb, 0);
1088b67b6c7cSRichard Henderson return DISAS_NORETURN;
1089c9274b6bSCho, Yu-Chen } else {
1090c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(psw_addr, dest);
109153313396SRichard Henderson return DISAS_PC_CC_UPDATED;
1092c9274b6bSCho, Yu-Chen }
1093c9274b6bSCho, Yu-Chen }
1094c9274b6bSCho, Yu-Chen
help_goto_indirect(DisasContext * s,TCGv_i64 dest)10959bbbcf5dSRichard Henderson static DisasJumpType help_goto_indirect(DisasContext *s, TCGv_i64 dest)
10969bbbcf5dSRichard Henderson {
109753313396SRichard Henderson update_cc_op(s);
1098619f6891SRichard Henderson per_breaking_event(s);
10999bbbcf5dSRichard Henderson tcg_gen_mov_i64(psw_addr, dest);
110053313396SRichard Henderson per_branch(s, psw_addr);
110153313396SRichard Henderson return DISAS_PC_CC_UPDATED;
11029bbbcf5dSRichard Henderson }
11039bbbcf5dSRichard Henderson
help_branch(DisasContext * s,DisasCompare * c,bool is_imm,int imm,TCGv_i64 cdest)1104c9274b6bSCho, Yu-Chen static DisasJumpType help_branch(DisasContext *s, DisasCompare *c,
1105c9274b6bSCho, Yu-Chen bool is_imm, int imm, TCGv_i64 cdest)
1106c9274b6bSCho, Yu-Chen {
110716ed5f14SIlya Leoshkevich uint64_t dest = s->base.pc_next + (int64_t)imm * 2;
110853313396SRichard Henderson TCGLabel *lab;
1109c9274b6bSCho, Yu-Chen
1110c9274b6bSCho, Yu-Chen /* Take care of the special cases first. */
1111c9274b6bSCho, Yu-Chen if (c->cond == TCG_COND_NEVER) {
1112e6405455SRichard Henderson return DISAS_NEXT;
1113c9274b6bSCho, Yu-Chen }
1114c9274b6bSCho, Yu-Chen if (is_imm) {
1115a90e3195SRichard Henderson /*
1116a90e3195SRichard Henderson * Do not optimize a conditional branch if PER enabled, because we
1117a90e3195SRichard Henderson * still need a conditional call to helper_per_branch.
1118a90e3195SRichard Henderson */
1119a90e3195SRichard Henderson if (c->cond == TCG_COND_ALWAYS
1120a90e3195SRichard Henderson || (dest == s->pc_tmp &&
1121a90e3195SRichard Henderson !(s->base.tb->flags & FLAG_MASK_PER_BRANCH))) {
1122e6405455SRichard Henderson return help_goto_direct(s, dest);
1123c9274b6bSCho, Yu-Chen }
1124c9274b6bSCho, Yu-Chen } else {
1125c9274b6bSCho, Yu-Chen if (!cdest) {
1126c9274b6bSCho, Yu-Chen /* E.g. bcr %r0 -> no branch. */
1127e6405455SRichard Henderson return DISAS_NEXT;
1128c9274b6bSCho, Yu-Chen }
1129c9274b6bSCho, Yu-Chen if (c->cond == TCG_COND_ALWAYS) {
1130e6405455SRichard Henderson return help_goto_indirect(s, cdest);
1131c9274b6bSCho, Yu-Chen }
1132c9274b6bSCho, Yu-Chen }
1133c9274b6bSCho, Yu-Chen
1134c9274b6bSCho, Yu-Chen update_cc_op(s);
1135c9274b6bSCho, Yu-Chen
1136e6405455SRichard Henderson /*
1137e6405455SRichard Henderson * Ensure the taken branch is fall-through of the tcg branch.
1138e6405455SRichard Henderson * This keeps @cdest usage within the extended basic block,
1139e6405455SRichard Henderson * which avoids an otherwise unnecessary spill to the stack.
1140e6405455SRichard Henderson */
1141c9274b6bSCho, Yu-Chen lab = gen_new_label();
1142e6405455SRichard Henderson if (c->is_64) {
1143e6405455SRichard Henderson tcg_gen_brcond_i64(tcg_invert_cond(c->cond),
1144e6405455SRichard Henderson c->u.s64.a, c->u.s64.b, lab);
1145e6405455SRichard Henderson } else {
1146e6405455SRichard Henderson tcg_gen_brcond_i32(tcg_invert_cond(c->cond),
1147e6405455SRichard Henderson c->u.s32.a, c->u.s32.b, lab);
1148e6405455SRichard Henderson }
1149c9274b6bSCho, Yu-Chen
1150c9274b6bSCho, Yu-Chen /* Branch taken. */
1151619f6891SRichard Henderson per_breaking_event(s);
1152e6405455SRichard Henderson if (is_imm) {
1153c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(psw_addr, dest);
1154c9274b6bSCho, Yu-Chen } else {
1155c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(psw_addr, cdest);
1156c9274b6bSCho, Yu-Chen }
115753313396SRichard Henderson per_branch(s, psw_addr);
1158c9274b6bSCho, Yu-Chen
1159e6405455SRichard Henderson if (is_imm && use_goto_tb(s, dest)) {
1160c9274b6bSCho, Yu-Chen tcg_gen_goto_tb(0);
1161c9274b6bSCho, Yu-Chen tcg_gen_exit_tb(s->base.tb, 0);
1162e6405455SRichard Henderson } else {
1163e6405455SRichard Henderson tcg_gen_lookup_and_goto_ptr();
1164e6405455SRichard Henderson }
1165c9274b6bSCho, Yu-Chen
1166c9274b6bSCho, Yu-Chen gen_set_label(lab);
1167c9274b6bSCho, Yu-Chen
1168e6405455SRichard Henderson /* Branch not taken. */
1169e6405455SRichard Henderson tcg_gen_movi_i64(psw_addr, s->pc_tmp);
1170e6405455SRichard Henderson if (use_goto_tb(s, s->pc_tmp)) {
1171e6405455SRichard Henderson tcg_gen_goto_tb(1);
1172e6405455SRichard Henderson tcg_gen_exit_tb(s->base.tb, 1);
1173e6405455SRichard Henderson return DISAS_NORETURN;
1174c9274b6bSCho, Yu-Chen }
117553313396SRichard Henderson return DISAS_PC_CC_UPDATED;
117653313396SRichard Henderson }
1177c9274b6bSCho, Yu-Chen
1178c9274b6bSCho, Yu-Chen /* ====================================================================== */
1179c9274b6bSCho, Yu-Chen /* The operations. These perform the bulk of the work for any insn,
1180c9274b6bSCho, Yu-Chen usually after the operands have been loaded and output initialized. */
1181c9274b6bSCho, Yu-Chen
op_abs(DisasContext * s,DisasOps * o)1182c9274b6bSCho, Yu-Chen static DisasJumpType op_abs(DisasContext *s, DisasOps *o)
1183c9274b6bSCho, Yu-Chen {
1184c9274b6bSCho, Yu-Chen tcg_gen_abs_i64(o->out, o->in2);
1185c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1186c9274b6bSCho, Yu-Chen }
1187c9274b6bSCho, Yu-Chen
op_absf32(DisasContext * s,DisasOps * o)1188c9274b6bSCho, Yu-Chen static DisasJumpType op_absf32(DisasContext *s, DisasOps *o)
1189c9274b6bSCho, Yu-Chen {
1190c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffull);
1191c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1192c9274b6bSCho, Yu-Chen }
1193c9274b6bSCho, Yu-Chen
op_absf64(DisasContext * s,DisasOps * o)1194c9274b6bSCho, Yu-Chen static DisasJumpType op_absf64(DisasContext *s, DisasOps *o)
1195c9274b6bSCho, Yu-Chen {
1196c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
1197c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1198c9274b6bSCho, Yu-Chen }
1199c9274b6bSCho, Yu-Chen
op_absf128(DisasContext * s,DisasOps * o)1200c9274b6bSCho, Yu-Chen static DisasJumpType op_absf128(DisasContext *s, DisasOps *o)
1201c9274b6bSCho, Yu-Chen {
1202c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in1, 0x7fffffffffffffffull);
1203c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(o->out2, o->in2);
1204c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1205c9274b6bSCho, Yu-Chen }
1206c9274b6bSCho, Yu-Chen
op_add(DisasContext * s,DisasOps * o)1207c9274b6bSCho, Yu-Chen static DisasJumpType op_add(DisasContext *s, DisasOps *o)
1208c9274b6bSCho, Yu-Chen {
1209c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->out, o->in1, o->in2);
1210c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1211c9274b6bSCho, Yu-Chen }
1212c9274b6bSCho, Yu-Chen
op_addu64(DisasContext * s,DisasOps * o)1213c9274b6bSCho, Yu-Chen static DisasJumpType op_addu64(DisasContext *s, DisasOps *o)
1214c9274b6bSCho, Yu-Chen {
1215c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(cc_src, 0);
1216c9274b6bSCho, Yu-Chen tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);
1217c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1218c9274b6bSCho, Yu-Chen }
1219c9274b6bSCho, Yu-Chen
1220c9274b6bSCho, Yu-Chen /* Compute carry into cc_src. */
compute_carry(DisasContext * s)1221c9274b6bSCho, Yu-Chen static void compute_carry(DisasContext *s)
1222c9274b6bSCho, Yu-Chen {
1223c9274b6bSCho, Yu-Chen switch (s->cc_op) {
1224c9274b6bSCho, Yu-Chen case CC_OP_ADDU:
1225c9274b6bSCho, Yu-Chen /* The carry value is already in cc_src (1,0). */
1226c9274b6bSCho, Yu-Chen break;
1227c9274b6bSCho, Yu-Chen case CC_OP_SUBU:
1228c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(cc_src, cc_src, 1);
1229c9274b6bSCho, Yu-Chen break;
1230c9274b6bSCho, Yu-Chen default:
1231c9274b6bSCho, Yu-Chen gen_op_calc_cc(s);
1232c9274b6bSCho, Yu-Chen /* fall through */
1233c9274b6bSCho, Yu-Chen case CC_OP_STATIC:
1234c9274b6bSCho, Yu-Chen /* The carry flag is the msb of CC; compute into cc_src. */
1235c9274b6bSCho, Yu-Chen tcg_gen_extu_i32_i64(cc_src, cc_op);
1236c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(cc_src, cc_src, 1);
1237c9274b6bSCho, Yu-Chen break;
1238c9274b6bSCho, Yu-Chen }
1239c9274b6bSCho, Yu-Chen }
1240c9274b6bSCho, Yu-Chen
op_addc32(DisasContext * s,DisasOps * o)1241c9274b6bSCho, Yu-Chen static DisasJumpType op_addc32(DisasContext *s, DisasOps *o)
1242c9274b6bSCho, Yu-Chen {
1243c9274b6bSCho, Yu-Chen compute_carry(s);
1244c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->out, o->in1, o->in2);
1245c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->out, o->out, cc_src);
1246c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1247c9274b6bSCho, Yu-Chen }
1248c9274b6bSCho, Yu-Chen
op_addc64(DisasContext * s,DisasOps * o)1249c9274b6bSCho, Yu-Chen static DisasJumpType op_addc64(DisasContext *s, DisasOps *o)
1250c9274b6bSCho, Yu-Chen {
1251c9274b6bSCho, Yu-Chen compute_carry(s);
1252c9274b6bSCho, Yu-Chen
1253f1ea739bSRichard Henderson TCGv_i64 zero = tcg_constant_i64(0);
1254c9274b6bSCho, Yu-Chen tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero);
1255c9274b6bSCho, Yu-Chen tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero);
1256c9274b6bSCho, Yu-Chen
1257c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1258c9274b6bSCho, Yu-Chen }
1259c9274b6bSCho, Yu-Chen
op_asi(DisasContext * s,DisasOps * o)1260c9274b6bSCho, Yu-Chen static DisasJumpType op_asi(DisasContext *s, DisasOps *o)
1261c9274b6bSCho, Yu-Chen {
1262c9274b6bSCho, Yu-Chen bool non_atomic = !s390_has_feat(S390_FEAT_STFLE_45);
1263c9274b6bSCho, Yu-Chen
1264c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
1265c9274b6bSCho, Yu-Chen if (non_atomic) {
1266c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
1267c9274b6bSCho, Yu-Chen } else {
1268c9274b6bSCho, Yu-Chen /* Perform the atomic addition in memory. */
1269c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
1270c9274b6bSCho, Yu-Chen s->insn->data);
1271c9274b6bSCho, Yu-Chen }
1272c9274b6bSCho, Yu-Chen
1273c9274b6bSCho, Yu-Chen /* Recompute also for atomic case: needed for setting CC. */
1274c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->out, o->in1, o->in2);
1275c9274b6bSCho, Yu-Chen
1276c9274b6bSCho, Yu-Chen if (non_atomic) {
1277c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
1278c9274b6bSCho, Yu-Chen }
1279c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1280c9274b6bSCho, Yu-Chen }
1281c9274b6bSCho, Yu-Chen
op_asiu64(DisasContext * s,DisasOps * o)1282c9274b6bSCho, Yu-Chen static DisasJumpType op_asiu64(DisasContext *s, DisasOps *o)
1283c9274b6bSCho, Yu-Chen {
1284c9274b6bSCho, Yu-Chen bool non_atomic = !s390_has_feat(S390_FEAT_STFLE_45);
1285c9274b6bSCho, Yu-Chen
1286c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
1287c9274b6bSCho, Yu-Chen if (non_atomic) {
1288c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
1289c9274b6bSCho, Yu-Chen } else {
1290c9274b6bSCho, Yu-Chen /* Perform the atomic addition in memory. */
1291c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_add_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
1292c9274b6bSCho, Yu-Chen s->insn->data);
1293c9274b6bSCho, Yu-Chen }
1294c9274b6bSCho, Yu-Chen
1295c9274b6bSCho, Yu-Chen /* Recompute also for atomic case: needed for setting CC. */
1296c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(cc_src, 0);
1297c9274b6bSCho, Yu-Chen tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);
1298c9274b6bSCho, Yu-Chen
1299c9274b6bSCho, Yu-Chen if (non_atomic) {
1300c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
1301c9274b6bSCho, Yu-Chen }
1302c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1303c9274b6bSCho, Yu-Chen }
1304c9274b6bSCho, Yu-Chen
op_aeb(DisasContext * s,DisasOps * o)1305c9274b6bSCho, Yu-Chen static DisasJumpType op_aeb(DisasContext *s, DisasOps *o)
1306c9274b6bSCho, Yu-Chen {
1307ad75a51eSRichard Henderson gen_helper_aeb(o->out, tcg_env, o->in1, o->in2);
1308c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1309c9274b6bSCho, Yu-Chen }
1310c9274b6bSCho, Yu-Chen
op_adb(DisasContext * s,DisasOps * o)1311c9274b6bSCho, Yu-Chen static DisasJumpType op_adb(DisasContext *s, DisasOps *o)
1312c9274b6bSCho, Yu-Chen {
1313ad75a51eSRichard Henderson gen_helper_adb(o->out, tcg_env, o->in1, o->in2);
1314c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1315c9274b6bSCho, Yu-Chen }
1316c9274b6bSCho, Yu-Chen
op_axb(DisasContext * s,DisasOps * o)1317c9274b6bSCho, Yu-Chen static DisasJumpType op_axb(DisasContext *s, DisasOps *o)
1318c9274b6bSCho, Yu-Chen {
1319ad75a51eSRichard Henderson gen_helper_axb(o->out_128, tcg_env, o->in1_128, o->in2_128);
1320c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1321c9274b6bSCho, Yu-Chen }
1322c9274b6bSCho, Yu-Chen
op_and(DisasContext * s,DisasOps * o)1323c9274b6bSCho, Yu-Chen static DisasJumpType op_and(DisasContext *s, DisasOps *o)
1324c9274b6bSCho, Yu-Chen {
1325c9274b6bSCho, Yu-Chen tcg_gen_and_i64(o->out, o->in1, o->in2);
1326c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1327c9274b6bSCho, Yu-Chen }
1328c9274b6bSCho, Yu-Chen
op_andi(DisasContext * s,DisasOps * o)1329c9274b6bSCho, Yu-Chen static DisasJumpType op_andi(DisasContext *s, DisasOps *o)
1330c9274b6bSCho, Yu-Chen {
1331c9274b6bSCho, Yu-Chen int shift = s->insn->data & 0xff;
1332c9274b6bSCho, Yu-Chen int size = s->insn->data >> 8;
1333c9274b6bSCho, Yu-Chen uint64_t mask = ((1ull << size) - 1) << shift;
1334ab9984bdSRichard Henderson TCGv_i64 t = tcg_temp_new_i64();
1335c9274b6bSCho, Yu-Chen
1336ab9984bdSRichard Henderson tcg_gen_shli_i64(t, o->in2, shift);
1337ab9984bdSRichard Henderson tcg_gen_ori_i64(t, t, ~mask);
1338ab9984bdSRichard Henderson tcg_gen_and_i64(o->out, o->in1, t);
1339c9274b6bSCho, Yu-Chen
1340c9274b6bSCho, Yu-Chen /* Produce the CC from only the bits manipulated. */
1341c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(cc_dst, o->out, mask);
1342c9274b6bSCho, Yu-Chen set_cc_nz_u64(s, cc_dst);
1343c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1344c9274b6bSCho, Yu-Chen }
1345c9274b6bSCho, Yu-Chen
op_andc(DisasContext * s,DisasOps * o)1346ea0a1053SDavid Miller static DisasJumpType op_andc(DisasContext *s, DisasOps *o)
1347ea0a1053SDavid Miller {
1348ea0a1053SDavid Miller tcg_gen_andc_i64(o->out, o->in1, o->in2);
1349ea0a1053SDavid Miller return DISAS_NEXT;
1350ea0a1053SDavid Miller }
1351ea0a1053SDavid Miller
op_orc(DisasContext * s,DisasOps * o)1352ea0a1053SDavid Miller static DisasJumpType op_orc(DisasContext *s, DisasOps *o)
1353ea0a1053SDavid Miller {
1354ea0a1053SDavid Miller tcg_gen_orc_i64(o->out, o->in1, o->in2);
1355ea0a1053SDavid Miller return DISAS_NEXT;
1356ea0a1053SDavid Miller }
1357ea0a1053SDavid Miller
op_nand(DisasContext * s,DisasOps * o)1358ea0a1053SDavid Miller static DisasJumpType op_nand(DisasContext *s, DisasOps *o)
1359ea0a1053SDavid Miller {
1360ea0a1053SDavid Miller tcg_gen_nand_i64(o->out, o->in1, o->in2);
1361ea0a1053SDavid Miller return DISAS_NEXT;
1362ea0a1053SDavid Miller }
1363ea0a1053SDavid Miller
op_nor(DisasContext * s,DisasOps * o)1364ea0a1053SDavid Miller static DisasJumpType op_nor(DisasContext *s, DisasOps *o)
1365ea0a1053SDavid Miller {
1366ea0a1053SDavid Miller tcg_gen_nor_i64(o->out, o->in1, o->in2);
1367ea0a1053SDavid Miller return DISAS_NEXT;
1368ea0a1053SDavid Miller }
1369ea0a1053SDavid Miller
op_nxor(DisasContext * s,DisasOps * o)1370ea0a1053SDavid Miller static DisasJumpType op_nxor(DisasContext *s, DisasOps *o)
1371ea0a1053SDavid Miller {
1372ea0a1053SDavid Miller tcg_gen_eqv_i64(o->out, o->in1, o->in2);
1373ea0a1053SDavid Miller return DISAS_NEXT;
1374ea0a1053SDavid Miller }
1375ea0a1053SDavid Miller
op_ni(DisasContext * s,DisasOps * o)1376c9274b6bSCho, Yu-Chen static DisasJumpType op_ni(DisasContext *s, DisasOps *o)
1377c9274b6bSCho, Yu-Chen {
1378c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
1379c9274b6bSCho, Yu-Chen
1380c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
1381c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
1382c9274b6bSCho, Yu-Chen } else {
1383c9274b6bSCho, Yu-Chen /* Perform the atomic operation in memory. */
1384c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_and_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
1385c9274b6bSCho, Yu-Chen s->insn->data);
1386c9274b6bSCho, Yu-Chen }
1387c9274b6bSCho, Yu-Chen
1388c9274b6bSCho, Yu-Chen /* Recompute also for atomic case: needed for setting CC. */
1389c9274b6bSCho, Yu-Chen tcg_gen_and_i64(o->out, o->in1, o->in2);
1390c9274b6bSCho, Yu-Chen
1391c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
1392c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
1393c9274b6bSCho, Yu-Chen }
1394c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1395c9274b6bSCho, Yu-Chen }
1396c9274b6bSCho, Yu-Chen
op_bas(DisasContext * s,DisasOps * o)1397c9274b6bSCho, Yu-Chen static DisasJumpType op_bas(DisasContext *s, DisasOps *o)
1398c9274b6bSCho, Yu-Chen {
1399c9274b6bSCho, Yu-Chen pc_to_link_info(o->out, s, s->pc_tmp);
1400c9274b6bSCho, Yu-Chen if (o->in2) {
14019bbbcf5dSRichard Henderson return help_goto_indirect(s, o->in2);
1402c9274b6bSCho, Yu-Chen } else {
1403c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1404c9274b6bSCho, Yu-Chen }
1405c9274b6bSCho, Yu-Chen }
1406c9274b6bSCho, Yu-Chen
save_link_info(DisasContext * s,DisasOps * o)1407c9274b6bSCho, Yu-Chen static void save_link_info(DisasContext *s, DisasOps *o)
1408c9274b6bSCho, Yu-Chen {
1409c9274b6bSCho, Yu-Chen TCGv_i64 t;
1410c9274b6bSCho, Yu-Chen
1411c9274b6bSCho, Yu-Chen if (s->base.tb->flags & (FLAG_MASK_32 | FLAG_MASK_64)) {
1412c9274b6bSCho, Yu-Chen pc_to_link_info(o->out, s, s->pc_tmp);
1413c9274b6bSCho, Yu-Chen return;
1414c9274b6bSCho, Yu-Chen }
1415c9274b6bSCho, Yu-Chen gen_op_calc_cc(s);
1416c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull);
1417c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp);
1418c9274b6bSCho, Yu-Chen t = tcg_temp_new_i64();
1419c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(t, psw_mask, 16);
1420c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(t, t, 0x0f000000);
1421c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->out, t);
1422c9274b6bSCho, Yu-Chen tcg_gen_extu_i32_i64(t, cc_op);
1423c9274b6bSCho, Yu-Chen tcg_gen_shli_i64(t, t, 28);
1424c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->out, t);
1425c9274b6bSCho, Yu-Chen }
1426c9274b6bSCho, Yu-Chen
op_bal(DisasContext * s,DisasOps * o)1427c9274b6bSCho, Yu-Chen static DisasJumpType op_bal(DisasContext *s, DisasOps *o)
1428c9274b6bSCho, Yu-Chen {
1429c9274b6bSCho, Yu-Chen save_link_info(s, o);
1430c9274b6bSCho, Yu-Chen if (o->in2) {
14319bbbcf5dSRichard Henderson return help_goto_indirect(s, o->in2);
1432c9274b6bSCho, Yu-Chen } else {
1433c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1434c9274b6bSCho, Yu-Chen }
1435c9274b6bSCho, Yu-Chen }
1436c9274b6bSCho, Yu-Chen
1437e8ecdfebSIlya Leoshkevich /*
1438e8ecdfebSIlya Leoshkevich * Disassemble the target of a branch. The results are returned in a form
1439e8ecdfebSIlya Leoshkevich * suitable for passing into help_branch():
1440e8ecdfebSIlya Leoshkevich *
1441e8ecdfebSIlya Leoshkevich * - bool IS_IMM reflects whether the target is fixed or computed. Non-EXECUTEd
1442e8ecdfebSIlya Leoshkevich * branches, whose DisasContext *S contains the relative immediate field RI,
1443e8ecdfebSIlya Leoshkevich * are considered fixed. All the other branches are considered computed.
1444e8ecdfebSIlya Leoshkevich * - int IMM is the value of RI.
1445e8ecdfebSIlya Leoshkevich * - TCGv_i64 CDEST is the address of the computed target.
1446e8ecdfebSIlya Leoshkevich */
1447e8ecdfebSIlya Leoshkevich #define disas_jdest(s, ri, is_imm, imm, cdest) do { \
1448e8ecdfebSIlya Leoshkevich if (have_field(s, ri)) { \
1449e8ecdfebSIlya Leoshkevich if (unlikely(s->ex_value)) { \
1450e8ecdfebSIlya Leoshkevich cdest = tcg_temp_new_i64(); \
1451ad75a51eSRichard Henderson tcg_gen_ld_i64(cdest, tcg_env, offsetof(CPUS390XState, ex_target));\
1452e8ecdfebSIlya Leoshkevich tcg_gen_addi_i64(cdest, cdest, (int64_t)get_field(s, ri) * 2); \
1453e8ecdfebSIlya Leoshkevich is_imm = false; \
1454e8ecdfebSIlya Leoshkevich } else { \
1455e8ecdfebSIlya Leoshkevich is_imm = true; \
1456e8ecdfebSIlya Leoshkevich } \
1457e8ecdfebSIlya Leoshkevich } else { \
1458e8ecdfebSIlya Leoshkevich is_imm = false; \
1459e8ecdfebSIlya Leoshkevich } \
1460e8ecdfebSIlya Leoshkevich imm = is_imm ? get_field(s, ri) : 0; \
1461e8ecdfebSIlya Leoshkevich } while (false)
1462e8ecdfebSIlya Leoshkevich
op_basi(DisasContext * s,DisasOps * o)1463c9274b6bSCho, Yu-Chen static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
1464c9274b6bSCho, Yu-Chen {
1465e8ecdfebSIlya Leoshkevich DisasCompare c;
1466e8ecdfebSIlya Leoshkevich bool is_imm;
1467e8ecdfebSIlya Leoshkevich int imm;
1468e8ecdfebSIlya Leoshkevich
1469c9274b6bSCho, Yu-Chen pc_to_link_info(o->out, s, s->pc_tmp);
1470e8ecdfebSIlya Leoshkevich
1471e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, o->in2);
1472e8ecdfebSIlya Leoshkevich disas_jcc(s, &c, 0xf);
1473e8ecdfebSIlya Leoshkevich return help_branch(s, &c, is_imm, imm, o->in2);
1474c9274b6bSCho, Yu-Chen }
1475c9274b6bSCho, Yu-Chen
op_bc(DisasContext * s,DisasOps * o)1476c9274b6bSCho, Yu-Chen static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
1477c9274b6bSCho, Yu-Chen {
1478c9274b6bSCho, Yu-Chen int m1 = get_field(s, m1);
1479c9274b6bSCho, Yu-Chen DisasCompare c;
1480e8ecdfebSIlya Leoshkevich bool is_imm;
1481e8ecdfebSIlya Leoshkevich int imm;
1482c9274b6bSCho, Yu-Chen
1483c9274b6bSCho, Yu-Chen /* BCR with R2 = 0 causes no branching */
1484c9274b6bSCho, Yu-Chen if (have_field(s, r2) && get_field(s, r2) == 0) {
1485c9274b6bSCho, Yu-Chen if (m1 == 14) {
1486c9274b6bSCho, Yu-Chen /* Perform serialization */
1487c9274b6bSCho, Yu-Chen /* FIXME: check for fast-BCR-serialization facility */
1488c9274b6bSCho, Yu-Chen tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
1489c9274b6bSCho, Yu-Chen }
1490c9274b6bSCho, Yu-Chen if (m1 == 15) {
1491c9274b6bSCho, Yu-Chen /* Perform serialization */
1492c9274b6bSCho, Yu-Chen /* FIXME: perform checkpoint-synchronisation */
1493c9274b6bSCho, Yu-Chen tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
1494c9274b6bSCho, Yu-Chen }
1495c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1496c9274b6bSCho, Yu-Chen }
1497c9274b6bSCho, Yu-Chen
1498e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, o->in2);
1499c9274b6bSCho, Yu-Chen disas_jcc(s, &c, m1);
1500c9274b6bSCho, Yu-Chen return help_branch(s, &c, is_imm, imm, o->in2);
1501c9274b6bSCho, Yu-Chen }
1502c9274b6bSCho, Yu-Chen
op_bct32(DisasContext * s,DisasOps * o)1503c9274b6bSCho, Yu-Chen static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
1504c9274b6bSCho, Yu-Chen {
1505c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1506c9274b6bSCho, Yu-Chen DisasCompare c;
1507e8ecdfebSIlya Leoshkevich bool is_imm;
1508c9274b6bSCho, Yu-Chen TCGv_i64 t;
1509e8ecdfebSIlya Leoshkevich int imm;
1510c9274b6bSCho, Yu-Chen
1511c9274b6bSCho, Yu-Chen c.cond = TCG_COND_NE;
1512c9274b6bSCho, Yu-Chen c.is_64 = false;
1513c9274b6bSCho, Yu-Chen
1514c9274b6bSCho, Yu-Chen t = tcg_temp_new_i64();
1515c9274b6bSCho, Yu-Chen tcg_gen_subi_i64(t, regs[r1], 1);
1516c9274b6bSCho, Yu-Chen store_reg32_i64(r1, t);
1517c9274b6bSCho, Yu-Chen c.u.s32.a = tcg_temp_new_i32();
1518f5d7b0e2SRichard Henderson c.u.s32.b = tcg_constant_i32(0);
1519c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c.u.s32.a, t);
1520c9274b6bSCho, Yu-Chen
1521e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, o->in2);
1522c9274b6bSCho, Yu-Chen return help_branch(s, &c, is_imm, imm, o->in2);
1523c9274b6bSCho, Yu-Chen }
1524c9274b6bSCho, Yu-Chen
op_bcth(DisasContext * s,DisasOps * o)1525c9274b6bSCho, Yu-Chen static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
1526c9274b6bSCho, Yu-Chen {
1527c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1528c9274b6bSCho, Yu-Chen int imm = get_field(s, i2);
1529c9274b6bSCho, Yu-Chen DisasCompare c;
1530c9274b6bSCho, Yu-Chen TCGv_i64 t;
1531c9274b6bSCho, Yu-Chen
1532c9274b6bSCho, Yu-Chen c.cond = TCG_COND_NE;
1533c9274b6bSCho, Yu-Chen c.is_64 = false;
1534c9274b6bSCho, Yu-Chen
1535c9274b6bSCho, Yu-Chen t = tcg_temp_new_i64();
1536c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(t, regs[r1], 32);
1537c9274b6bSCho, Yu-Chen tcg_gen_subi_i64(t, t, 1);
1538c9274b6bSCho, Yu-Chen store_reg32h_i64(r1, t);
1539c9274b6bSCho, Yu-Chen c.u.s32.a = tcg_temp_new_i32();
1540f5d7b0e2SRichard Henderson c.u.s32.b = tcg_constant_i32(0);
1541c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c.u.s32.a, t);
1542c9274b6bSCho, Yu-Chen
1543c9274b6bSCho, Yu-Chen return help_branch(s, &c, 1, imm, o->in2);
1544c9274b6bSCho, Yu-Chen }
1545c9274b6bSCho, Yu-Chen
op_bct64(DisasContext * s,DisasOps * o)1546c9274b6bSCho, Yu-Chen static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
1547c9274b6bSCho, Yu-Chen {
1548c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1549c9274b6bSCho, Yu-Chen DisasCompare c;
1550e8ecdfebSIlya Leoshkevich bool is_imm;
1551e8ecdfebSIlya Leoshkevich int imm;
1552c9274b6bSCho, Yu-Chen
1553c9274b6bSCho, Yu-Chen c.cond = TCG_COND_NE;
1554c9274b6bSCho, Yu-Chen c.is_64 = true;
1555c9274b6bSCho, Yu-Chen
1556c9274b6bSCho, Yu-Chen tcg_gen_subi_i64(regs[r1], regs[r1], 1);
1557c9274b6bSCho, Yu-Chen c.u.s64.a = regs[r1];
1558f5d7b0e2SRichard Henderson c.u.s64.b = tcg_constant_i64(0);
1559c9274b6bSCho, Yu-Chen
1560e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, o->in2);
1561c9274b6bSCho, Yu-Chen return help_branch(s, &c, is_imm, imm, o->in2);
1562c9274b6bSCho, Yu-Chen }
1563c9274b6bSCho, Yu-Chen
op_bx32(DisasContext * s,DisasOps * o)1564c9274b6bSCho, Yu-Chen static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
1565c9274b6bSCho, Yu-Chen {
1566c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1567c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
1568c9274b6bSCho, Yu-Chen DisasCompare c;
1569e8ecdfebSIlya Leoshkevich bool is_imm;
1570c9274b6bSCho, Yu-Chen TCGv_i64 t;
1571e8ecdfebSIlya Leoshkevich int imm;
1572c9274b6bSCho, Yu-Chen
1573c9274b6bSCho, Yu-Chen c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1574c9274b6bSCho, Yu-Chen c.is_64 = false;
1575c9274b6bSCho, Yu-Chen
1576c9274b6bSCho, Yu-Chen t = tcg_temp_new_i64();
1577c9274b6bSCho, Yu-Chen tcg_gen_add_i64(t, regs[r1], regs[r3]);
1578c9274b6bSCho, Yu-Chen c.u.s32.a = tcg_temp_new_i32();
1579c9274b6bSCho, Yu-Chen c.u.s32.b = tcg_temp_new_i32();
1580c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c.u.s32.a, t);
1581c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(c.u.s32.b, regs[r3 | 1]);
1582c9274b6bSCho, Yu-Chen store_reg32_i64(r1, t);
1583c9274b6bSCho, Yu-Chen
1584e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, o->in2);
1585c9274b6bSCho, Yu-Chen return help_branch(s, &c, is_imm, imm, o->in2);
1586c9274b6bSCho, Yu-Chen }
1587c9274b6bSCho, Yu-Chen
op_bx64(DisasContext * s,DisasOps * o)1588c9274b6bSCho, Yu-Chen static DisasJumpType op_bx64(DisasContext *s, DisasOps *o)
1589c9274b6bSCho, Yu-Chen {
1590c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1591c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
1592c9274b6bSCho, Yu-Chen DisasCompare c;
1593e8ecdfebSIlya Leoshkevich bool is_imm;
1594e8ecdfebSIlya Leoshkevich int imm;
1595c9274b6bSCho, Yu-Chen
1596c9274b6bSCho, Yu-Chen c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
1597c9274b6bSCho, Yu-Chen c.is_64 = true;
1598c9274b6bSCho, Yu-Chen
1599c9274b6bSCho, Yu-Chen if (r1 == (r3 | 1)) {
1600c9274b6bSCho, Yu-Chen c.u.s64.b = load_reg(r3 | 1);
1601c9274b6bSCho, Yu-Chen } else {
1602c9274b6bSCho, Yu-Chen c.u.s64.b = regs[r3 | 1];
1603c9274b6bSCho, Yu-Chen }
1604c9274b6bSCho, Yu-Chen
1605c9274b6bSCho, Yu-Chen tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]);
1606c9274b6bSCho, Yu-Chen c.u.s64.a = regs[r1];
1607c9274b6bSCho, Yu-Chen
1608e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, o->in2);
1609c9274b6bSCho, Yu-Chen return help_branch(s, &c, is_imm, imm, o->in2);
1610c9274b6bSCho, Yu-Chen }
1611c9274b6bSCho, Yu-Chen
op_cj(DisasContext * s,DisasOps * o)1612c9274b6bSCho, Yu-Chen static DisasJumpType op_cj(DisasContext *s, DisasOps *o)
1613c9274b6bSCho, Yu-Chen {
1614c9274b6bSCho, Yu-Chen int imm, m3 = get_field(s, m3);
1615c9274b6bSCho, Yu-Chen bool is_imm;
1616c9274b6bSCho, Yu-Chen DisasCompare c;
1617c9274b6bSCho, Yu-Chen
1618c9274b6bSCho, Yu-Chen c.cond = ltgt_cond[m3];
1619c9274b6bSCho, Yu-Chen if (s->insn->data) {
1620c9274b6bSCho, Yu-Chen c.cond = tcg_unsigned_cond(c.cond);
1621c9274b6bSCho, Yu-Chen }
1622b4dfbbe0SRichard Henderson c.is_64 = true;
1623c9274b6bSCho, Yu-Chen c.u.s64.a = o->in1;
1624c9274b6bSCho, Yu-Chen c.u.s64.b = o->in2;
1625c9274b6bSCho, Yu-Chen
1626e8ecdfebSIlya Leoshkevich o->out = NULL;
1627e8ecdfebSIlya Leoshkevich disas_jdest(s, i4, is_imm, imm, o->out);
1628e8ecdfebSIlya Leoshkevich if (!is_imm && !o->out) {
1629c9274b6bSCho, Yu-Chen imm = 0;
1630c9274b6bSCho, Yu-Chen o->out = get_address(s, 0, get_field(s, b4),
1631c9274b6bSCho, Yu-Chen get_field(s, d4));
1632c9274b6bSCho, Yu-Chen }
1633c9274b6bSCho, Yu-Chen
1634c9274b6bSCho, Yu-Chen return help_branch(s, &c, is_imm, imm, o->out);
1635c9274b6bSCho, Yu-Chen }
1636c9274b6bSCho, Yu-Chen
op_ceb(DisasContext * s,DisasOps * o)1637c9274b6bSCho, Yu-Chen static DisasJumpType op_ceb(DisasContext *s, DisasOps *o)
1638c9274b6bSCho, Yu-Chen {
1639ad75a51eSRichard Henderson gen_helper_ceb(cc_op, tcg_env, o->in1, o->in2);
1640c9274b6bSCho, Yu-Chen set_cc_static(s);
1641c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1642c9274b6bSCho, Yu-Chen }
1643c9274b6bSCho, Yu-Chen
op_cdb(DisasContext * s,DisasOps * o)1644c9274b6bSCho, Yu-Chen static DisasJumpType op_cdb(DisasContext *s, DisasOps *o)
1645c9274b6bSCho, Yu-Chen {
1646ad75a51eSRichard Henderson gen_helper_cdb(cc_op, tcg_env, o->in1, o->in2);
1647c9274b6bSCho, Yu-Chen set_cc_static(s);
1648c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1649c9274b6bSCho, Yu-Chen }
1650c9274b6bSCho, Yu-Chen
op_cxb(DisasContext * s,DisasOps * o)1651c9274b6bSCho, Yu-Chen static DisasJumpType op_cxb(DisasContext *s, DisasOps *o)
1652c9274b6bSCho, Yu-Chen {
1653ad75a51eSRichard Henderson gen_helper_cxb(cc_op, tcg_env, o->in1_128, o->in2_128);
1654c9274b6bSCho, Yu-Chen set_cc_static(s);
1655c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1656c9274b6bSCho, Yu-Chen }
1657c9274b6bSCho, Yu-Chen
fpinst_extract_m34(DisasContext * s,bool m3_with_fpe,bool m4_with_fpe)1658c9274b6bSCho, Yu-Chen static TCGv_i32 fpinst_extract_m34(DisasContext *s, bool m3_with_fpe,
1659c9274b6bSCho, Yu-Chen bool m4_with_fpe)
1660c9274b6bSCho, Yu-Chen {
1661c9274b6bSCho, Yu-Chen const bool fpe = s390_has_feat(S390_FEAT_FLOATING_POINT_EXT);
1662c9274b6bSCho, Yu-Chen uint8_t m3 = get_field(s, m3);
1663c9274b6bSCho, Yu-Chen uint8_t m4 = get_field(s, m4);
1664c9274b6bSCho, Yu-Chen
1665c9274b6bSCho, Yu-Chen /* m3 field was introduced with FPE */
1666c9274b6bSCho, Yu-Chen if (!fpe && m3_with_fpe) {
1667c9274b6bSCho, Yu-Chen m3 = 0;
1668c9274b6bSCho, Yu-Chen }
1669c9274b6bSCho, Yu-Chen /* m4 field was introduced with FPE */
1670c9274b6bSCho, Yu-Chen if (!fpe && m4_with_fpe) {
1671c9274b6bSCho, Yu-Chen m4 = 0;
1672c9274b6bSCho, Yu-Chen }
1673c9274b6bSCho, Yu-Chen
1674c9274b6bSCho, Yu-Chen /* Check for valid rounding modes. Mode 3 was introduced later. */
1675c9274b6bSCho, Yu-Chen if (m3 == 2 || m3 > 7 || (!fpe && m3 == 3)) {
1676c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
1677c9274b6bSCho, Yu-Chen return NULL;
1678c9274b6bSCho, Yu-Chen }
1679c9274b6bSCho, Yu-Chen
16806276d93fSRichard Henderson return tcg_constant_i32(deposit32(m3, 4, 4, m4));
1681c9274b6bSCho, Yu-Chen }
1682c9274b6bSCho, Yu-Chen
op_cfeb(DisasContext * s,DisasOps * o)1683c9274b6bSCho, Yu-Chen static DisasJumpType op_cfeb(DisasContext *s, DisasOps *o)
1684c9274b6bSCho, Yu-Chen {
1685c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
1686c9274b6bSCho, Yu-Chen
1687c9274b6bSCho, Yu-Chen if (!m34) {
1688c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1689c9274b6bSCho, Yu-Chen }
1690ad75a51eSRichard Henderson gen_helper_cfeb(o->out, tcg_env, o->in2, m34);
1691c9274b6bSCho, Yu-Chen set_cc_static(s);
1692c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1693c9274b6bSCho, Yu-Chen }
1694c9274b6bSCho, Yu-Chen
op_cfdb(DisasContext * s,DisasOps * o)1695c9274b6bSCho, Yu-Chen static DisasJumpType op_cfdb(DisasContext *s, DisasOps *o)
1696c9274b6bSCho, Yu-Chen {
1697c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
1698c9274b6bSCho, Yu-Chen
1699c9274b6bSCho, Yu-Chen if (!m34) {
1700c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1701c9274b6bSCho, Yu-Chen }
1702ad75a51eSRichard Henderson gen_helper_cfdb(o->out, tcg_env, o->in2, m34);
1703c9274b6bSCho, Yu-Chen set_cc_static(s);
1704c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1705c9274b6bSCho, Yu-Chen }
1706c9274b6bSCho, Yu-Chen
op_cfxb(DisasContext * s,DisasOps * o)1707c9274b6bSCho, Yu-Chen static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o)
1708c9274b6bSCho, Yu-Chen {
1709c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
1710c9274b6bSCho, Yu-Chen
1711c9274b6bSCho, Yu-Chen if (!m34) {
1712c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1713c9274b6bSCho, Yu-Chen }
1714ad75a51eSRichard Henderson gen_helper_cfxb(o->out, tcg_env, o->in2_128, m34);
1715c9274b6bSCho, Yu-Chen set_cc_static(s);
1716c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1717c9274b6bSCho, Yu-Chen }
1718c9274b6bSCho, Yu-Chen
op_cgeb(DisasContext * s,DisasOps * o)1719c9274b6bSCho, Yu-Chen static DisasJumpType op_cgeb(DisasContext *s, DisasOps *o)
1720c9274b6bSCho, Yu-Chen {
1721c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
1722c9274b6bSCho, Yu-Chen
1723c9274b6bSCho, Yu-Chen if (!m34) {
1724c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1725c9274b6bSCho, Yu-Chen }
1726ad75a51eSRichard Henderson gen_helper_cgeb(o->out, tcg_env, o->in2, m34);
1727c9274b6bSCho, Yu-Chen set_cc_static(s);
1728c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1729c9274b6bSCho, Yu-Chen }
1730c9274b6bSCho, Yu-Chen
op_cgdb(DisasContext * s,DisasOps * o)1731c9274b6bSCho, Yu-Chen static DisasJumpType op_cgdb(DisasContext *s, DisasOps *o)
1732c9274b6bSCho, Yu-Chen {
1733c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
1734c9274b6bSCho, Yu-Chen
1735c9274b6bSCho, Yu-Chen if (!m34) {
1736c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1737c9274b6bSCho, Yu-Chen }
1738ad75a51eSRichard Henderson gen_helper_cgdb(o->out, tcg_env, o->in2, m34);
1739c9274b6bSCho, Yu-Chen set_cc_static(s);
1740c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1741c9274b6bSCho, Yu-Chen }
1742c9274b6bSCho, Yu-Chen
op_cgxb(DisasContext * s,DisasOps * o)1743c9274b6bSCho, Yu-Chen static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o)
1744c9274b6bSCho, Yu-Chen {
1745c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
1746c9274b6bSCho, Yu-Chen
1747c9274b6bSCho, Yu-Chen if (!m34) {
1748c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1749c9274b6bSCho, Yu-Chen }
1750ad75a51eSRichard Henderson gen_helper_cgxb(o->out, tcg_env, o->in2_128, m34);
1751c9274b6bSCho, Yu-Chen set_cc_static(s);
1752c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1753c9274b6bSCho, Yu-Chen }
1754c9274b6bSCho, Yu-Chen
op_clfeb(DisasContext * s,DisasOps * o)1755c9274b6bSCho, Yu-Chen static DisasJumpType op_clfeb(DisasContext *s, DisasOps *o)
1756c9274b6bSCho, Yu-Chen {
1757c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1758c9274b6bSCho, Yu-Chen
1759c9274b6bSCho, Yu-Chen if (!m34) {
1760c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1761c9274b6bSCho, Yu-Chen }
1762ad75a51eSRichard Henderson gen_helper_clfeb(o->out, tcg_env, o->in2, m34);
1763c9274b6bSCho, Yu-Chen set_cc_static(s);
1764c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1765c9274b6bSCho, Yu-Chen }
1766c9274b6bSCho, Yu-Chen
op_clfdb(DisasContext * s,DisasOps * o)1767c9274b6bSCho, Yu-Chen static DisasJumpType op_clfdb(DisasContext *s, DisasOps *o)
1768c9274b6bSCho, Yu-Chen {
1769c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1770c9274b6bSCho, Yu-Chen
1771c9274b6bSCho, Yu-Chen if (!m34) {
1772c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1773c9274b6bSCho, Yu-Chen }
1774ad75a51eSRichard Henderson gen_helper_clfdb(o->out, tcg_env, o->in2, m34);
1775c9274b6bSCho, Yu-Chen set_cc_static(s);
1776c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1777c9274b6bSCho, Yu-Chen }
1778c9274b6bSCho, Yu-Chen
op_clfxb(DisasContext * s,DisasOps * o)1779c9274b6bSCho, Yu-Chen static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o)
1780c9274b6bSCho, Yu-Chen {
1781c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1782c9274b6bSCho, Yu-Chen
1783c9274b6bSCho, Yu-Chen if (!m34) {
1784c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1785c9274b6bSCho, Yu-Chen }
1786ad75a51eSRichard Henderson gen_helper_clfxb(o->out, tcg_env, o->in2_128, m34);
1787c9274b6bSCho, Yu-Chen set_cc_static(s);
1788c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1789c9274b6bSCho, Yu-Chen }
1790c9274b6bSCho, Yu-Chen
op_clgeb(DisasContext * s,DisasOps * o)1791c9274b6bSCho, Yu-Chen static DisasJumpType op_clgeb(DisasContext *s, DisasOps *o)
1792c9274b6bSCho, Yu-Chen {
1793c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1794c9274b6bSCho, Yu-Chen
1795c9274b6bSCho, Yu-Chen if (!m34) {
1796c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1797c9274b6bSCho, Yu-Chen }
1798ad75a51eSRichard Henderson gen_helper_clgeb(o->out, tcg_env, o->in2, m34);
1799c9274b6bSCho, Yu-Chen set_cc_static(s);
1800c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1801c9274b6bSCho, Yu-Chen }
1802c9274b6bSCho, Yu-Chen
op_clgdb(DisasContext * s,DisasOps * o)1803c9274b6bSCho, Yu-Chen static DisasJumpType op_clgdb(DisasContext *s, DisasOps *o)
1804c9274b6bSCho, Yu-Chen {
1805c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1806c9274b6bSCho, Yu-Chen
1807c9274b6bSCho, Yu-Chen if (!m34) {
1808c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1809c9274b6bSCho, Yu-Chen }
1810ad75a51eSRichard Henderson gen_helper_clgdb(o->out, tcg_env, o->in2, m34);
1811c9274b6bSCho, Yu-Chen set_cc_static(s);
1812c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1813c9274b6bSCho, Yu-Chen }
1814c9274b6bSCho, Yu-Chen
op_clgxb(DisasContext * s,DisasOps * o)1815c9274b6bSCho, Yu-Chen static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o)
1816c9274b6bSCho, Yu-Chen {
1817c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1818c9274b6bSCho, Yu-Chen
1819c9274b6bSCho, Yu-Chen if (!m34) {
1820c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1821c9274b6bSCho, Yu-Chen }
1822ad75a51eSRichard Henderson gen_helper_clgxb(o->out, tcg_env, o->in2_128, m34);
1823c9274b6bSCho, Yu-Chen set_cc_static(s);
1824c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1825c9274b6bSCho, Yu-Chen }
1826c9274b6bSCho, Yu-Chen
op_cegb(DisasContext * s,DisasOps * o)1827c9274b6bSCho, Yu-Chen static DisasJumpType op_cegb(DisasContext *s, DisasOps *o)
1828c9274b6bSCho, Yu-Chen {
1829c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, true, true);
1830c9274b6bSCho, Yu-Chen
1831c9274b6bSCho, Yu-Chen if (!m34) {
1832c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1833c9274b6bSCho, Yu-Chen }
1834ad75a51eSRichard Henderson gen_helper_cegb(o->out, tcg_env, o->in2, m34);
1835c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1836c9274b6bSCho, Yu-Chen }
1837c9274b6bSCho, Yu-Chen
op_cdgb(DisasContext * s,DisasOps * o)1838c9274b6bSCho, Yu-Chen static DisasJumpType op_cdgb(DisasContext *s, DisasOps *o)
1839c9274b6bSCho, Yu-Chen {
1840c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, true, true);
1841c9274b6bSCho, Yu-Chen
1842c9274b6bSCho, Yu-Chen if (!m34) {
1843c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1844c9274b6bSCho, Yu-Chen }
1845ad75a51eSRichard Henderson gen_helper_cdgb(o->out, tcg_env, o->in2, m34);
1846c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1847c9274b6bSCho, Yu-Chen }
1848c9274b6bSCho, Yu-Chen
op_cxgb(DisasContext * s,DisasOps * o)1849c9274b6bSCho, Yu-Chen static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o)
1850c9274b6bSCho, Yu-Chen {
1851c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, true, true);
1852c9274b6bSCho, Yu-Chen
1853c9274b6bSCho, Yu-Chen if (!m34) {
1854c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1855c9274b6bSCho, Yu-Chen }
1856ad75a51eSRichard Henderson gen_helper_cxgb(o->out_128, tcg_env, o->in2, m34);
1857c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1858c9274b6bSCho, Yu-Chen }
1859c9274b6bSCho, Yu-Chen
op_celgb(DisasContext * s,DisasOps * o)1860c9274b6bSCho, Yu-Chen static DisasJumpType op_celgb(DisasContext *s, DisasOps *o)
1861c9274b6bSCho, Yu-Chen {
1862c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1863c9274b6bSCho, Yu-Chen
1864c9274b6bSCho, Yu-Chen if (!m34) {
1865c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1866c9274b6bSCho, Yu-Chen }
1867ad75a51eSRichard Henderson gen_helper_celgb(o->out, tcg_env, o->in2, m34);
1868c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1869c9274b6bSCho, Yu-Chen }
1870c9274b6bSCho, Yu-Chen
op_cdlgb(DisasContext * s,DisasOps * o)1871c9274b6bSCho, Yu-Chen static DisasJumpType op_cdlgb(DisasContext *s, DisasOps *o)
1872c9274b6bSCho, Yu-Chen {
1873c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1874c9274b6bSCho, Yu-Chen
1875c9274b6bSCho, Yu-Chen if (!m34) {
1876c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1877c9274b6bSCho, Yu-Chen }
1878ad75a51eSRichard Henderson gen_helper_cdlgb(o->out, tcg_env, o->in2, m34);
1879c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1880c9274b6bSCho, Yu-Chen }
1881c9274b6bSCho, Yu-Chen
op_cxlgb(DisasContext * s,DisasOps * o)1882c9274b6bSCho, Yu-Chen static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o)
1883c9274b6bSCho, Yu-Chen {
1884c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, false);
1885c9274b6bSCho, Yu-Chen
1886c9274b6bSCho, Yu-Chen if (!m34) {
1887c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1888c9274b6bSCho, Yu-Chen }
1889ad75a51eSRichard Henderson gen_helper_cxlgb(o->out_128, tcg_env, o->in2, m34);
1890c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1891c9274b6bSCho, Yu-Chen }
1892c9274b6bSCho, Yu-Chen
op_cksm(DisasContext * s,DisasOps * o)1893c9274b6bSCho, Yu-Chen static DisasJumpType op_cksm(DisasContext *s, DisasOps *o)
1894c9274b6bSCho, Yu-Chen {
1895c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
1896c9119224SRichard Henderson TCGv_i128 pair = tcg_temp_new_i128();
1897c9274b6bSCho, Yu-Chen TCGv_i64 len = tcg_temp_new_i64();
1898c9274b6bSCho, Yu-Chen
1899ad75a51eSRichard Henderson gen_helper_cksm(pair, tcg_env, o->in1, o->in2, regs[r2 + 1]);
1900c9274b6bSCho, Yu-Chen set_cc_static(s);
1901c9119224SRichard Henderson tcg_gen_extr_i128_i64(o->out, len, pair);
1902c9274b6bSCho, Yu-Chen
1903c9274b6bSCho, Yu-Chen tcg_gen_add_i64(regs[r2], regs[r2], len);
1904c9274b6bSCho, Yu-Chen tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len);
1905c9274b6bSCho, Yu-Chen
1906c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1907c9274b6bSCho, Yu-Chen }
1908c9274b6bSCho, Yu-Chen
op_clc(DisasContext * s,DisasOps * o)1909c9274b6bSCho, Yu-Chen static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
1910c9274b6bSCho, Yu-Chen {
1911c9274b6bSCho, Yu-Chen int l = get_field(s, l1);
1912aba2ec34SIlya Leoshkevich TCGv_i64 src;
1913c9274b6bSCho, Yu-Chen TCGv_i32 vl;
1914e87027d0SRichard Henderson MemOp mop;
1915c9274b6bSCho, Yu-Chen
1916c9274b6bSCho, Yu-Chen switch (l + 1) {
1917c9274b6bSCho, Yu-Chen case 1:
1918c9274b6bSCho, Yu-Chen case 2:
1919c9274b6bSCho, Yu-Chen case 4:
1920c9274b6bSCho, Yu-Chen case 8:
1921e87027d0SRichard Henderson mop = ctz32(l + 1) | MO_TE;
1922aba2ec34SIlya Leoshkevich /* Do not update cc_src yet: loading cc_dst may cause an exception. */
1923aba2ec34SIlya Leoshkevich src = tcg_temp_new_i64();
1924aba2ec34SIlya Leoshkevich tcg_gen_qemu_ld_tl(src, o->addr1, get_mem_index(s), mop);
1925e87027d0SRichard Henderson tcg_gen_qemu_ld_tl(cc_dst, o->in2, get_mem_index(s), mop);
1926aba2ec34SIlya Leoshkevich gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, src, cc_dst);
1927e87027d0SRichard Henderson return DISAS_NEXT;
1928c9274b6bSCho, Yu-Chen default:
1929f1ea739bSRichard Henderson vl = tcg_constant_i32(l);
1930ad75a51eSRichard Henderson gen_helper_clc(cc_op, tcg_env, vl, o->addr1, o->in2);
1931c9274b6bSCho, Yu-Chen set_cc_static(s);
1932c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1933c9274b6bSCho, Yu-Chen }
1934c9274b6bSCho, Yu-Chen }
1935c9274b6bSCho, Yu-Chen
op_clcl(DisasContext * s,DisasOps * o)1936c9274b6bSCho, Yu-Chen static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
1937c9274b6bSCho, Yu-Chen {
1938c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1939c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
1940c9274b6bSCho, Yu-Chen TCGv_i32 t1, t2;
1941c9274b6bSCho, Yu-Chen
1942c9274b6bSCho, Yu-Chen /* r1 and r2 must be even. */
1943c9274b6bSCho, Yu-Chen if (r1 & 1 || r2 & 1) {
1944c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
1945c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1946c9274b6bSCho, Yu-Chen }
1947c9274b6bSCho, Yu-Chen
1948f1ea739bSRichard Henderson t1 = tcg_constant_i32(r1);
1949f1ea739bSRichard Henderson t2 = tcg_constant_i32(r2);
1950ad75a51eSRichard Henderson gen_helper_clcl(cc_op, tcg_env, t1, t2);
1951c9274b6bSCho, Yu-Chen set_cc_static(s);
1952c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1953c9274b6bSCho, Yu-Chen }
1954c9274b6bSCho, Yu-Chen
op_clcle(DisasContext * s,DisasOps * o)1955c9274b6bSCho, Yu-Chen static DisasJumpType op_clcle(DisasContext *s, DisasOps *o)
1956c9274b6bSCho, Yu-Chen {
1957c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1958c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
1959c9274b6bSCho, Yu-Chen TCGv_i32 t1, t3;
1960c9274b6bSCho, Yu-Chen
1961c9274b6bSCho, Yu-Chen /* r1 and r3 must be even. */
1962c9274b6bSCho, Yu-Chen if (r1 & 1 || r3 & 1) {
1963c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
1964c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1965c9274b6bSCho, Yu-Chen }
1966c9274b6bSCho, Yu-Chen
1967f1ea739bSRichard Henderson t1 = tcg_constant_i32(r1);
1968f1ea739bSRichard Henderson t3 = tcg_constant_i32(r3);
1969ad75a51eSRichard Henderson gen_helper_clcle(cc_op, tcg_env, t1, o->in2, t3);
1970c9274b6bSCho, Yu-Chen set_cc_static(s);
1971c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1972c9274b6bSCho, Yu-Chen }
1973c9274b6bSCho, Yu-Chen
op_clclu(DisasContext * s,DisasOps * o)1974c9274b6bSCho, Yu-Chen static DisasJumpType op_clclu(DisasContext *s, DisasOps *o)
1975c9274b6bSCho, Yu-Chen {
1976c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
1977c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
1978c9274b6bSCho, Yu-Chen TCGv_i32 t1, t3;
1979c9274b6bSCho, Yu-Chen
1980c9274b6bSCho, Yu-Chen /* r1 and r3 must be even. */
1981c9274b6bSCho, Yu-Chen if (r1 & 1 || r3 & 1) {
1982c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
1983c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
1984c9274b6bSCho, Yu-Chen }
1985c9274b6bSCho, Yu-Chen
1986f1ea739bSRichard Henderson t1 = tcg_constant_i32(r1);
1987f1ea739bSRichard Henderson t3 = tcg_constant_i32(r3);
1988ad75a51eSRichard Henderson gen_helper_clclu(cc_op, tcg_env, t1, o->in2, t3);
1989c9274b6bSCho, Yu-Chen set_cc_static(s);
1990c9274b6bSCho, Yu-Chen return DISAS_NEXT;
1991c9274b6bSCho, Yu-Chen }
1992c9274b6bSCho, Yu-Chen
op_clm(DisasContext * s,DisasOps * o)1993c9274b6bSCho, Yu-Chen static DisasJumpType op_clm(DisasContext *s, DisasOps *o)
1994c9274b6bSCho, Yu-Chen {
1995f1ea739bSRichard Henderson TCGv_i32 m3 = tcg_constant_i32(get_field(s, m3));
1996c9274b6bSCho, Yu-Chen TCGv_i32 t1 = tcg_temp_new_i32();
1997f1ea739bSRichard Henderson
1998c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(t1, o->in1);
1999ad75a51eSRichard Henderson gen_helper_clm(cc_op, tcg_env, t1, m3, o->in2);
2000c9274b6bSCho, Yu-Chen set_cc_static(s);
2001c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2002c9274b6bSCho, Yu-Chen }
2003c9274b6bSCho, Yu-Chen
op_clst(DisasContext * s,DisasOps * o)2004c9274b6bSCho, Yu-Chen static DisasJumpType op_clst(DisasContext *s, DisasOps *o)
2005c9274b6bSCho, Yu-Chen {
2006b71dd2a5SRichard Henderson TCGv_i128 pair = tcg_temp_new_i128();
2007b71dd2a5SRichard Henderson
2008ad75a51eSRichard Henderson gen_helper_clst(pair, tcg_env, regs[0], o->in1, o->in2);
2009b71dd2a5SRichard Henderson tcg_gen_extr_i128_i64(o->in2, o->in1, pair);
2010b71dd2a5SRichard Henderson
2011c9274b6bSCho, Yu-Chen set_cc_static(s);
2012c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2013c9274b6bSCho, Yu-Chen }
2014c9274b6bSCho, Yu-Chen
op_cps(DisasContext * s,DisasOps * o)2015c9274b6bSCho, Yu-Chen static DisasJumpType op_cps(DisasContext *s, DisasOps *o)
2016c9274b6bSCho, Yu-Chen {
2017c9274b6bSCho, Yu-Chen TCGv_i64 t = tcg_temp_new_i64();
2018c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull);
2019c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull);
2020c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->out, t);
2021c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2022c9274b6bSCho, Yu-Chen }
2023c9274b6bSCho, Yu-Chen
op_cs(DisasContext * s,DisasOps * o)2024c9274b6bSCho, Yu-Chen static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
2025c9274b6bSCho, Yu-Chen {
2026c9274b6bSCho, Yu-Chen int d2 = get_field(s, d2);
2027c9274b6bSCho, Yu-Chen int b2 = get_field(s, b2);
2028c9274b6bSCho, Yu-Chen TCGv_i64 addr, cc;
2029c9274b6bSCho, Yu-Chen
2030c9274b6bSCho, Yu-Chen /* Note that in1 = R3 (new value) and
2031c9274b6bSCho, Yu-Chen in2 = (zero-extended) R1 (expected value). */
2032c9274b6bSCho, Yu-Chen
2033c9274b6bSCho, Yu-Chen addr = get_address(s, 0, b2, d2);
2034c9274b6bSCho, Yu-Chen tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1,
2035c9274b6bSCho, Yu-Chen get_mem_index(s), s->insn->data | MO_ALIGN);
2036c9274b6bSCho, Yu-Chen
2037c9274b6bSCho, Yu-Chen /* Are the memory and expected values (un)equal? Note that this setcond
2038c9274b6bSCho, Yu-Chen produces the output CC value, thus the NE sense of the test. */
2039c9274b6bSCho, Yu-Chen cc = tcg_temp_new_i64();
2040c9274b6bSCho, Yu-Chen tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out);
2041c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(cc_op, cc);
2042c9274b6bSCho, Yu-Chen set_cc_static(s);
2043c9274b6bSCho, Yu-Chen
2044c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2045c9274b6bSCho, Yu-Chen }
2046c9274b6bSCho, Yu-Chen
op_cdsg(DisasContext * s,DisasOps * o)2047c9274b6bSCho, Yu-Chen static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
2048c9274b6bSCho, Yu-Chen {
2049c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
2050c9274b6bSCho, Yu-Chen
20511fcd84faSRichard Henderson o->out_128 = tcg_temp_new_i128();
20521fcd84faSRichard Henderson tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]);
2053c9274b6bSCho, Yu-Chen
20541fcd84faSRichard Henderson /* Note out (R1:R1+1) = expected value and in2 (R3:R3+1) = new value. */
20551fcd84faSRichard Henderson tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_128,
20561fcd84faSRichard Henderson get_mem_index(s), MO_BE | MO_128 | MO_ALIGN);
20571fcd84faSRichard Henderson
20581fcd84faSRichard Henderson /*
20591fcd84faSRichard Henderson * Extract result into cc_dst:cc_src, compare vs the expected value
20601fcd84faSRichard Henderson * in the as yet unmodified input registers, then update CC_OP.
20611fcd84faSRichard Henderson */
20621fcd84faSRichard Henderson tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128);
20631fcd84faSRichard Henderson tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]);
20641fcd84faSRichard Henderson tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]);
20651fcd84faSRichard Henderson tcg_gen_or_i64(cc_dst, cc_dst, cc_src);
20661fcd84faSRichard Henderson set_cc_nz_u64(s, cc_dst);
20671fcd84faSRichard Henderson
20681fcd84faSRichard Henderson return DISAS_NEXT;
2069c9274b6bSCho, Yu-Chen }
2070c9274b6bSCho, Yu-Chen
op_csst(DisasContext * s,DisasOps * o)2071c9274b6bSCho, Yu-Chen static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
2072c9274b6bSCho, Yu-Chen {
2073c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
2074f1ea739bSRichard Henderson TCGv_i32 t_r3 = tcg_constant_i32(r3);
2075c9274b6bSCho, Yu-Chen
2076c9274b6bSCho, Yu-Chen if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2077ad75a51eSRichard Henderson gen_helper_csst_parallel(cc_op, tcg_env, t_r3, o->addr1, o->in2);
2078c9274b6bSCho, Yu-Chen } else {
2079ad75a51eSRichard Henderson gen_helper_csst(cc_op, tcg_env, t_r3, o->addr1, o->in2);
2080c9274b6bSCho, Yu-Chen }
2081c9274b6bSCho, Yu-Chen
2082c9274b6bSCho, Yu-Chen set_cc_static(s);
2083c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2084c9274b6bSCho, Yu-Chen }
2085c9274b6bSCho, Yu-Chen
2086c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_csp(DisasContext * s,DisasOps * o)2087c9274b6bSCho, Yu-Chen static DisasJumpType op_csp(DisasContext *s, DisasOps *o)
2088c9274b6bSCho, Yu-Chen {
2089c9274b6bSCho, Yu-Chen MemOp mop = s->insn->data;
2090c9274b6bSCho, Yu-Chen TCGv_i64 addr, old, cc;
2091c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2092c9274b6bSCho, Yu-Chen
2093c9274b6bSCho, Yu-Chen /* Note that in1 = R1 (zero-extended expected value),
2094c9274b6bSCho, Yu-Chen out = R1 (original reg), out2 = R1+1 (new value). */
2095c9274b6bSCho, Yu-Chen
2096c9274b6bSCho, Yu-Chen addr = tcg_temp_new_i64();
2097c9274b6bSCho, Yu-Chen old = tcg_temp_new_i64();
2098c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE));
2099c9274b6bSCho, Yu-Chen tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2,
2100c9274b6bSCho, Yu-Chen get_mem_index(s), mop | MO_ALIGN);
2101c9274b6bSCho, Yu-Chen
2102c9274b6bSCho, Yu-Chen /* Are the memory and expected values (un)equal? */
2103c9274b6bSCho, Yu-Chen cc = tcg_temp_new_i64();
2104c9274b6bSCho, Yu-Chen tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in1, old);
2105c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(cc_op, cc);
2106c9274b6bSCho, Yu-Chen
2107c9274b6bSCho, Yu-Chen /* Write back the output now, so that it happens before the
2108c9274b6bSCho, Yu-Chen following branch, so that we don't need local temps. */
2109c9274b6bSCho, Yu-Chen if ((mop & MO_SIZE) == MO_32) {
2110c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(o->out, o->out, old, 0, 32);
2111c9274b6bSCho, Yu-Chen } else {
2112c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(o->out, old);
2113c9274b6bSCho, Yu-Chen }
2114c9274b6bSCho, Yu-Chen
2115c9274b6bSCho, Yu-Chen /* If the comparison was equal, and the LSB of R2 was set,
2116c9274b6bSCho, Yu-Chen then we need to flush the TLB (for all cpus). */
2117c9274b6bSCho, Yu-Chen tcg_gen_xori_i64(cc, cc, 1);
2118c9274b6bSCho, Yu-Chen tcg_gen_and_i64(cc, cc, o->in2);
2119c9274b6bSCho, Yu-Chen tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab);
2120c9274b6bSCho, Yu-Chen
2121ad75a51eSRichard Henderson gen_helper_purge(tcg_env);
2122c9274b6bSCho, Yu-Chen gen_set_label(lab);
2123c9274b6bSCho, Yu-Chen
2124c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2125c9274b6bSCho, Yu-Chen }
2126c9274b6bSCho, Yu-Chen #endif
2127c9274b6bSCho, Yu-Chen
op_cvb(DisasContext * s,DisasOps * o)2128b4b8d58eSIlya Leoshkevich static DisasJumpType op_cvb(DisasContext *s, DisasOps *o)
2129b4b8d58eSIlya Leoshkevich {
2130b4b8d58eSIlya Leoshkevich TCGv_i64 t = tcg_temp_new_i64();
2131b4b8d58eSIlya Leoshkevich tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TEUQ);
2132b4b8d58eSIlya Leoshkevich gen_helper_cvb(tcg_env, tcg_constant_i32(get_field(s, r1)), t);
2133b4b8d58eSIlya Leoshkevich return DISAS_NEXT;
2134b4b8d58eSIlya Leoshkevich }
2135b4b8d58eSIlya Leoshkevich
op_cvbg(DisasContext * s,DisasOps * o)2136b4b8d58eSIlya Leoshkevich static DisasJumpType op_cvbg(DisasContext *s, DisasOps *o)
2137b4b8d58eSIlya Leoshkevich {
2138b4b8d58eSIlya Leoshkevich TCGv_i128 t = tcg_temp_new_i128();
2139b4b8d58eSIlya Leoshkevich tcg_gen_qemu_ld_i128(t, o->addr1, get_mem_index(s), MO_TE | MO_128);
2140b4b8d58eSIlya Leoshkevich gen_helper_cvbg(o->out, tcg_env, t);
2141b4b8d58eSIlya Leoshkevich return DISAS_NEXT;
2142b4b8d58eSIlya Leoshkevich }
2143b4b8d58eSIlya Leoshkevich
op_cvd(DisasContext * s,DisasOps * o)2144c9274b6bSCho, Yu-Chen static DisasJumpType op_cvd(DisasContext *s, DisasOps *o)
2145c9274b6bSCho, Yu-Chen {
2146c9274b6bSCho, Yu-Chen TCGv_i64 t1 = tcg_temp_new_i64();
2147c9274b6bSCho, Yu-Chen TCGv_i32 t2 = tcg_temp_new_i32();
2148c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(t2, o->in1);
2149c9274b6bSCho, Yu-Chen gen_helper_cvd(t1, t2);
2150e87027d0SRichard Henderson tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
2151c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2152c9274b6bSCho, Yu-Chen }
2153c9274b6bSCho, Yu-Chen
op_cvdg(DisasContext * s,DisasOps * o)2154a6e55a82SIlya Leoshkevich static DisasJumpType op_cvdg(DisasContext *s, DisasOps *o)
2155a6e55a82SIlya Leoshkevich {
2156a6e55a82SIlya Leoshkevich TCGv_i128 t = tcg_temp_new_i128();
2157a6e55a82SIlya Leoshkevich gen_helper_cvdg(t, o->in1);
2158a6e55a82SIlya Leoshkevich tcg_gen_qemu_st_i128(t, o->in2, get_mem_index(s), MO_TE | MO_128);
2159a6e55a82SIlya Leoshkevich return DISAS_NEXT;
2160a6e55a82SIlya Leoshkevich }
2161a6e55a82SIlya Leoshkevich
op_ct(DisasContext * s,DisasOps * o)2162c9274b6bSCho, Yu-Chen static DisasJumpType op_ct(DisasContext *s, DisasOps *o)
2163c9274b6bSCho, Yu-Chen {
2164c9274b6bSCho, Yu-Chen int m3 = get_field(s, m3);
2165c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2166c9274b6bSCho, Yu-Chen TCGCond c;
2167c9274b6bSCho, Yu-Chen
2168c9274b6bSCho, Yu-Chen c = tcg_invert_cond(ltgt_cond[m3]);
2169c9274b6bSCho, Yu-Chen if (s->insn->data) {
2170c9274b6bSCho, Yu-Chen c = tcg_unsigned_cond(c);
2171c9274b6bSCho, Yu-Chen }
2172c9274b6bSCho, Yu-Chen tcg_gen_brcond_i64(c, o->in1, o->in2, lab);
2173c9274b6bSCho, Yu-Chen
2174c9274b6bSCho, Yu-Chen /* Trap. */
2175c9274b6bSCho, Yu-Chen gen_trap(s);
2176c9274b6bSCho, Yu-Chen
2177c9274b6bSCho, Yu-Chen gen_set_label(lab);
2178c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2179c9274b6bSCho, Yu-Chen }
2180c9274b6bSCho, Yu-Chen
op_cuXX(DisasContext * s,DisasOps * o)2181c9274b6bSCho, Yu-Chen static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o)
2182c9274b6bSCho, Yu-Chen {
2183c9274b6bSCho, Yu-Chen int m3 = get_field(s, m3);
2184c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
2185c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
2186c9274b6bSCho, Yu-Chen TCGv_i32 tr1, tr2, chk;
2187c9274b6bSCho, Yu-Chen
2188c9274b6bSCho, Yu-Chen /* R1 and R2 must both be even. */
2189c9274b6bSCho, Yu-Chen if ((r1 | r2) & 1) {
2190c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
2191c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2192c9274b6bSCho, Yu-Chen }
2193c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_ETF3_ENH)) {
2194c9274b6bSCho, Yu-Chen m3 = 0;
2195c9274b6bSCho, Yu-Chen }
2196c9274b6bSCho, Yu-Chen
2197f1ea739bSRichard Henderson tr1 = tcg_constant_i32(r1);
2198f1ea739bSRichard Henderson tr2 = tcg_constant_i32(r2);
2199f1ea739bSRichard Henderson chk = tcg_constant_i32(m3);
2200c9274b6bSCho, Yu-Chen
2201c9274b6bSCho, Yu-Chen switch (s->insn->data) {
2202c9274b6bSCho, Yu-Chen case 12:
2203ad75a51eSRichard Henderson gen_helper_cu12(cc_op, tcg_env, tr1, tr2, chk);
2204c9274b6bSCho, Yu-Chen break;
2205c9274b6bSCho, Yu-Chen case 14:
2206ad75a51eSRichard Henderson gen_helper_cu14(cc_op, tcg_env, tr1, tr2, chk);
2207c9274b6bSCho, Yu-Chen break;
2208c9274b6bSCho, Yu-Chen case 21:
2209ad75a51eSRichard Henderson gen_helper_cu21(cc_op, tcg_env, tr1, tr2, chk);
2210c9274b6bSCho, Yu-Chen break;
2211c9274b6bSCho, Yu-Chen case 24:
2212ad75a51eSRichard Henderson gen_helper_cu24(cc_op, tcg_env, tr1, tr2, chk);
2213c9274b6bSCho, Yu-Chen break;
2214c9274b6bSCho, Yu-Chen case 41:
2215ad75a51eSRichard Henderson gen_helper_cu41(cc_op, tcg_env, tr1, tr2, chk);
2216c9274b6bSCho, Yu-Chen break;
2217c9274b6bSCho, Yu-Chen case 42:
2218ad75a51eSRichard Henderson gen_helper_cu42(cc_op, tcg_env, tr1, tr2, chk);
2219c9274b6bSCho, Yu-Chen break;
2220c9274b6bSCho, Yu-Chen default:
2221c9274b6bSCho, Yu-Chen g_assert_not_reached();
2222c9274b6bSCho, Yu-Chen }
2223c9274b6bSCho, Yu-Chen
2224c9274b6bSCho, Yu-Chen set_cc_static(s);
2225c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2226c9274b6bSCho, Yu-Chen }
2227c9274b6bSCho, Yu-Chen
2228c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_diag(DisasContext * s,DisasOps * o)2229c9274b6bSCho, Yu-Chen static DisasJumpType op_diag(DisasContext *s, DisasOps *o)
2230c9274b6bSCho, Yu-Chen {
2231f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
2232f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
2233f1ea739bSRichard Henderson TCGv_i32 func_code = tcg_constant_i32(get_field(s, i2));
2234c9274b6bSCho, Yu-Chen
2235ad75a51eSRichard Henderson gen_helper_diag(tcg_env, r1, r3, func_code);
2236c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2237c9274b6bSCho, Yu-Chen }
2238c9274b6bSCho, Yu-Chen #endif
2239c9274b6bSCho, Yu-Chen
op_divs32(DisasContext * s,DisasOps * o)2240c9274b6bSCho, Yu-Chen static DisasJumpType op_divs32(DisasContext *s, DisasOps *o)
2241c9274b6bSCho, Yu-Chen {
2242ad75a51eSRichard Henderson gen_helper_divs32(o->out, tcg_env, o->in1, o->in2);
22436d28ff40SRichard Henderson tcg_gen_extr32_i64(o->out2, o->out, o->out);
2244c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2245c9274b6bSCho, Yu-Chen }
2246c9274b6bSCho, Yu-Chen
op_divu32(DisasContext * s,DisasOps * o)2247c9274b6bSCho, Yu-Chen static DisasJumpType op_divu32(DisasContext *s, DisasOps *o)
2248c9274b6bSCho, Yu-Chen {
2249ad75a51eSRichard Henderson gen_helper_divu32(o->out, tcg_env, o->in1, o->in2);
22506d28ff40SRichard Henderson tcg_gen_extr32_i64(o->out2, o->out, o->out);
2251c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2252c9274b6bSCho, Yu-Chen }
2253c9274b6bSCho, Yu-Chen
op_divs64(DisasContext * s,DisasOps * o)2254c9274b6bSCho, Yu-Chen static DisasJumpType op_divs64(DisasContext *s, DisasOps *o)
2255c9274b6bSCho, Yu-Chen {
22564e5712f9SRichard Henderson TCGv_i128 t = tcg_temp_new_i128();
22574e5712f9SRichard Henderson
2258ad75a51eSRichard Henderson gen_helper_divs64(t, tcg_env, o->in1, o->in2);
22594e5712f9SRichard Henderson tcg_gen_extr_i128_i64(o->out2, o->out, t);
2260c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2261c9274b6bSCho, Yu-Chen }
2262c9274b6bSCho, Yu-Chen
op_divu64(DisasContext * s,DisasOps * o)2263c9274b6bSCho, Yu-Chen static DisasJumpType op_divu64(DisasContext *s, DisasOps *o)
2264c9274b6bSCho, Yu-Chen {
22654e5712f9SRichard Henderson TCGv_i128 t = tcg_temp_new_i128();
22664e5712f9SRichard Henderson
2267ad75a51eSRichard Henderson gen_helper_divu64(t, tcg_env, o->out, o->out2, o->in2);
22684e5712f9SRichard Henderson tcg_gen_extr_i128_i64(o->out2, o->out, t);
2269c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2270c9274b6bSCho, Yu-Chen }
2271c9274b6bSCho, Yu-Chen
op_deb(DisasContext * s,DisasOps * o)2272c9274b6bSCho, Yu-Chen static DisasJumpType op_deb(DisasContext *s, DisasOps *o)
2273c9274b6bSCho, Yu-Chen {
2274ad75a51eSRichard Henderson gen_helper_deb(o->out, tcg_env, o->in1, o->in2);
2275c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2276c9274b6bSCho, Yu-Chen }
2277c9274b6bSCho, Yu-Chen
op_ddb(DisasContext * s,DisasOps * o)2278c9274b6bSCho, Yu-Chen static DisasJumpType op_ddb(DisasContext *s, DisasOps *o)
2279c9274b6bSCho, Yu-Chen {
2280ad75a51eSRichard Henderson gen_helper_ddb(o->out, tcg_env, o->in1, o->in2);
2281c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2282c9274b6bSCho, Yu-Chen }
2283c9274b6bSCho, Yu-Chen
op_dxb(DisasContext * s,DisasOps * o)2284c9274b6bSCho, Yu-Chen static DisasJumpType op_dxb(DisasContext *s, DisasOps *o)
2285c9274b6bSCho, Yu-Chen {
2286ad75a51eSRichard Henderson gen_helper_dxb(o->out_128, tcg_env, o->in1_128, o->in2_128);
2287c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2288c9274b6bSCho, Yu-Chen }
2289c9274b6bSCho, Yu-Chen
op_ear(DisasContext * s,DisasOps * o)2290c9274b6bSCho, Yu-Chen static DisasJumpType op_ear(DisasContext *s, DisasOps *o)
2291c9274b6bSCho, Yu-Chen {
2292c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
2293ad75a51eSRichard Henderson tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, aregs[r2]));
2294c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2295c9274b6bSCho, Yu-Chen }
2296c9274b6bSCho, Yu-Chen
op_ecag(DisasContext * s,DisasOps * o)2297c9274b6bSCho, Yu-Chen static DisasJumpType op_ecag(DisasContext *s, DisasOps *o)
2298c9274b6bSCho, Yu-Chen {
2299c9274b6bSCho, Yu-Chen /* No cache information provided. */
2300c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(o->out, -1);
2301c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2302c9274b6bSCho, Yu-Chen }
2303c9274b6bSCho, Yu-Chen
op_efpc(DisasContext * s,DisasOps * o)2304c9274b6bSCho, Yu-Chen static DisasJumpType op_efpc(DisasContext *s, DisasOps *o)
2305c9274b6bSCho, Yu-Chen {
2306ad75a51eSRichard Henderson tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, fpc));
2307c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2308c9274b6bSCho, Yu-Chen }
2309c9274b6bSCho, Yu-Chen
op_epsw(DisasContext * s,DisasOps * o)2310c9274b6bSCho, Yu-Chen static DisasJumpType op_epsw(DisasContext *s, DisasOps *o)
2311c9274b6bSCho, Yu-Chen {
2312c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
2313c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
2314c9274b6bSCho, Yu-Chen TCGv_i64 t = tcg_temp_new_i64();
2315110b1bacSIlya Leoshkevich TCGv_i64 t_cc = tcg_temp_new_i64();
2316c9274b6bSCho, Yu-Chen
2317c9274b6bSCho, Yu-Chen /* Note the "subsequently" in the PoO, which implies a defined result
2318c9274b6bSCho, Yu-Chen if r1 == r2. Thus we cannot defer these writes to an output hook. */
2319110b1bacSIlya Leoshkevich gen_op_calc_cc(s);
2320110b1bacSIlya Leoshkevich tcg_gen_extu_i32_i64(t_cc, cc_op);
2321c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(t, psw_mask, 32);
2322110b1bacSIlya Leoshkevich tcg_gen_deposit_i64(t, t, t_cc, 12, 2);
2323c9274b6bSCho, Yu-Chen store_reg32_i64(r1, t);
2324c9274b6bSCho, Yu-Chen if (r2 != 0) {
2325c9274b6bSCho, Yu-Chen store_reg32_i64(r2, psw_mask);
2326c9274b6bSCho, Yu-Chen }
2327c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2328c9274b6bSCho, Yu-Chen }
2329c9274b6bSCho, Yu-Chen
op_ex(DisasContext * s,DisasOps * o)2330c9274b6bSCho, Yu-Chen static DisasJumpType op_ex(DisasContext *s, DisasOps *o)
2331c9274b6bSCho, Yu-Chen {
2332c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
2333c9274b6bSCho, Yu-Chen TCGv_i32 ilen;
2334c9274b6bSCho, Yu-Chen TCGv_i64 v1;
2335c9274b6bSCho, Yu-Chen
2336c9274b6bSCho, Yu-Chen /* Nested EXECUTE is not allowed. */
2337c9274b6bSCho, Yu-Chen if (unlikely(s->ex_value)) {
2338c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_EXECUTE);
2339c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2340c9274b6bSCho, Yu-Chen }
2341c9274b6bSCho, Yu-Chen
2342c9274b6bSCho, Yu-Chen update_psw_addr(s);
2343c9274b6bSCho, Yu-Chen update_cc_op(s);
2344c9274b6bSCho, Yu-Chen
2345c9274b6bSCho, Yu-Chen if (r1 == 0) {
2346f1ea739bSRichard Henderson v1 = tcg_constant_i64(0);
2347c9274b6bSCho, Yu-Chen } else {
2348c9274b6bSCho, Yu-Chen v1 = regs[r1];
2349c9274b6bSCho, Yu-Chen }
2350c9274b6bSCho, Yu-Chen
2351f1ea739bSRichard Henderson ilen = tcg_constant_i32(s->ilen);
2352ad75a51eSRichard Henderson gen_helper_ex(tcg_env, ilen, v1, o->in2);
2353c9274b6bSCho, Yu-Chen
2354c9274b6bSCho, Yu-Chen return DISAS_PC_CC_UPDATED;
2355c9274b6bSCho, Yu-Chen }
2356c9274b6bSCho, Yu-Chen
op_fieb(DisasContext * s,DisasOps * o)2357c9274b6bSCho, Yu-Chen static DisasJumpType op_fieb(DisasContext *s, DisasOps *o)
2358c9274b6bSCho, Yu-Chen {
2359c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
2360c9274b6bSCho, Yu-Chen
2361c9274b6bSCho, Yu-Chen if (!m34) {
2362c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2363c9274b6bSCho, Yu-Chen }
2364ad75a51eSRichard Henderson gen_helper_fieb(o->out, tcg_env, o->in2, m34);
2365c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2366c9274b6bSCho, Yu-Chen }
2367c9274b6bSCho, Yu-Chen
op_fidb(DisasContext * s,DisasOps * o)2368c9274b6bSCho, Yu-Chen static DisasJumpType op_fidb(DisasContext *s, DisasOps *o)
2369c9274b6bSCho, Yu-Chen {
2370c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
2371c9274b6bSCho, Yu-Chen
2372c9274b6bSCho, Yu-Chen if (!m34) {
2373c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2374c9274b6bSCho, Yu-Chen }
2375ad75a51eSRichard Henderson gen_helper_fidb(o->out, tcg_env, o->in2, m34);
2376c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2377c9274b6bSCho, Yu-Chen }
2378c9274b6bSCho, Yu-Chen
op_fixb(DisasContext * s,DisasOps * o)2379c9274b6bSCho, Yu-Chen static DisasJumpType op_fixb(DisasContext *s, DisasOps *o)
2380c9274b6bSCho, Yu-Chen {
2381c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, false, true);
2382c9274b6bSCho, Yu-Chen
2383c9274b6bSCho, Yu-Chen if (!m34) {
2384c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2385c9274b6bSCho, Yu-Chen }
2386ad75a51eSRichard Henderson gen_helper_fixb(o->out_128, tcg_env, o->in2_128, m34);
2387c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2388c9274b6bSCho, Yu-Chen }
2389c9274b6bSCho, Yu-Chen
op_flogr(DisasContext * s,DisasOps * o)2390c9274b6bSCho, Yu-Chen static DisasJumpType op_flogr(DisasContext *s, DisasOps *o)
2391c9274b6bSCho, Yu-Chen {
2392c9274b6bSCho, Yu-Chen /* We'll use the original input for cc computation, since we get to
2393c9274b6bSCho, Yu-Chen compare that against 0, which ought to be better than comparing
2394c9274b6bSCho, Yu-Chen the real output against 64. It also lets cc_dst be a convenient
2395c9274b6bSCho, Yu-Chen temporary during our computation. */
2396c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_FLOGR, o->in2);
2397c9274b6bSCho, Yu-Chen
2398c9274b6bSCho, Yu-Chen /* R1 = IN ? CLZ(IN) : 64. */
2399c9274b6bSCho, Yu-Chen tcg_gen_clzi_i64(o->out, o->in2, 64);
2400c9274b6bSCho, Yu-Chen
2401c9274b6bSCho, Yu-Chen /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2402c9274b6bSCho, Yu-Chen value by 64, which is undefined. But since the shift is 64 iff the
2403c9274b6bSCho, Yu-Chen input is zero, we still get the correct result after and'ing. */
2404c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(o->out2, 0x8000000000000000ull);
2405c9274b6bSCho, Yu-Chen tcg_gen_shr_i64(o->out2, o->out2, o->out);
2406c9274b6bSCho, Yu-Chen tcg_gen_andc_i64(o->out2, cc_dst, o->out2);
2407c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2408c9274b6bSCho, Yu-Chen }
2409c9274b6bSCho, Yu-Chen
op_icm(DisasContext * s,DisasOps * o)2410c9274b6bSCho, Yu-Chen static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
2411c9274b6bSCho, Yu-Chen {
2412c9274b6bSCho, Yu-Chen int m3 = get_field(s, m3);
2413c9274b6bSCho, Yu-Chen int pos, len, base = s->insn->data;
2414c9274b6bSCho, Yu-Chen TCGv_i64 tmp = tcg_temp_new_i64();
2415c9274b6bSCho, Yu-Chen uint64_t ccm;
2416c9274b6bSCho, Yu-Chen
2417c9274b6bSCho, Yu-Chen switch (m3) {
2418c9274b6bSCho, Yu-Chen case 0xf:
2419c9274b6bSCho, Yu-Chen /* Effectively a 32-bit load. */
2420e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
2421c9274b6bSCho, Yu-Chen len = 32;
2422c9274b6bSCho, Yu-Chen goto one_insert;
2423c9274b6bSCho, Yu-Chen
2424c9274b6bSCho, Yu-Chen case 0xc:
2425c9274b6bSCho, Yu-Chen case 0x6:
2426c9274b6bSCho, Yu-Chen case 0x3:
2427c9274b6bSCho, Yu-Chen /* Effectively a 16-bit load. */
2428e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
2429c9274b6bSCho, Yu-Chen len = 16;
2430c9274b6bSCho, Yu-Chen goto one_insert;
2431c9274b6bSCho, Yu-Chen
2432c9274b6bSCho, Yu-Chen case 0x8:
2433c9274b6bSCho, Yu-Chen case 0x4:
2434c9274b6bSCho, Yu-Chen case 0x2:
2435c9274b6bSCho, Yu-Chen case 0x1:
2436c9274b6bSCho, Yu-Chen /* Effectively an 8-bit load. */
2437e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
2438c9274b6bSCho, Yu-Chen len = 8;
2439c9274b6bSCho, Yu-Chen goto one_insert;
2440c9274b6bSCho, Yu-Chen
2441c9274b6bSCho, Yu-Chen one_insert:
2442c9274b6bSCho, Yu-Chen pos = base + ctz32(m3) * 8;
2443c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
2444c9274b6bSCho, Yu-Chen ccm = ((1ull << len) - 1) << pos;
2445c9274b6bSCho, Yu-Chen break;
2446c9274b6bSCho, Yu-Chen
2447a2025557SIlya Leoshkevich case 0:
2448a2025557SIlya Leoshkevich /* Recognize access exceptions for the first byte. */
2449a2025557SIlya Leoshkevich tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
2450a2025557SIlya Leoshkevich gen_op_movi_cc(s, 0);
2451a2025557SIlya Leoshkevich return DISAS_NEXT;
2452a2025557SIlya Leoshkevich
2453c9274b6bSCho, Yu-Chen default:
2454c9274b6bSCho, Yu-Chen /* This is going to be a sequence of loads and inserts. */
2455c9274b6bSCho, Yu-Chen pos = base + 32 - 8;
2456c9274b6bSCho, Yu-Chen ccm = 0;
2457c9274b6bSCho, Yu-Chen while (m3) {
2458c9274b6bSCho, Yu-Chen if (m3 & 0x8) {
2459e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
2460c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->in2, o->in2, 1);
2461c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
246221641ee5SRichard Henderson ccm |= 0xffull << pos;
2463c9274b6bSCho, Yu-Chen }
2464c9274b6bSCho, Yu-Chen m3 = (m3 << 1) & 0xf;
2465c9274b6bSCho, Yu-Chen pos -= 8;
2466c9274b6bSCho, Yu-Chen }
2467c9274b6bSCho, Yu-Chen break;
2468c9274b6bSCho, Yu-Chen }
2469c9274b6bSCho, Yu-Chen
2470c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(tmp, ccm);
2471c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out);
2472c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2473c9274b6bSCho, Yu-Chen }
2474c9274b6bSCho, Yu-Chen
op_insi(DisasContext * s,DisasOps * o)2475c9274b6bSCho, Yu-Chen static DisasJumpType op_insi(DisasContext *s, DisasOps *o)
2476c9274b6bSCho, Yu-Chen {
2477c9274b6bSCho, Yu-Chen int shift = s->insn->data & 0xff;
2478c9274b6bSCho, Yu-Chen int size = s->insn->data >> 8;
2479c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(o->out, o->in1, o->in2, shift, size);
2480c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2481c9274b6bSCho, Yu-Chen }
2482c9274b6bSCho, Yu-Chen
op_ipm(DisasContext * s,DisasOps * o)2483c9274b6bSCho, Yu-Chen static DisasJumpType op_ipm(DisasContext *s, DisasOps *o)
2484c9274b6bSCho, Yu-Chen {
2485c9274b6bSCho, Yu-Chen TCGv_i64 t1, t2;
2486c9274b6bSCho, Yu-Chen
2487c9274b6bSCho, Yu-Chen gen_op_calc_cc(s);
2488c9274b6bSCho, Yu-Chen t1 = tcg_temp_new_i64();
2489c9274b6bSCho, Yu-Chen tcg_gen_extract_i64(t1, psw_mask, 40, 4);
2490c9274b6bSCho, Yu-Chen t2 = tcg_temp_new_i64();
2491c9274b6bSCho, Yu-Chen tcg_gen_extu_i32_i64(t2, cc_op);
2492c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(t1, t1, t2, 4, 60);
2493c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8);
2494c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2495c9274b6bSCho, Yu-Chen }
2496c9274b6bSCho, Yu-Chen
2497c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_idte(DisasContext * s,DisasOps * o)2498c9274b6bSCho, Yu-Chen static DisasJumpType op_idte(DisasContext *s, DisasOps *o)
2499c9274b6bSCho, Yu-Chen {
2500c9274b6bSCho, Yu-Chen TCGv_i32 m4;
2501c9274b6bSCho, Yu-Chen
2502c9274b6bSCho, Yu-Chen if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
2503f1ea739bSRichard Henderson m4 = tcg_constant_i32(get_field(s, m4));
2504c9274b6bSCho, Yu-Chen } else {
2505f1ea739bSRichard Henderson m4 = tcg_constant_i32(0);
2506c9274b6bSCho, Yu-Chen }
2507ad75a51eSRichard Henderson gen_helper_idte(tcg_env, o->in1, o->in2, m4);
2508c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2509c9274b6bSCho, Yu-Chen }
2510c9274b6bSCho, Yu-Chen
op_ipte(DisasContext * s,DisasOps * o)2511c9274b6bSCho, Yu-Chen static DisasJumpType op_ipte(DisasContext *s, DisasOps *o)
2512c9274b6bSCho, Yu-Chen {
2513c9274b6bSCho, Yu-Chen TCGv_i32 m4;
2514c9274b6bSCho, Yu-Chen
2515c9274b6bSCho, Yu-Chen if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
2516f1ea739bSRichard Henderson m4 = tcg_constant_i32(get_field(s, m4));
2517c9274b6bSCho, Yu-Chen } else {
2518f1ea739bSRichard Henderson m4 = tcg_constant_i32(0);
2519c9274b6bSCho, Yu-Chen }
2520ad75a51eSRichard Henderson gen_helper_ipte(tcg_env, o->in1, o->in2, m4);
2521c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2522c9274b6bSCho, Yu-Chen }
2523c9274b6bSCho, Yu-Chen
op_iske(DisasContext * s,DisasOps * o)2524c9274b6bSCho, Yu-Chen static DisasJumpType op_iske(DisasContext *s, DisasOps *o)
2525c9274b6bSCho, Yu-Chen {
2526ad75a51eSRichard Henderson gen_helper_iske(o->out, tcg_env, o->in2);
2527c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2528c9274b6bSCho, Yu-Chen }
2529c9274b6bSCho, Yu-Chen #endif
2530c9274b6bSCho, Yu-Chen
op_msa(DisasContext * s,DisasOps * o)2531c9274b6bSCho, Yu-Chen static DisasJumpType op_msa(DisasContext *s, DisasOps *o)
2532c9274b6bSCho, Yu-Chen {
2533c9274b6bSCho, Yu-Chen int r1 = have_field(s, r1) ? get_field(s, r1) : 0;
2534c9274b6bSCho, Yu-Chen int r2 = have_field(s, r2) ? get_field(s, r2) : 0;
2535c9274b6bSCho, Yu-Chen int r3 = have_field(s, r3) ? get_field(s, r3) : 0;
2536c9274b6bSCho, Yu-Chen TCGv_i32 t_r1, t_r2, t_r3, type;
2537c9274b6bSCho, Yu-Chen
2538c9274b6bSCho, Yu-Chen switch (s->insn->data) {
2539c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KMA:
2540c9274b6bSCho, Yu-Chen if (r3 == r1 || r3 == r2) {
2541c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
2542c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2543c9274b6bSCho, Yu-Chen }
2544c9274b6bSCho, Yu-Chen /* FALL THROUGH */
2545c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KMCTR:
2546c9274b6bSCho, Yu-Chen if (r3 & 1 || !r3) {
2547c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
2548c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2549c9274b6bSCho, Yu-Chen }
2550c9274b6bSCho, Yu-Chen /* FALL THROUGH */
2551c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_PPNO:
2552c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KMF:
2553c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KMC:
2554c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KMO:
2555c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KM:
2556c9274b6bSCho, Yu-Chen if (r1 & 1 || !r1) {
2557c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
2558c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2559c9274b6bSCho, Yu-Chen }
2560c9274b6bSCho, Yu-Chen /* FALL THROUGH */
2561c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KMAC:
2562c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KIMD:
2563c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_KLMD:
2564c9274b6bSCho, Yu-Chen if (r2 & 1 || !r2) {
2565c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
2566c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2567c9274b6bSCho, Yu-Chen }
2568c9274b6bSCho, Yu-Chen /* FALL THROUGH */
2569c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_PCKMO:
2570c9274b6bSCho, Yu-Chen case S390_FEAT_TYPE_PCC:
2571c9274b6bSCho, Yu-Chen break;
2572c9274b6bSCho, Yu-Chen default:
2573c9274b6bSCho, Yu-Chen g_assert_not_reached();
2574c9274b6bSCho, Yu-Chen };
2575c9274b6bSCho, Yu-Chen
2576f1ea739bSRichard Henderson t_r1 = tcg_constant_i32(r1);
2577f1ea739bSRichard Henderson t_r2 = tcg_constant_i32(r2);
2578f1ea739bSRichard Henderson t_r3 = tcg_constant_i32(r3);
2579f1ea739bSRichard Henderson type = tcg_constant_i32(s->insn->data);
2580ad75a51eSRichard Henderson gen_helper_msa(cc_op, tcg_env, t_r1, t_r2, t_r3, type);
2581c9274b6bSCho, Yu-Chen set_cc_static(s);
2582c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2583c9274b6bSCho, Yu-Chen }
2584c9274b6bSCho, Yu-Chen
op_keb(DisasContext * s,DisasOps * o)2585c9274b6bSCho, Yu-Chen static DisasJumpType op_keb(DisasContext *s, DisasOps *o)
2586c9274b6bSCho, Yu-Chen {
2587ad75a51eSRichard Henderson gen_helper_keb(cc_op, tcg_env, o->in1, o->in2);
2588c9274b6bSCho, Yu-Chen set_cc_static(s);
2589c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2590c9274b6bSCho, Yu-Chen }
2591c9274b6bSCho, Yu-Chen
op_kdb(DisasContext * s,DisasOps * o)2592c9274b6bSCho, Yu-Chen static DisasJumpType op_kdb(DisasContext *s, DisasOps *o)
2593c9274b6bSCho, Yu-Chen {
2594ad75a51eSRichard Henderson gen_helper_kdb(cc_op, tcg_env, o->in1, o->in2);
2595c9274b6bSCho, Yu-Chen set_cc_static(s);
2596c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2597c9274b6bSCho, Yu-Chen }
2598c9274b6bSCho, Yu-Chen
op_kxb(DisasContext * s,DisasOps * o)2599c9274b6bSCho, Yu-Chen static DisasJumpType op_kxb(DisasContext *s, DisasOps *o)
2600c9274b6bSCho, Yu-Chen {
2601ad75a51eSRichard Henderson gen_helper_kxb(cc_op, tcg_env, o->in1_128, o->in2_128);
2602c9274b6bSCho, Yu-Chen set_cc_static(s);
2603c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2604c9274b6bSCho, Yu-Chen }
2605c9274b6bSCho, Yu-Chen
help_laa(DisasContext * s,DisasOps * o,bool addu64)2606bea40248SIlya Leoshkevich static DisasJumpType help_laa(DisasContext *s, DisasOps *o, bool addu64)
2607c9274b6bSCho, Yu-Chen {
2608c9274b6bSCho, Yu-Chen /* The real output is indeed the original value in memory;
2609c9274b6bSCho, Yu-Chen recompute the addition for the computation of CC. */
2610c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_add_i64(o->in2, o->in2, o->in1, get_mem_index(s),
2611c9274b6bSCho, Yu-Chen s->insn->data | MO_ALIGN);
2612c9274b6bSCho, Yu-Chen /* However, we need to recompute the addition for setting CC. */
2613bea40248SIlya Leoshkevich if (addu64) {
2614bea40248SIlya Leoshkevich tcg_gen_movi_i64(cc_src, 0);
2615bea40248SIlya Leoshkevich tcg_gen_add2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);
2616bea40248SIlya Leoshkevich } else {
2617c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->out, o->in1, o->in2);
2618bea40248SIlya Leoshkevich }
2619c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2620c9274b6bSCho, Yu-Chen }
2621c9274b6bSCho, Yu-Chen
op_laa(DisasContext * s,DisasOps * o)2622bea40248SIlya Leoshkevich static DisasJumpType op_laa(DisasContext *s, DisasOps *o)
2623bea40248SIlya Leoshkevich {
2624bea40248SIlya Leoshkevich return help_laa(s, o, false);
2625bea40248SIlya Leoshkevich }
2626bea40248SIlya Leoshkevich
op_laa_addu64(DisasContext * s,DisasOps * o)2627bea40248SIlya Leoshkevich static DisasJumpType op_laa_addu64(DisasContext *s, DisasOps *o)
2628bea40248SIlya Leoshkevich {
2629bea40248SIlya Leoshkevich return help_laa(s, o, true);
2630bea40248SIlya Leoshkevich }
2631bea40248SIlya Leoshkevich
op_lan(DisasContext * s,DisasOps * o)2632c9274b6bSCho, Yu-Chen static DisasJumpType op_lan(DisasContext *s, DisasOps *o)
2633c9274b6bSCho, Yu-Chen {
2634c9274b6bSCho, Yu-Chen /* The real output is indeed the original value in memory;
2635c9274b6bSCho, Yu-Chen recompute the addition for the computation of CC. */
2636c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_and_i64(o->in2, o->in2, o->in1, get_mem_index(s),
2637c9274b6bSCho, Yu-Chen s->insn->data | MO_ALIGN);
2638c9274b6bSCho, Yu-Chen /* However, we need to recompute the operation for setting CC. */
2639c9274b6bSCho, Yu-Chen tcg_gen_and_i64(o->out, o->in1, o->in2);
2640c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2641c9274b6bSCho, Yu-Chen }
2642c9274b6bSCho, Yu-Chen
op_lao(DisasContext * s,DisasOps * o)2643c9274b6bSCho, Yu-Chen static DisasJumpType op_lao(DisasContext *s, DisasOps *o)
2644c9274b6bSCho, Yu-Chen {
2645c9274b6bSCho, Yu-Chen /* The real output is indeed the original value in memory;
2646c9274b6bSCho, Yu-Chen recompute the addition for the computation of CC. */
2647c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_or_i64(o->in2, o->in2, o->in1, get_mem_index(s),
2648c9274b6bSCho, Yu-Chen s->insn->data | MO_ALIGN);
2649c9274b6bSCho, Yu-Chen /* However, we need to recompute the operation for setting CC. */
2650c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->in1, o->in2);
2651c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2652c9274b6bSCho, Yu-Chen }
2653c9274b6bSCho, Yu-Chen
op_lax(DisasContext * s,DisasOps * o)2654c9274b6bSCho, Yu-Chen static DisasJumpType op_lax(DisasContext *s, DisasOps *o)
2655c9274b6bSCho, Yu-Chen {
2656c9274b6bSCho, Yu-Chen /* The real output is indeed the original value in memory;
2657c9274b6bSCho, Yu-Chen recompute the addition for the computation of CC. */
2658c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_xor_i64(o->in2, o->in2, o->in1, get_mem_index(s),
2659c9274b6bSCho, Yu-Chen s->insn->data | MO_ALIGN);
2660c9274b6bSCho, Yu-Chen /* However, we need to recompute the operation for setting CC. */
2661c9274b6bSCho, Yu-Chen tcg_gen_xor_i64(o->out, o->in1, o->in2);
2662c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2663c9274b6bSCho, Yu-Chen }
2664c9274b6bSCho, Yu-Chen
op_ldeb(DisasContext * s,DisasOps * o)2665c9274b6bSCho, Yu-Chen static DisasJumpType op_ldeb(DisasContext *s, DisasOps *o)
2666c9274b6bSCho, Yu-Chen {
2667ad75a51eSRichard Henderson gen_helper_ldeb(o->out, tcg_env, o->in2);
2668c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2669c9274b6bSCho, Yu-Chen }
2670c9274b6bSCho, Yu-Chen
op_ledb(DisasContext * s,DisasOps * o)2671c9274b6bSCho, Yu-Chen static DisasJumpType op_ledb(DisasContext *s, DisasOps *o)
2672c9274b6bSCho, Yu-Chen {
2673c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, true, true);
2674c9274b6bSCho, Yu-Chen
2675c9274b6bSCho, Yu-Chen if (!m34) {
2676c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2677c9274b6bSCho, Yu-Chen }
2678ad75a51eSRichard Henderson gen_helper_ledb(o->out, tcg_env, o->in2, m34);
2679c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2680c9274b6bSCho, Yu-Chen }
2681c9274b6bSCho, Yu-Chen
op_ldxb(DisasContext * s,DisasOps * o)2682c9274b6bSCho, Yu-Chen static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o)
2683c9274b6bSCho, Yu-Chen {
2684c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, true, true);
2685c9274b6bSCho, Yu-Chen
2686c9274b6bSCho, Yu-Chen if (!m34) {
2687c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2688c9274b6bSCho, Yu-Chen }
2689ad75a51eSRichard Henderson gen_helper_ldxb(o->out, tcg_env, o->in2_128, m34);
2690c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2691c9274b6bSCho, Yu-Chen }
2692c9274b6bSCho, Yu-Chen
op_lexb(DisasContext * s,DisasOps * o)2693c9274b6bSCho, Yu-Chen static DisasJumpType op_lexb(DisasContext *s, DisasOps *o)
2694c9274b6bSCho, Yu-Chen {
2695c9274b6bSCho, Yu-Chen TCGv_i32 m34 = fpinst_extract_m34(s, true, true);
2696c9274b6bSCho, Yu-Chen
2697c9274b6bSCho, Yu-Chen if (!m34) {
2698c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2699c9274b6bSCho, Yu-Chen }
2700ad75a51eSRichard Henderson gen_helper_lexb(o->out, tcg_env, o->in2_128, m34);
2701c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2702c9274b6bSCho, Yu-Chen }
2703c9274b6bSCho, Yu-Chen
op_lxdb(DisasContext * s,DisasOps * o)2704c9274b6bSCho, Yu-Chen static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o)
2705c9274b6bSCho, Yu-Chen {
2706ad75a51eSRichard Henderson gen_helper_lxdb(o->out_128, tcg_env, o->in2);
2707c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2708c9274b6bSCho, Yu-Chen }
2709c9274b6bSCho, Yu-Chen
op_lxeb(DisasContext * s,DisasOps * o)2710c9274b6bSCho, Yu-Chen static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o)
2711c9274b6bSCho, Yu-Chen {
2712ad75a51eSRichard Henderson gen_helper_lxeb(o->out_128, tcg_env, o->in2);
2713c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2714c9274b6bSCho, Yu-Chen }
2715c9274b6bSCho, Yu-Chen
op_lde(DisasContext * s,DisasOps * o)2716c9274b6bSCho, Yu-Chen static DisasJumpType op_lde(DisasContext *s, DisasOps *o)
2717c9274b6bSCho, Yu-Chen {
2718c9274b6bSCho, Yu-Chen tcg_gen_shli_i64(o->out, o->in2, 32);
2719c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2720c9274b6bSCho, Yu-Chen }
2721c9274b6bSCho, Yu-Chen
op_llgt(DisasContext * s,DisasOps * o)2722c9274b6bSCho, Yu-Chen static DisasJumpType op_llgt(DisasContext *s, DisasOps *o)
2723c9274b6bSCho, Yu-Chen {
2724c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2725c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2726c9274b6bSCho, Yu-Chen }
2727c9274b6bSCho, Yu-Chen
op_ld8s(DisasContext * s,DisasOps * o)2728c9274b6bSCho, Yu-Chen static DisasJumpType op_ld8s(DisasContext *s, DisasOps *o)
2729c9274b6bSCho, Yu-Chen {
2730e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB);
2731c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2732c9274b6bSCho, Yu-Chen }
2733c9274b6bSCho, Yu-Chen
op_ld8u(DisasContext * s,DisasOps * o)2734c9274b6bSCho, Yu-Chen static DisasJumpType op_ld8u(DisasContext *s, DisasOps *o)
2735c9274b6bSCho, Yu-Chen {
2736e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB);
2737c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2738c9274b6bSCho, Yu-Chen }
2739c9274b6bSCho, Yu-Chen
op_ld16s(DisasContext * s,DisasOps * o)2740c9274b6bSCho, Yu-Chen static DisasJumpType op_ld16s(DisasContext *s, DisasOps *o)
2741c9274b6bSCho, Yu-Chen {
2742e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TESW);
2743c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2744c9274b6bSCho, Yu-Chen }
2745c9274b6bSCho, Yu-Chen
op_ld16u(DisasContext * s,DisasOps * o)2746c9274b6bSCho, Yu-Chen static DisasJumpType op_ld16u(DisasContext *s, DisasOps *o)
2747c9274b6bSCho, Yu-Chen {
2748e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUW);
2749c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2750c9274b6bSCho, Yu-Chen }
2751c9274b6bSCho, Yu-Chen
op_ld32s(DisasContext * s,DisasOps * o)2752c9274b6bSCho, Yu-Chen static DisasJumpType op_ld32s(DisasContext *s, DisasOps *o)
2753c9274b6bSCho, Yu-Chen {
2754e6d70c82SIlya Leoshkevich tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
2755e6d70c82SIlya Leoshkevich MO_TESL | s->insn->data);
2756c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2757c9274b6bSCho, Yu-Chen }
2758c9274b6bSCho, Yu-Chen
op_ld32u(DisasContext * s,DisasOps * o)2759c9274b6bSCho, Yu-Chen static DisasJumpType op_ld32u(DisasContext *s, DisasOps *o)
2760c9274b6bSCho, Yu-Chen {
27614942e4ccSIlya Leoshkevich tcg_gen_qemu_ld_tl(o->out, o->in2, get_mem_index(s),
27624942e4ccSIlya Leoshkevich MO_TEUL | s->insn->data);
2763c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2764c9274b6bSCho, Yu-Chen }
2765c9274b6bSCho, Yu-Chen
op_ld64(DisasContext * s,DisasOps * o)2766c9274b6bSCho, Yu-Chen static DisasJumpType op_ld64(DisasContext *s, DisasOps *o)
2767c9274b6bSCho, Yu-Chen {
27682a00d55dSIlya Leoshkevich tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s),
27692a00d55dSIlya Leoshkevich MO_TEUQ | s->insn->data);
2770c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2771c9274b6bSCho, Yu-Chen }
2772c9274b6bSCho, Yu-Chen
op_lat(DisasContext * s,DisasOps * o)2773c9274b6bSCho, Yu-Chen static DisasJumpType op_lat(DisasContext *s, DisasOps *o)
2774c9274b6bSCho, Yu-Chen {
2775c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2776c9274b6bSCho, Yu-Chen store_reg32_i64(get_field(s, r1), o->in2);
2777c9274b6bSCho, Yu-Chen /* The value is stored even in case of trap. */
2778c9274b6bSCho, Yu-Chen tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab);
2779c9274b6bSCho, Yu-Chen gen_trap(s);
2780c9274b6bSCho, Yu-Chen gen_set_label(lab);
2781c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2782c9274b6bSCho, Yu-Chen }
2783c9274b6bSCho, Yu-Chen
op_lgat(DisasContext * s,DisasOps * o)2784c9274b6bSCho, Yu-Chen static DisasJumpType op_lgat(DisasContext *s, DisasOps *o)
2785c9274b6bSCho, Yu-Chen {
2786c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2787e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUQ);
2788c9274b6bSCho, Yu-Chen /* The value is stored even in case of trap. */
2789c9274b6bSCho, Yu-Chen tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
2790c9274b6bSCho, Yu-Chen gen_trap(s);
2791c9274b6bSCho, Yu-Chen gen_set_label(lab);
2792c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2793c9274b6bSCho, Yu-Chen }
2794c9274b6bSCho, Yu-Chen
op_lfhat(DisasContext * s,DisasOps * o)2795c9274b6bSCho, Yu-Chen static DisasJumpType op_lfhat(DisasContext *s, DisasOps *o)
2796c9274b6bSCho, Yu-Chen {
2797c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2798c9274b6bSCho, Yu-Chen store_reg32h_i64(get_field(s, r1), o->in2);
2799c9274b6bSCho, Yu-Chen /* The value is stored even in case of trap. */
2800c9274b6bSCho, Yu-Chen tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab);
2801c9274b6bSCho, Yu-Chen gen_trap(s);
2802c9274b6bSCho, Yu-Chen gen_set_label(lab);
2803c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2804c9274b6bSCho, Yu-Chen }
2805c9274b6bSCho, Yu-Chen
op_llgfat(DisasContext * s,DisasOps * o)2806c9274b6bSCho, Yu-Chen static DisasJumpType op_llgfat(DisasContext *s, DisasOps *o)
2807c9274b6bSCho, Yu-Chen {
2808c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2809e87027d0SRichard Henderson
2810e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
2811c9274b6bSCho, Yu-Chen /* The value is stored even in case of trap. */
2812c9274b6bSCho, Yu-Chen tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
2813c9274b6bSCho, Yu-Chen gen_trap(s);
2814c9274b6bSCho, Yu-Chen gen_set_label(lab);
2815c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2816c9274b6bSCho, Yu-Chen }
2817c9274b6bSCho, Yu-Chen
op_llgtat(DisasContext * s,DisasOps * o)2818c9274b6bSCho, Yu-Chen static DisasJumpType op_llgtat(DisasContext *s, DisasOps *o)
2819c9274b6bSCho, Yu-Chen {
2820c9274b6bSCho, Yu-Chen TCGLabel *lab = gen_new_label();
2821c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, 0x7fffffff);
2822c9274b6bSCho, Yu-Chen /* The value is stored even in case of trap. */
2823c9274b6bSCho, Yu-Chen tcg_gen_brcondi_i64(TCG_COND_NE, o->out, 0, lab);
2824c9274b6bSCho, Yu-Chen gen_trap(s);
2825c9274b6bSCho, Yu-Chen gen_set_label(lab);
2826c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2827c9274b6bSCho, Yu-Chen }
2828c9274b6bSCho, Yu-Chen
op_loc(DisasContext * s,DisasOps * o)2829c9274b6bSCho, Yu-Chen static DisasJumpType op_loc(DisasContext *s, DisasOps *o)
2830c9274b6bSCho, Yu-Chen {
2831c9274b6bSCho, Yu-Chen DisasCompare c;
2832c9274b6bSCho, Yu-Chen
2833ea0a1053SDavid Miller if (have_field(s, m3)) {
2834ea0a1053SDavid Miller /* LOAD * ON CONDITION */
2835c9274b6bSCho, Yu-Chen disas_jcc(s, &c, get_field(s, m3));
2836ea0a1053SDavid Miller } else {
2837ea0a1053SDavid Miller /* SELECT */
2838ea0a1053SDavid Miller disas_jcc(s, &c, get_field(s, m4));
2839ea0a1053SDavid Miller }
2840c9274b6bSCho, Yu-Chen
2841c9274b6bSCho, Yu-Chen if (c.is_64) {
2842c9274b6bSCho, Yu-Chen tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
2843c9274b6bSCho, Yu-Chen o->in2, o->in1);
2844c9274b6bSCho, Yu-Chen } else {
2845c9274b6bSCho, Yu-Chen TCGv_i32 t32 = tcg_temp_new_i32();
2846c9274b6bSCho, Yu-Chen TCGv_i64 t, z;
2847c9274b6bSCho, Yu-Chen
2848c9274b6bSCho, Yu-Chen tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b);
2849c9274b6bSCho, Yu-Chen
2850c9274b6bSCho, Yu-Chen t = tcg_temp_new_i64();
2851c9274b6bSCho, Yu-Chen tcg_gen_extu_i32_i64(t, t32);
2852c9274b6bSCho, Yu-Chen
2853f1ea739bSRichard Henderson z = tcg_constant_i64(0);
2854c9274b6bSCho, Yu-Chen tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1);
2855c9274b6bSCho, Yu-Chen }
2856c9274b6bSCho, Yu-Chen
2857c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2858c9274b6bSCho, Yu-Chen }
2859c9274b6bSCho, Yu-Chen
2860c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_lctl(DisasContext * s,DisasOps * o)2861c9274b6bSCho, Yu-Chen static DisasJumpType op_lctl(DisasContext *s, DisasOps *o)
2862c9274b6bSCho, Yu-Chen {
2863f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
2864f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
2865f1ea739bSRichard Henderson
2866ad75a51eSRichard Henderson gen_helper_lctl(tcg_env, r1, o->in2, r3);
2867c9274b6bSCho, Yu-Chen /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
2868872e1379SRichard Henderson s->exit_to_mainloop = true;
2869872e1379SRichard Henderson return DISAS_TOO_MANY;
2870c9274b6bSCho, Yu-Chen }
2871c9274b6bSCho, Yu-Chen
op_lctlg(DisasContext * s,DisasOps * o)2872c9274b6bSCho, Yu-Chen static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o)
2873c9274b6bSCho, Yu-Chen {
2874f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
2875f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
2876f1ea739bSRichard Henderson
2877ad75a51eSRichard Henderson gen_helper_lctlg(tcg_env, r1, o->in2, r3);
2878c9274b6bSCho, Yu-Chen /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
2879872e1379SRichard Henderson s->exit_to_mainloop = true;
2880872e1379SRichard Henderson return DISAS_TOO_MANY;
2881c9274b6bSCho, Yu-Chen }
2882c9274b6bSCho, Yu-Chen
op_lra(DisasContext * s,DisasOps * o)2883c9274b6bSCho, Yu-Chen static DisasJumpType op_lra(DisasContext *s, DisasOps *o)
2884c9274b6bSCho, Yu-Chen {
2885ad75a51eSRichard Henderson gen_helper_lra(o->out, tcg_env, o->out, o->in2);
2886c9274b6bSCho, Yu-Chen set_cc_static(s);
2887c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2888c9274b6bSCho, Yu-Chen }
2889c9274b6bSCho, Yu-Chen
op_lpp(DisasContext * s,DisasOps * o)2890c9274b6bSCho, Yu-Chen static DisasJumpType op_lpp(DisasContext *s, DisasOps *o)
2891c9274b6bSCho, Yu-Chen {
2892ad75a51eSRichard Henderson tcg_gen_st_i64(o->in2, tcg_env, offsetof(CPUS390XState, pp));
2893c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2894c9274b6bSCho, Yu-Chen }
2895c9274b6bSCho, Yu-Chen
op_lpsw(DisasContext * s,DisasOps * o)2896c9274b6bSCho, Yu-Chen static DisasJumpType op_lpsw(DisasContext *s, DisasOps *o)
2897c9274b6bSCho, Yu-Chen {
2898377dc84eSIlya Leoshkevich TCGv_i64 mask, addr;
2899c9274b6bSCho, Yu-Chen
2900c9274b6bSCho, Yu-Chen per_breaking_event(s);
2901c9274b6bSCho, Yu-Chen
2902377dc84eSIlya Leoshkevich /*
2903377dc84eSIlya Leoshkevich * Convert the short PSW into the normal PSW, similar to what
2904377dc84eSIlya Leoshkevich * s390_cpu_load_normal() does.
2905377dc84eSIlya Leoshkevich */
2906377dc84eSIlya Leoshkevich mask = tcg_temp_new_i64();
2907377dc84eSIlya Leoshkevich addr = tcg_temp_new_i64();
2908377dc84eSIlya Leoshkevich tcg_gen_qemu_ld_i64(mask, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN_8);
2909377dc84eSIlya Leoshkevich tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR);
2910377dc84eSIlya Leoshkevich tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL);
2911377dc84eSIlya Leoshkevich tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW);
2912ad75a51eSRichard Henderson gen_helper_load_psw(tcg_env, mask, addr);
2913c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2914c9274b6bSCho, Yu-Chen }
2915c9274b6bSCho, Yu-Chen
op_lpswe(DisasContext * s,DisasOps * o)2916c9274b6bSCho, Yu-Chen static DisasJumpType op_lpswe(DisasContext *s, DisasOps *o)
2917c9274b6bSCho, Yu-Chen {
2918c9274b6bSCho, Yu-Chen TCGv_i64 t1, t2;
2919c9274b6bSCho, Yu-Chen
2920c9274b6bSCho, Yu-Chen per_breaking_event(s);
2921c9274b6bSCho, Yu-Chen
2922c9274b6bSCho, Yu-Chen t1 = tcg_temp_new_i64();
2923c9274b6bSCho, Yu-Chen t2 = tcg_temp_new_i64();
2924c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s),
2925fc313c64SFrédéric Pétrot MO_TEUQ | MO_ALIGN_8);
2926c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->in2, o->in2, 8);
2927e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ);
2928ad75a51eSRichard Henderson gen_helper_load_psw(tcg_env, t1, t2);
2929c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
2930c9274b6bSCho, Yu-Chen }
2931c9274b6bSCho, Yu-Chen #endif
2932c9274b6bSCho, Yu-Chen
op_lam(DisasContext * s,DisasOps * o)2933c9274b6bSCho, Yu-Chen static DisasJumpType op_lam(DisasContext *s, DisasOps *o)
2934c9274b6bSCho, Yu-Chen {
2935f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
2936f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
2937f1ea739bSRichard Henderson
2938ad75a51eSRichard Henderson gen_helper_lam(tcg_env, r1, o->in2, r3);
2939c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2940c9274b6bSCho, Yu-Chen }
2941c9274b6bSCho, Yu-Chen
op_lm32(DisasContext * s,DisasOps * o)2942c9274b6bSCho, Yu-Chen static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
2943c9274b6bSCho, Yu-Chen {
2944c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
2945c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
2946c9274b6bSCho, Yu-Chen TCGv_i64 t1, t2;
2947c9274b6bSCho, Yu-Chen
2948c9274b6bSCho, Yu-Chen /* Only one register to read. */
2949c9274b6bSCho, Yu-Chen t1 = tcg_temp_new_i64();
2950c9274b6bSCho, Yu-Chen if (unlikely(r1 == r3)) {
2951e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
2952c9274b6bSCho, Yu-Chen store_reg32_i64(r1, t1);
2953c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2954c9274b6bSCho, Yu-Chen }
2955c9274b6bSCho, Yu-Chen
2956c9274b6bSCho, Yu-Chen /* First load the values of the first and last registers to trigger
2957c9274b6bSCho, Yu-Chen possible page faults. */
2958c9274b6bSCho, Yu-Chen t2 = tcg_temp_new_i64();
2959e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
2960c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
2961e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
2962c9274b6bSCho, Yu-Chen store_reg32_i64(r1, t1);
2963c9274b6bSCho, Yu-Chen store_reg32_i64(r3, t2);
2964c9274b6bSCho, Yu-Chen
2965c9274b6bSCho, Yu-Chen /* Only two registers to read. */
2966c9274b6bSCho, Yu-Chen if (((r1 + 1) & 15) == r3) {
2967c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2968c9274b6bSCho, Yu-Chen }
2969c9274b6bSCho, Yu-Chen
2970c9274b6bSCho, Yu-Chen /* Then load the remaining registers. Page fault can't occur. */
2971c9274b6bSCho, Yu-Chen r3 = (r3 - 1) & 15;
2972c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(t2, 4);
2973c9274b6bSCho, Yu-Chen while (r1 != r3) {
2974c9274b6bSCho, Yu-Chen r1 = (r1 + 1) & 15;
2975c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->in2, o->in2, t2);
2976e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
2977c9274b6bSCho, Yu-Chen store_reg32_i64(r1, t1);
2978c9274b6bSCho, Yu-Chen }
2979c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2980c9274b6bSCho, Yu-Chen }
2981c9274b6bSCho, Yu-Chen
op_lmh(DisasContext * s,DisasOps * o)2982c9274b6bSCho, Yu-Chen static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
2983c9274b6bSCho, Yu-Chen {
2984c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
2985c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
2986c9274b6bSCho, Yu-Chen TCGv_i64 t1, t2;
2987c9274b6bSCho, Yu-Chen
2988c9274b6bSCho, Yu-Chen /* Only one register to read. */
2989c9274b6bSCho, Yu-Chen t1 = tcg_temp_new_i64();
2990c9274b6bSCho, Yu-Chen if (unlikely(r1 == r3)) {
2991e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
2992c9274b6bSCho, Yu-Chen store_reg32h_i64(r1, t1);
2993c9274b6bSCho, Yu-Chen return DISAS_NEXT;
2994c9274b6bSCho, Yu-Chen }
2995c9274b6bSCho, Yu-Chen
2996c9274b6bSCho, Yu-Chen /* First load the values of the first and last registers to trigger
2997c9274b6bSCho, Yu-Chen possible page faults. */
2998c9274b6bSCho, Yu-Chen t2 = tcg_temp_new_i64();
2999e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
3000c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(t2, o->in2, 4 * ((r3 - r1) & 15));
3001e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t2, t2, get_mem_index(s), MO_TEUL);
3002c9274b6bSCho, Yu-Chen store_reg32h_i64(r1, t1);
3003c9274b6bSCho, Yu-Chen store_reg32h_i64(r3, t2);
3004c9274b6bSCho, Yu-Chen
3005c9274b6bSCho, Yu-Chen /* Only two registers to read. */
3006c9274b6bSCho, Yu-Chen if (((r1 + 1) & 15) == r3) {
3007c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3008c9274b6bSCho, Yu-Chen }
3009c9274b6bSCho, Yu-Chen
3010c9274b6bSCho, Yu-Chen /* Then load the remaining registers. Page fault can't occur. */
3011c9274b6bSCho, Yu-Chen r3 = (r3 - 1) & 15;
3012c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(t2, 4);
3013c9274b6bSCho, Yu-Chen while (r1 != r3) {
3014c9274b6bSCho, Yu-Chen r1 = (r1 + 1) & 15;
3015c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->in2, o->in2, t2);
3016e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUL);
3017c9274b6bSCho, Yu-Chen store_reg32h_i64(r1, t1);
3018c9274b6bSCho, Yu-Chen }
3019c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3020c9274b6bSCho, Yu-Chen }
3021c9274b6bSCho, Yu-Chen
op_lm64(DisasContext * s,DisasOps * o)3022c9274b6bSCho, Yu-Chen static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
3023c9274b6bSCho, Yu-Chen {
3024c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
3025c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
3026c9274b6bSCho, Yu-Chen TCGv_i64 t1, t2;
3027c9274b6bSCho, Yu-Chen
3028c9274b6bSCho, Yu-Chen /* Only one register to read. */
3029c9274b6bSCho, Yu-Chen if (unlikely(r1 == r3)) {
3030e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
3031c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3032c9274b6bSCho, Yu-Chen }
3033c9274b6bSCho, Yu-Chen
3034c9274b6bSCho, Yu-Chen /* First load the values of the first and last registers to trigger
3035c9274b6bSCho, Yu-Chen possible page faults. */
3036c9274b6bSCho, Yu-Chen t1 = tcg_temp_new_i64();
3037c9274b6bSCho, Yu-Chen t2 = tcg_temp_new_i64();
3038e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_TEUQ);
3039c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15));
3040e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(regs[r3], t2, get_mem_index(s), MO_TEUQ);
3041c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(regs[r1], t1);
3042c9274b6bSCho, Yu-Chen
3043c9274b6bSCho, Yu-Chen /* Only two registers to read. */
3044c9274b6bSCho, Yu-Chen if (((r1 + 1) & 15) == r3) {
3045c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3046c9274b6bSCho, Yu-Chen }
3047c9274b6bSCho, Yu-Chen
3048c9274b6bSCho, Yu-Chen /* Then load the remaining registers. Page fault can't occur. */
3049c9274b6bSCho, Yu-Chen r3 = (r3 - 1) & 15;
3050c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(t1, 8);
3051c9274b6bSCho, Yu-Chen while (r1 != r3) {
3052c9274b6bSCho, Yu-Chen r1 = (r1 + 1) & 15;
3053c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->in2, o->in2, t1);
3054e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_TEUQ);
3055c9274b6bSCho, Yu-Chen }
3056c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3057c9274b6bSCho, Yu-Chen }
3058c9274b6bSCho, Yu-Chen
op_lpd(DisasContext * s,DisasOps * o)3059c9274b6bSCho, Yu-Chen static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
3060c9274b6bSCho, Yu-Chen {
3061c9274b6bSCho, Yu-Chen TCGv_i64 a1, a2;
3062c9274b6bSCho, Yu-Chen MemOp mop = s->insn->data;
3063c9274b6bSCho, Yu-Chen
3064c9274b6bSCho, Yu-Chen /* In a parallel context, stop the world and single step. */
3065c9274b6bSCho, Yu-Chen if (tb_cflags(s->base.tb) & CF_PARALLEL) {
3066c9274b6bSCho, Yu-Chen update_psw_addr(s);
3067c9274b6bSCho, Yu-Chen update_cc_op(s);
3068c9274b6bSCho, Yu-Chen gen_exception(EXCP_ATOMIC);
3069c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3070c9274b6bSCho, Yu-Chen }
3071c9274b6bSCho, Yu-Chen
3072c9274b6bSCho, Yu-Chen /* In a serial context, perform the two loads ... */
3073c9274b6bSCho, Yu-Chen a1 = get_address(s, 0, get_field(s, b1), get_field(s, d1));
3074c9274b6bSCho, Yu-Chen a2 = get_address(s, 0, get_field(s, b2), get_field(s, d2));
3075c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN);
3076c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN);
3077c9274b6bSCho, Yu-Chen
3078c9274b6bSCho, Yu-Chen /* ... and indicate that we performed them while interlocked. */
3079c9274b6bSCho, Yu-Chen gen_op_movi_cc(s, 0);
3080c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3081c9274b6bSCho, Yu-Chen }
3082c9274b6bSCho, Yu-Chen
op_lpq(DisasContext * s,DisasOps * o)3083c9274b6bSCho, Yu-Chen static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
3084c9274b6bSCho, Yu-Chen {
3085d54a20b9SRichard Henderson o->out_128 = tcg_temp_new_i128();
3086d54a20b9SRichard Henderson tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s),
3087d54a20b9SRichard Henderson MO_TE | MO_128 | MO_ALIGN);
3088c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3089c9274b6bSCho, Yu-Chen }
3090c9274b6bSCho, Yu-Chen
3091c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_lura(DisasContext * s,DisasOps * o)3092c9274b6bSCho, Yu-Chen static DisasJumpType op_lura(DisasContext *s, DisasOps *o)
3093c9274b6bSCho, Yu-Chen {
3094c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->out, o->in2, MMU_REAL_IDX, s->insn->data);
3095c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3096c9274b6bSCho, Yu-Chen }
3097c9274b6bSCho, Yu-Chen #endif
3098c9274b6bSCho, Yu-Chen
op_lzrb(DisasContext * s,DisasOps * o)3099c9274b6bSCho, Yu-Chen static DisasJumpType op_lzrb(DisasContext *s, DisasOps *o)
3100c9274b6bSCho, Yu-Chen {
3101c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, -256);
3102c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3103c9274b6bSCho, Yu-Chen }
3104c9274b6bSCho, Yu-Chen
op_lcbb(DisasContext * s,DisasOps * o)3105c9274b6bSCho, Yu-Chen static DisasJumpType op_lcbb(DisasContext *s, DisasOps *o)
3106c9274b6bSCho, Yu-Chen {
3107c9274b6bSCho, Yu-Chen const int64_t block_size = (1ull << (get_field(s, m3) + 6));
3108c9274b6bSCho, Yu-Chen
3109c9274b6bSCho, Yu-Chen if (get_field(s, m3) > 6) {
3110c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3111c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3112c9274b6bSCho, Yu-Chen }
3113c9274b6bSCho, Yu-Chen
3114c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(o->addr1, o->addr1, -block_size);
3115c9274b6bSCho, Yu-Chen tcg_gen_neg_i64(o->addr1, o->addr1);
3116c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(o->out, 16);
3117c9274b6bSCho, Yu-Chen tcg_gen_umin_i64(o->out, o->out, o->addr1);
3118c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_LCBB, o->out);
3119c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3120c9274b6bSCho, Yu-Chen }
3121c9274b6bSCho, Yu-Chen
op_mc(DisasContext * s,DisasOps * o)3122c9274b6bSCho, Yu-Chen static DisasJumpType op_mc(DisasContext *s, DisasOps *o)
3123c9274b6bSCho, Yu-Chen {
31249c028c05SIlya Leoshkevich const uint8_t monitor_class = get_field(s, i2);
3125c9274b6bSCho, Yu-Chen
31269c028c05SIlya Leoshkevich if (monitor_class & 0xf0) {
3127c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3128c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3129c9274b6bSCho, Yu-Chen }
3130c9274b6bSCho, Yu-Chen
3131c9274b6bSCho, Yu-Chen #if !defined(CONFIG_USER_ONLY)
3132ad75a51eSRichard Henderson gen_helper_monitor_call(tcg_env, o->addr1,
3133f1ea739bSRichard Henderson tcg_constant_i32(monitor_class));
3134c9274b6bSCho, Yu-Chen #endif
3135c9274b6bSCho, Yu-Chen /* Defaults to a NOP. */
3136c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3137c9274b6bSCho, Yu-Chen }
3138c9274b6bSCho, Yu-Chen
op_mov2(DisasContext * s,DisasOps * o)3139c9274b6bSCho, Yu-Chen static DisasJumpType op_mov2(DisasContext *s, DisasOps *o)
3140c9274b6bSCho, Yu-Chen {
3141c9274b6bSCho, Yu-Chen o->out = o->in2;
3142c9274b6bSCho, Yu-Chen o->in2 = NULL;
3143c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3144c9274b6bSCho, Yu-Chen }
3145c9274b6bSCho, Yu-Chen
op_mov2e(DisasContext * s,DisasOps * o)3146c9274b6bSCho, Yu-Chen static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
3147c9274b6bSCho, Yu-Chen {
3148c9274b6bSCho, Yu-Chen int b2 = get_field(s, b2);
3149c9274b6bSCho, Yu-Chen TCGv ar1 = tcg_temp_new_i64();
3150e358a25aSIlya Leoshkevich int r1 = get_field(s, r1);
3151c9274b6bSCho, Yu-Chen
3152c9274b6bSCho, Yu-Chen o->out = o->in2;
3153c9274b6bSCho, Yu-Chen o->in2 = NULL;
3154c9274b6bSCho, Yu-Chen
3155c9274b6bSCho, Yu-Chen switch (s->base.tb->flags & FLAG_MASK_ASC) {
3156c9274b6bSCho, Yu-Chen case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
3157c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(ar1, 0);
3158c9274b6bSCho, Yu-Chen break;
3159c9274b6bSCho, Yu-Chen case PSW_ASC_ACCREG >> FLAG_MASK_PSW_SHIFT:
3160c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(ar1, 1);
3161c9274b6bSCho, Yu-Chen break;
3162c9274b6bSCho, Yu-Chen case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
3163c9274b6bSCho, Yu-Chen if (b2) {
3164ad75a51eSRichard Henderson tcg_gen_ld32u_i64(ar1, tcg_env, offsetof(CPUS390XState, aregs[b2]));
3165c9274b6bSCho, Yu-Chen } else {
3166c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(ar1, 0);
3167c9274b6bSCho, Yu-Chen }
3168c9274b6bSCho, Yu-Chen break;
3169c9274b6bSCho, Yu-Chen case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
3170c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(ar1, 2);
3171c9274b6bSCho, Yu-Chen break;
3172c9274b6bSCho, Yu-Chen }
3173c9274b6bSCho, Yu-Chen
3174e358a25aSIlya Leoshkevich tcg_gen_st32_i64(ar1, tcg_env, offsetof(CPUS390XState, aregs[r1]));
3175c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3176c9274b6bSCho, Yu-Chen }
3177c9274b6bSCho, Yu-Chen
op_movx(DisasContext * s,DisasOps * o)3178c9274b6bSCho, Yu-Chen static DisasJumpType op_movx(DisasContext *s, DisasOps *o)
3179c9274b6bSCho, Yu-Chen {
3180c9274b6bSCho, Yu-Chen o->out = o->in1;
3181c9274b6bSCho, Yu-Chen o->out2 = o->in2;
3182c9274b6bSCho, Yu-Chen o->in1 = NULL;
3183c9274b6bSCho, Yu-Chen o->in2 = NULL;
3184c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3185c9274b6bSCho, Yu-Chen }
3186c9274b6bSCho, Yu-Chen
op_mvc(DisasContext * s,DisasOps * o)3187c9274b6bSCho, Yu-Chen static DisasJumpType op_mvc(DisasContext *s, DisasOps *o)
3188c9274b6bSCho, Yu-Chen {
3189f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3190f1ea739bSRichard Henderson
3191ad75a51eSRichard Henderson gen_helper_mvc(tcg_env, l, o->addr1, o->in2);
3192c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3193c9274b6bSCho, Yu-Chen }
3194c9274b6bSCho, Yu-Chen
op_mvcrl(DisasContext * s,DisasOps * o)3195ea0a1053SDavid Miller static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o)
3196ea0a1053SDavid Miller {
3197ad75a51eSRichard Henderson gen_helper_mvcrl(tcg_env, regs[0], o->addr1, o->in2);
3198ea0a1053SDavid Miller return DISAS_NEXT;
3199ea0a1053SDavid Miller }
3200ea0a1053SDavid Miller
op_mvcin(DisasContext * s,DisasOps * o)3201c9274b6bSCho, Yu-Chen static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o)
3202c9274b6bSCho, Yu-Chen {
3203f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3204f1ea739bSRichard Henderson
3205ad75a51eSRichard Henderson gen_helper_mvcin(tcg_env, l, o->addr1, o->in2);
3206c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3207c9274b6bSCho, Yu-Chen }
3208c9274b6bSCho, Yu-Chen
op_mvcl(DisasContext * s,DisasOps * o)3209c9274b6bSCho, Yu-Chen static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o)
3210c9274b6bSCho, Yu-Chen {
3211c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
3212c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
3213c9274b6bSCho, Yu-Chen TCGv_i32 t1, t2;
3214c9274b6bSCho, Yu-Chen
3215c9274b6bSCho, Yu-Chen /* r1 and r2 must be even. */
3216c9274b6bSCho, Yu-Chen if (r1 & 1 || r2 & 1) {
3217c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3218c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3219c9274b6bSCho, Yu-Chen }
3220c9274b6bSCho, Yu-Chen
3221f1ea739bSRichard Henderson t1 = tcg_constant_i32(r1);
3222f1ea739bSRichard Henderson t2 = tcg_constant_i32(r2);
3223ad75a51eSRichard Henderson gen_helper_mvcl(cc_op, tcg_env, t1, t2);
3224c9274b6bSCho, Yu-Chen set_cc_static(s);
3225c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3226c9274b6bSCho, Yu-Chen }
3227c9274b6bSCho, Yu-Chen
op_mvcle(DisasContext * s,DisasOps * o)3228c9274b6bSCho, Yu-Chen static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o)
3229c9274b6bSCho, Yu-Chen {
3230c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
3231c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
3232c9274b6bSCho, Yu-Chen TCGv_i32 t1, t3;
3233c9274b6bSCho, Yu-Chen
3234c9274b6bSCho, Yu-Chen /* r1 and r3 must be even. */
3235c9274b6bSCho, Yu-Chen if (r1 & 1 || r3 & 1) {
3236c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3237c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3238c9274b6bSCho, Yu-Chen }
3239c9274b6bSCho, Yu-Chen
3240f1ea739bSRichard Henderson t1 = tcg_constant_i32(r1);
3241f1ea739bSRichard Henderson t3 = tcg_constant_i32(r3);
3242ad75a51eSRichard Henderson gen_helper_mvcle(cc_op, tcg_env, t1, o->in2, t3);
3243c9274b6bSCho, Yu-Chen set_cc_static(s);
3244c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3245c9274b6bSCho, Yu-Chen }
3246c9274b6bSCho, Yu-Chen
op_mvclu(DisasContext * s,DisasOps * o)3247c9274b6bSCho, Yu-Chen static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o)
3248c9274b6bSCho, Yu-Chen {
3249c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
3250c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
3251c9274b6bSCho, Yu-Chen TCGv_i32 t1, t3;
3252c9274b6bSCho, Yu-Chen
3253c9274b6bSCho, Yu-Chen /* r1 and r3 must be even. */
3254c9274b6bSCho, Yu-Chen if (r1 & 1 || r3 & 1) {
3255c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3256c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3257c9274b6bSCho, Yu-Chen }
3258c9274b6bSCho, Yu-Chen
3259f1ea739bSRichard Henderson t1 = tcg_constant_i32(r1);
3260f1ea739bSRichard Henderson t3 = tcg_constant_i32(r3);
3261ad75a51eSRichard Henderson gen_helper_mvclu(cc_op, tcg_env, t1, o->in2, t3);
3262c9274b6bSCho, Yu-Chen set_cc_static(s);
3263c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3264c9274b6bSCho, Yu-Chen }
3265c9274b6bSCho, Yu-Chen
op_mvcos(DisasContext * s,DisasOps * o)3266c9274b6bSCho, Yu-Chen static DisasJumpType op_mvcos(DisasContext *s, DisasOps *o)
3267c9274b6bSCho, Yu-Chen {
3268c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
3269ad75a51eSRichard Henderson gen_helper_mvcos(cc_op, tcg_env, o->addr1, o->in2, regs[r3]);
3270c9274b6bSCho, Yu-Chen set_cc_static(s);
3271c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3272c9274b6bSCho, Yu-Chen }
3273c9274b6bSCho, Yu-Chen
3274c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_mvcp(DisasContext * s,DisasOps * o)3275c9274b6bSCho, Yu-Chen static DisasJumpType op_mvcp(DisasContext *s, DisasOps *o)
3276c9274b6bSCho, Yu-Chen {
3277c9274b6bSCho, Yu-Chen int r1 = get_field(s, l1);
32783ef473e5SThomas Huth int r3 = get_field(s, r3);
3279ad75a51eSRichard Henderson gen_helper_mvcp(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]);
3280c9274b6bSCho, Yu-Chen set_cc_static(s);
3281c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3282c9274b6bSCho, Yu-Chen }
3283c9274b6bSCho, Yu-Chen
op_mvcs(DisasContext * s,DisasOps * o)3284c9274b6bSCho, Yu-Chen static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o)
3285c9274b6bSCho, Yu-Chen {
3286c9274b6bSCho, Yu-Chen int r1 = get_field(s, l1);
32873ef473e5SThomas Huth int r3 = get_field(s, r3);
3288ad75a51eSRichard Henderson gen_helper_mvcs(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]);
3289c9274b6bSCho, Yu-Chen set_cc_static(s);
3290c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3291c9274b6bSCho, Yu-Chen }
3292c9274b6bSCho, Yu-Chen #endif
3293c9274b6bSCho, Yu-Chen
op_mvn(DisasContext * s,DisasOps * o)3294c9274b6bSCho, Yu-Chen static DisasJumpType op_mvn(DisasContext *s, DisasOps *o)
3295c9274b6bSCho, Yu-Chen {
3296f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3297f1ea739bSRichard Henderson
3298ad75a51eSRichard Henderson gen_helper_mvn(tcg_env, l, o->addr1, o->in2);
3299c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3300c9274b6bSCho, Yu-Chen }
3301c9274b6bSCho, Yu-Chen
op_mvo(DisasContext * s,DisasOps * o)3302c9274b6bSCho, Yu-Chen static DisasJumpType op_mvo(DisasContext *s, DisasOps *o)
3303c9274b6bSCho, Yu-Chen {
3304f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3305f1ea739bSRichard Henderson
3306ad75a51eSRichard Henderson gen_helper_mvo(tcg_env, l, o->addr1, o->in2);
3307c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3308c9274b6bSCho, Yu-Chen }
3309c9274b6bSCho, Yu-Chen
op_mvpg(DisasContext * s,DisasOps * o)3310c9274b6bSCho, Yu-Chen static DisasJumpType op_mvpg(DisasContext *s, DisasOps *o)
3311c9274b6bSCho, Yu-Chen {
3312f1ea739bSRichard Henderson TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1));
3313f1ea739bSRichard Henderson TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2));
3314c9274b6bSCho, Yu-Chen
3315ad75a51eSRichard Henderson gen_helper_mvpg(cc_op, tcg_env, regs[0], t1, t2);
3316c9274b6bSCho, Yu-Chen set_cc_static(s);
3317c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3318c9274b6bSCho, Yu-Chen }
3319c9274b6bSCho, Yu-Chen
op_mvst(DisasContext * s,DisasOps * o)3320c9274b6bSCho, Yu-Chen static DisasJumpType op_mvst(DisasContext *s, DisasOps *o)
3321c9274b6bSCho, Yu-Chen {
3322f1ea739bSRichard Henderson TCGv_i32 t1 = tcg_constant_i32(get_field(s, r1));
3323f1ea739bSRichard Henderson TCGv_i32 t2 = tcg_constant_i32(get_field(s, r2));
3324c9274b6bSCho, Yu-Chen
3325ad75a51eSRichard Henderson gen_helper_mvst(cc_op, tcg_env, t1, t2);
3326c9274b6bSCho, Yu-Chen set_cc_static(s);
3327c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3328c9274b6bSCho, Yu-Chen }
3329c9274b6bSCho, Yu-Chen
op_mvz(DisasContext * s,DisasOps * o)3330c9274b6bSCho, Yu-Chen static DisasJumpType op_mvz(DisasContext *s, DisasOps *o)
3331c9274b6bSCho, Yu-Chen {
3332f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3333f1ea739bSRichard Henderson
3334ad75a51eSRichard Henderson gen_helper_mvz(tcg_env, l, o->addr1, o->in2);
3335c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3336c9274b6bSCho, Yu-Chen }
3337c9274b6bSCho, Yu-Chen
op_mul(DisasContext * s,DisasOps * o)3338c9274b6bSCho, Yu-Chen static DisasJumpType op_mul(DisasContext *s, DisasOps *o)
3339c9274b6bSCho, Yu-Chen {
3340c9274b6bSCho, Yu-Chen tcg_gen_mul_i64(o->out, o->in1, o->in2);
3341c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3342c9274b6bSCho, Yu-Chen }
3343c9274b6bSCho, Yu-Chen
op_mul128(DisasContext * s,DisasOps * o)3344c9274b6bSCho, Yu-Chen static DisasJumpType op_mul128(DisasContext *s, DisasOps *o)
3345c9274b6bSCho, Yu-Chen {
3346c9274b6bSCho, Yu-Chen tcg_gen_mulu2_i64(o->out2, o->out, o->in1, o->in2);
3347c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3348c9274b6bSCho, Yu-Chen }
3349c9274b6bSCho, Yu-Chen
op_muls128(DisasContext * s,DisasOps * o)3350c9274b6bSCho, Yu-Chen static DisasJumpType op_muls128(DisasContext *s, DisasOps *o)
3351c9274b6bSCho, Yu-Chen {
3352c9274b6bSCho, Yu-Chen tcg_gen_muls2_i64(o->out2, o->out, o->in1, o->in2);
3353c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3354c9274b6bSCho, Yu-Chen }
3355c9274b6bSCho, Yu-Chen
op_meeb(DisasContext * s,DisasOps * o)3356c9274b6bSCho, Yu-Chen static DisasJumpType op_meeb(DisasContext *s, DisasOps *o)
3357c9274b6bSCho, Yu-Chen {
3358ad75a51eSRichard Henderson gen_helper_meeb(o->out, tcg_env, o->in1, o->in2);
3359c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3360c9274b6bSCho, Yu-Chen }
3361c9274b6bSCho, Yu-Chen
op_mdeb(DisasContext * s,DisasOps * o)3362c9274b6bSCho, Yu-Chen static DisasJumpType op_mdeb(DisasContext *s, DisasOps *o)
3363c9274b6bSCho, Yu-Chen {
3364ad75a51eSRichard Henderson gen_helper_mdeb(o->out, tcg_env, o->in1, o->in2);
3365c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3366c9274b6bSCho, Yu-Chen }
3367c9274b6bSCho, Yu-Chen
op_mdb(DisasContext * s,DisasOps * o)3368c9274b6bSCho, Yu-Chen static DisasJumpType op_mdb(DisasContext *s, DisasOps *o)
3369c9274b6bSCho, Yu-Chen {
3370ad75a51eSRichard Henderson gen_helper_mdb(o->out, tcg_env, o->in1, o->in2);
3371c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3372c9274b6bSCho, Yu-Chen }
3373c9274b6bSCho, Yu-Chen
op_mxb(DisasContext * s,DisasOps * o)3374c9274b6bSCho, Yu-Chen static DisasJumpType op_mxb(DisasContext *s, DisasOps *o)
3375c9274b6bSCho, Yu-Chen {
3376ad75a51eSRichard Henderson gen_helper_mxb(o->out_128, tcg_env, o->in1_128, o->in2_128);
3377c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3378c9274b6bSCho, Yu-Chen }
3379c9274b6bSCho, Yu-Chen
op_mxdb(DisasContext * s,DisasOps * o)3380c9274b6bSCho, Yu-Chen static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o)
3381c9274b6bSCho, Yu-Chen {
3382ad75a51eSRichard Henderson gen_helper_mxdb(o->out_128, tcg_env, o->in1, o->in2);
3383c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3384c9274b6bSCho, Yu-Chen }
3385c9274b6bSCho, Yu-Chen
op_maeb(DisasContext * s,DisasOps * o)3386c9274b6bSCho, Yu-Chen static DisasJumpType op_maeb(DisasContext *s, DisasOps *o)
3387c9274b6bSCho, Yu-Chen {
3388c9274b6bSCho, Yu-Chen TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
3389ad75a51eSRichard Henderson gen_helper_maeb(o->out, tcg_env, o->in1, o->in2, r3);
3390c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3391c9274b6bSCho, Yu-Chen }
3392c9274b6bSCho, Yu-Chen
op_madb(DisasContext * s,DisasOps * o)3393c9274b6bSCho, Yu-Chen static DisasJumpType op_madb(DisasContext *s, DisasOps *o)
3394c9274b6bSCho, Yu-Chen {
3395c9274b6bSCho, Yu-Chen TCGv_i64 r3 = load_freg(get_field(s, r3));
3396ad75a51eSRichard Henderson gen_helper_madb(o->out, tcg_env, o->in1, o->in2, r3);
3397c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3398c9274b6bSCho, Yu-Chen }
3399c9274b6bSCho, Yu-Chen
op_mseb(DisasContext * s,DisasOps * o)3400c9274b6bSCho, Yu-Chen static DisasJumpType op_mseb(DisasContext *s, DisasOps *o)
3401c9274b6bSCho, Yu-Chen {
3402c9274b6bSCho, Yu-Chen TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
3403ad75a51eSRichard Henderson gen_helper_mseb(o->out, tcg_env, o->in1, o->in2, r3);
3404c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3405c9274b6bSCho, Yu-Chen }
3406c9274b6bSCho, Yu-Chen
op_msdb(DisasContext * s,DisasOps * o)3407c9274b6bSCho, Yu-Chen static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
3408c9274b6bSCho, Yu-Chen {
3409c9274b6bSCho, Yu-Chen TCGv_i64 r3 = load_freg(get_field(s, r3));
3410ad75a51eSRichard Henderson gen_helper_msdb(o->out, tcg_env, o->in1, o->in2, r3);
3411c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3412c9274b6bSCho, Yu-Chen }
3413c9274b6bSCho, Yu-Chen
op_nabs(DisasContext * s,DisasOps * o)3414c9274b6bSCho, Yu-Chen static DisasJumpType op_nabs(DisasContext *s, DisasOps *o)
3415c9274b6bSCho, Yu-Chen {
3416f1ea739bSRichard Henderson TCGv_i64 z = tcg_constant_i64(0);
3417f1ea739bSRichard Henderson TCGv_i64 n = tcg_temp_new_i64();
3418f1ea739bSRichard Henderson
3419c9274b6bSCho, Yu-Chen tcg_gen_neg_i64(n, o->in2);
3420c9274b6bSCho, Yu-Chen tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2);
3421c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3422c9274b6bSCho, Yu-Chen }
3423c9274b6bSCho, Yu-Chen
op_nabsf32(DisasContext * s,DisasOps * o)3424c9274b6bSCho, Yu-Chen static DisasJumpType op_nabsf32(DisasContext *s, DisasOps *o)
3425c9274b6bSCho, Yu-Chen {
3426c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(o->out, o->in2, 0x80000000ull);
3427c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3428c9274b6bSCho, Yu-Chen }
3429c9274b6bSCho, Yu-Chen
op_nabsf64(DisasContext * s,DisasOps * o)3430c9274b6bSCho, Yu-Chen static DisasJumpType op_nabsf64(DisasContext *s, DisasOps *o)
3431c9274b6bSCho, Yu-Chen {
3432c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(o->out, o->in2, 0x8000000000000000ull);
3433c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3434c9274b6bSCho, Yu-Chen }
3435c9274b6bSCho, Yu-Chen
op_nabsf128(DisasContext * s,DisasOps * o)3436c9274b6bSCho, Yu-Chen static DisasJumpType op_nabsf128(DisasContext *s, DisasOps *o)
3437c9274b6bSCho, Yu-Chen {
3438c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(o->out, o->in1, 0x8000000000000000ull);
3439c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(o->out2, o->in2);
3440c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3441c9274b6bSCho, Yu-Chen }
3442c9274b6bSCho, Yu-Chen
op_nc(DisasContext * s,DisasOps * o)3443c9274b6bSCho, Yu-Chen static DisasJumpType op_nc(DisasContext *s, DisasOps *o)
3444c9274b6bSCho, Yu-Chen {
3445f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3446f1ea739bSRichard Henderson
3447ad75a51eSRichard Henderson gen_helper_nc(cc_op, tcg_env, l, o->addr1, o->in2);
3448c9274b6bSCho, Yu-Chen set_cc_static(s);
3449c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3450c9274b6bSCho, Yu-Chen }
3451c9274b6bSCho, Yu-Chen
op_neg(DisasContext * s,DisasOps * o)3452c9274b6bSCho, Yu-Chen static DisasJumpType op_neg(DisasContext *s, DisasOps *o)
3453c9274b6bSCho, Yu-Chen {
3454c9274b6bSCho, Yu-Chen tcg_gen_neg_i64(o->out, o->in2);
3455c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3456c9274b6bSCho, Yu-Chen }
3457c9274b6bSCho, Yu-Chen
op_negf32(DisasContext * s,DisasOps * o)3458c9274b6bSCho, Yu-Chen static DisasJumpType op_negf32(DisasContext *s, DisasOps *o)
3459c9274b6bSCho, Yu-Chen {
3460c9274b6bSCho, Yu-Chen tcg_gen_xori_i64(o->out, o->in2, 0x80000000ull);
3461c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3462c9274b6bSCho, Yu-Chen }
3463c9274b6bSCho, Yu-Chen
op_negf64(DisasContext * s,DisasOps * o)3464c9274b6bSCho, Yu-Chen static DisasJumpType op_negf64(DisasContext *s, DisasOps *o)
3465c9274b6bSCho, Yu-Chen {
3466c9274b6bSCho, Yu-Chen tcg_gen_xori_i64(o->out, o->in2, 0x8000000000000000ull);
3467c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3468c9274b6bSCho, Yu-Chen }
3469c9274b6bSCho, Yu-Chen
op_negf128(DisasContext * s,DisasOps * o)3470c9274b6bSCho, Yu-Chen static DisasJumpType op_negf128(DisasContext *s, DisasOps *o)
3471c9274b6bSCho, Yu-Chen {
3472c9274b6bSCho, Yu-Chen tcg_gen_xori_i64(o->out, o->in1, 0x8000000000000000ull);
3473c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(o->out2, o->in2);
3474c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3475c9274b6bSCho, Yu-Chen }
3476c9274b6bSCho, Yu-Chen
op_oc(DisasContext * s,DisasOps * o)3477c9274b6bSCho, Yu-Chen static DisasJumpType op_oc(DisasContext *s, DisasOps *o)
3478c9274b6bSCho, Yu-Chen {
3479f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3480f1ea739bSRichard Henderson
3481ad75a51eSRichard Henderson gen_helper_oc(cc_op, tcg_env, l, o->addr1, o->in2);
3482c9274b6bSCho, Yu-Chen set_cc_static(s);
3483c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3484c9274b6bSCho, Yu-Chen }
3485c9274b6bSCho, Yu-Chen
op_or(DisasContext * s,DisasOps * o)3486c9274b6bSCho, Yu-Chen static DisasJumpType op_or(DisasContext *s, DisasOps *o)
3487c9274b6bSCho, Yu-Chen {
3488c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->in1, o->in2);
3489c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3490c9274b6bSCho, Yu-Chen }
3491c9274b6bSCho, Yu-Chen
op_ori(DisasContext * s,DisasOps * o)3492c9274b6bSCho, Yu-Chen static DisasJumpType op_ori(DisasContext *s, DisasOps *o)
3493c9274b6bSCho, Yu-Chen {
3494c9274b6bSCho, Yu-Chen int shift = s->insn->data & 0xff;
3495c9274b6bSCho, Yu-Chen int size = s->insn->data >> 8;
3496c9274b6bSCho, Yu-Chen uint64_t mask = ((1ull << size) - 1) << shift;
3497ab9984bdSRichard Henderson TCGv_i64 t = tcg_temp_new_i64();
3498c9274b6bSCho, Yu-Chen
3499ab9984bdSRichard Henderson tcg_gen_shli_i64(t, o->in2, shift);
3500ab9984bdSRichard Henderson tcg_gen_or_i64(o->out, o->in1, t);
3501c9274b6bSCho, Yu-Chen
3502c9274b6bSCho, Yu-Chen /* Produce the CC from only the bits manipulated. */
3503c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(cc_dst, o->out, mask);
3504c9274b6bSCho, Yu-Chen set_cc_nz_u64(s, cc_dst);
3505c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3506c9274b6bSCho, Yu-Chen }
3507c9274b6bSCho, Yu-Chen
op_oi(DisasContext * s,DisasOps * o)3508c9274b6bSCho, Yu-Chen static DisasJumpType op_oi(DisasContext *s, DisasOps *o)
3509c9274b6bSCho, Yu-Chen {
3510c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
3511c9274b6bSCho, Yu-Chen
3512c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
3513c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
3514c9274b6bSCho, Yu-Chen } else {
3515c9274b6bSCho, Yu-Chen /* Perform the atomic operation in memory. */
3516c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_or_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
3517c9274b6bSCho, Yu-Chen s->insn->data);
3518c9274b6bSCho, Yu-Chen }
3519c9274b6bSCho, Yu-Chen
3520c9274b6bSCho, Yu-Chen /* Recompute also for atomic case: needed for setting CC. */
3521c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->in1, o->in2);
3522c9274b6bSCho, Yu-Chen
3523c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
3524c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
3525c9274b6bSCho, Yu-Chen }
3526c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3527c9274b6bSCho, Yu-Chen }
3528c9274b6bSCho, Yu-Chen
op_pack(DisasContext * s,DisasOps * o)3529c9274b6bSCho, Yu-Chen static DisasJumpType op_pack(DisasContext *s, DisasOps *o)
3530c9274b6bSCho, Yu-Chen {
3531f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
3532f1ea739bSRichard Henderson
3533ad75a51eSRichard Henderson gen_helper_pack(tcg_env, l, o->addr1, o->in2);
3534c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3535c9274b6bSCho, Yu-Chen }
3536c9274b6bSCho, Yu-Chen
op_pka(DisasContext * s,DisasOps * o)3537c9274b6bSCho, Yu-Chen static DisasJumpType op_pka(DisasContext *s, DisasOps *o)
3538c9274b6bSCho, Yu-Chen {
3539c9274b6bSCho, Yu-Chen int l2 = get_field(s, l2) + 1;
3540c9274b6bSCho, Yu-Chen TCGv_i32 l;
3541c9274b6bSCho, Yu-Chen
3542c9274b6bSCho, Yu-Chen /* The length must not exceed 32 bytes. */
3543c9274b6bSCho, Yu-Chen if (l2 > 32) {
3544c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3545c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3546c9274b6bSCho, Yu-Chen }
3547f1ea739bSRichard Henderson l = tcg_constant_i32(l2);
3548ad75a51eSRichard Henderson gen_helper_pka(tcg_env, o->addr1, o->in2, l);
3549c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3550c9274b6bSCho, Yu-Chen }
3551c9274b6bSCho, Yu-Chen
op_pku(DisasContext * s,DisasOps * o)3552c9274b6bSCho, Yu-Chen static DisasJumpType op_pku(DisasContext *s, DisasOps *o)
3553c9274b6bSCho, Yu-Chen {
3554c9274b6bSCho, Yu-Chen int l2 = get_field(s, l2) + 1;
3555c9274b6bSCho, Yu-Chen TCGv_i32 l;
3556c9274b6bSCho, Yu-Chen
3557c9274b6bSCho, Yu-Chen /* The length must be even and should not exceed 64 bytes. */
3558c9274b6bSCho, Yu-Chen if ((l2 & 1) || (l2 > 64)) {
3559c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3560c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3561c9274b6bSCho, Yu-Chen }
3562f1ea739bSRichard Henderson l = tcg_constant_i32(l2);
3563ad75a51eSRichard Henderson gen_helper_pku(tcg_env, o->addr1, o->in2, l);
3564c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3565c9274b6bSCho, Yu-Chen }
3566c9274b6bSCho, Yu-Chen
op_popcnt(DisasContext * s,DisasOps * o)3567c9274b6bSCho, Yu-Chen static DisasJumpType op_popcnt(DisasContext *s, DisasOps *o)
3568c9274b6bSCho, Yu-Chen {
3569ea0a1053SDavid Miller const uint8_t m3 = get_field(s, m3);
3570ea0a1053SDavid Miller
3571ea0a1053SDavid Miller if ((m3 & 8) && s390_has_feat(S390_FEAT_MISC_INSTRUCTION_EXT3)) {
3572ea0a1053SDavid Miller tcg_gen_ctpop_i64(o->out, o->in2);
3573ea0a1053SDavid Miller } else {
3574c9274b6bSCho, Yu-Chen gen_helper_popcnt(o->out, o->in2);
3575ea0a1053SDavid Miller }
3576c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3577c9274b6bSCho, Yu-Chen }
3578c9274b6bSCho, Yu-Chen
3579c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_ptlb(DisasContext * s,DisasOps * o)3580c9274b6bSCho, Yu-Chen static DisasJumpType op_ptlb(DisasContext *s, DisasOps *o)
3581c9274b6bSCho, Yu-Chen {
3582ad75a51eSRichard Henderson gen_helper_ptlb(tcg_env);
3583c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3584c9274b6bSCho, Yu-Chen }
3585c9274b6bSCho, Yu-Chen #endif
3586c9274b6bSCho, Yu-Chen
op_risbg(DisasContext * s,DisasOps * o)3587c9274b6bSCho, Yu-Chen static DisasJumpType op_risbg(DisasContext *s, DisasOps *o)
3588c9274b6bSCho, Yu-Chen {
3589c9274b6bSCho, Yu-Chen int i3 = get_field(s, i3);
3590c9274b6bSCho, Yu-Chen int i4 = get_field(s, i4);
3591c9274b6bSCho, Yu-Chen int i5 = get_field(s, i5);
3592c9274b6bSCho, Yu-Chen int do_zero = i4 & 0x80;
3593c9274b6bSCho, Yu-Chen uint64_t mask, imask, pmask;
3594c9274b6bSCho, Yu-Chen int pos, len, rot;
3595c9274b6bSCho, Yu-Chen
3596c9274b6bSCho, Yu-Chen /* Adjust the arguments for the specific insn. */
3597c9274b6bSCho, Yu-Chen switch (s->fields.op2) {
3598c9274b6bSCho, Yu-Chen case 0x55: /* risbg */
3599c9274b6bSCho, Yu-Chen case 0x59: /* risbgn */
3600c9274b6bSCho, Yu-Chen i3 &= 63;
3601c9274b6bSCho, Yu-Chen i4 &= 63;
3602c9274b6bSCho, Yu-Chen pmask = ~0;
3603c9274b6bSCho, Yu-Chen break;
3604c9274b6bSCho, Yu-Chen case 0x5d: /* risbhg */
3605c9274b6bSCho, Yu-Chen i3 &= 31;
3606c9274b6bSCho, Yu-Chen i4 &= 31;
3607c9274b6bSCho, Yu-Chen pmask = 0xffffffff00000000ull;
3608c9274b6bSCho, Yu-Chen break;
3609c9274b6bSCho, Yu-Chen case 0x51: /* risblg */
3610c9274b6bSCho, Yu-Chen i3 = (i3 & 31) + 32;
3611c9274b6bSCho, Yu-Chen i4 = (i4 & 31) + 32;
3612c9274b6bSCho, Yu-Chen pmask = 0x00000000ffffffffull;
3613c9274b6bSCho, Yu-Chen break;
3614c9274b6bSCho, Yu-Chen default:
3615c9274b6bSCho, Yu-Chen g_assert_not_reached();
3616c9274b6bSCho, Yu-Chen }
3617c9274b6bSCho, Yu-Chen
3618c9274b6bSCho, Yu-Chen /* MASK is the set of bits to be inserted from R2. */
3619c9274b6bSCho, Yu-Chen if (i3 <= i4) {
3620c9274b6bSCho, Yu-Chen /* [0...i3---i4...63] */
3621c9274b6bSCho, Yu-Chen mask = (-1ull >> i3) & (-1ull << (63 - i4));
3622c9274b6bSCho, Yu-Chen } else {
3623c9274b6bSCho, Yu-Chen /* [0---i4...i3---63] */
3624c9274b6bSCho, Yu-Chen mask = (-1ull >> i3) | (-1ull << (63 - i4));
3625c9274b6bSCho, Yu-Chen }
3626c9274b6bSCho, Yu-Chen /* For RISBLG/RISBHG, the wrapping is limited to the high/low doubleword. */
3627c9274b6bSCho, Yu-Chen mask &= pmask;
3628c9274b6bSCho, Yu-Chen
3629c9274b6bSCho, Yu-Chen /* IMASK is the set of bits to be kept from R1. In the case of the high/low
3630c9274b6bSCho, Yu-Chen insns, we need to keep the other half of the register. */
3631c9274b6bSCho, Yu-Chen imask = ~mask | ~pmask;
3632c9274b6bSCho, Yu-Chen if (do_zero) {
3633c9274b6bSCho, Yu-Chen imask = ~pmask;
3634c9274b6bSCho, Yu-Chen }
3635c9274b6bSCho, Yu-Chen
3636c9274b6bSCho, Yu-Chen len = i4 - i3 + 1;
3637c9274b6bSCho, Yu-Chen pos = 63 - i4;
3638c9274b6bSCho, Yu-Chen rot = i5 & 63;
3639c9274b6bSCho, Yu-Chen
3640c9274b6bSCho, Yu-Chen /* In some cases we can implement this with extract. */
3641c9274b6bSCho, Yu-Chen if (imask == 0 && pos == 0 && len > 0 && len <= rot) {
3642c9274b6bSCho, Yu-Chen tcg_gen_extract_i64(o->out, o->in2, 64 - rot, len);
3643c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3644c9274b6bSCho, Yu-Chen }
3645c9274b6bSCho, Yu-Chen
3646c9274b6bSCho, Yu-Chen /* In some cases we can implement this with deposit. */
3647c9274b6bSCho, Yu-Chen if (len > 0 && (imask == 0 || ~mask == imask)) {
3648c9274b6bSCho, Yu-Chen /* Note that we rotate the bits to be inserted to the lsb, not to
3649c9274b6bSCho, Yu-Chen the position as described in the PoO. */
3650c9274b6bSCho, Yu-Chen rot = (rot - pos) & 63;
3651c9274b6bSCho, Yu-Chen } else {
3652c9274b6bSCho, Yu-Chen pos = -1;
3653c9274b6bSCho, Yu-Chen }
3654c9274b6bSCho, Yu-Chen
3655c9274b6bSCho, Yu-Chen /* Rotate the input as necessary. */
3656c9274b6bSCho, Yu-Chen tcg_gen_rotli_i64(o->in2, o->in2, rot);
3657c9274b6bSCho, Yu-Chen
3658c9274b6bSCho, Yu-Chen /* Insert the selected bits into the output. */
3659c9274b6bSCho, Yu-Chen if (pos >= 0) {
3660c9274b6bSCho, Yu-Chen if (imask == 0) {
3661c9274b6bSCho, Yu-Chen tcg_gen_deposit_z_i64(o->out, o->in2, pos, len);
3662c9274b6bSCho, Yu-Chen } else {
3663c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(o->out, o->out, o->in2, pos, len);
3664c9274b6bSCho, Yu-Chen }
3665c9274b6bSCho, Yu-Chen } else if (imask == 0) {
3666c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->in2, mask);
3667c9274b6bSCho, Yu-Chen } else {
3668c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->in2, o->in2, mask);
3669c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->out, imask);
3670c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->out, o->in2);
3671c9274b6bSCho, Yu-Chen }
3672c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3673c9274b6bSCho, Yu-Chen }
3674c9274b6bSCho, Yu-Chen
op_rosbg(DisasContext * s,DisasOps * o)3675c9274b6bSCho, Yu-Chen static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
3676c9274b6bSCho, Yu-Chen {
3677c9274b6bSCho, Yu-Chen int i3 = get_field(s, i3);
3678c9274b6bSCho, Yu-Chen int i4 = get_field(s, i4);
3679c9274b6bSCho, Yu-Chen int i5 = get_field(s, i5);
36809701596dSIlya Leoshkevich TCGv_i64 orig_out;
3681c9274b6bSCho, Yu-Chen uint64_t mask;
3682c9274b6bSCho, Yu-Chen
3683c9274b6bSCho, Yu-Chen /* If this is a test-only form, arrange to discard the result. */
3684c9274b6bSCho, Yu-Chen if (i3 & 0x80) {
36859701596dSIlya Leoshkevich tcg_debug_assert(o->out != NULL);
36869701596dSIlya Leoshkevich orig_out = o->out;
3687c9274b6bSCho, Yu-Chen o->out = tcg_temp_new_i64();
36889701596dSIlya Leoshkevich tcg_gen_mov_i64(o->out, orig_out);
3689c9274b6bSCho, Yu-Chen }
3690c9274b6bSCho, Yu-Chen
3691c9274b6bSCho, Yu-Chen i3 &= 63;
3692c9274b6bSCho, Yu-Chen i4 &= 63;
3693c9274b6bSCho, Yu-Chen i5 &= 63;
3694c9274b6bSCho, Yu-Chen
3695c9274b6bSCho, Yu-Chen /* MASK is the set of bits to be operated on from R2.
3696c9274b6bSCho, Yu-Chen Take care for I3/I4 wraparound. */
3697c9274b6bSCho, Yu-Chen mask = ~0ull >> i3;
3698c9274b6bSCho, Yu-Chen if (i3 <= i4) {
3699c9274b6bSCho, Yu-Chen mask ^= ~0ull >> i4 >> 1;
3700c9274b6bSCho, Yu-Chen } else {
3701c9274b6bSCho, Yu-Chen mask |= ~(~0ull >> i4 >> 1);
3702c9274b6bSCho, Yu-Chen }
3703c9274b6bSCho, Yu-Chen
3704c9274b6bSCho, Yu-Chen /* Rotate the input as necessary. */
3705c9274b6bSCho, Yu-Chen tcg_gen_rotli_i64(o->in2, o->in2, i5);
3706c9274b6bSCho, Yu-Chen
3707c9274b6bSCho, Yu-Chen /* Operate. */
3708c9274b6bSCho, Yu-Chen switch (s->fields.op2) {
3709c9274b6bSCho, Yu-Chen case 0x54: /* AND */
3710c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(o->in2, o->in2, ~mask);
3711c9274b6bSCho, Yu-Chen tcg_gen_and_i64(o->out, o->out, o->in2);
3712c9274b6bSCho, Yu-Chen break;
3713c9274b6bSCho, Yu-Chen case 0x56: /* OR */
3714c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->in2, o->in2, mask);
3715c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->out, o->in2);
3716c9274b6bSCho, Yu-Chen break;
3717c9274b6bSCho, Yu-Chen case 0x57: /* XOR */
3718c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->in2, o->in2, mask);
3719c9274b6bSCho, Yu-Chen tcg_gen_xor_i64(o->out, o->out, o->in2);
3720c9274b6bSCho, Yu-Chen break;
3721c9274b6bSCho, Yu-Chen default:
3722c9274b6bSCho, Yu-Chen abort();
3723c9274b6bSCho, Yu-Chen }
3724c9274b6bSCho, Yu-Chen
3725c9274b6bSCho, Yu-Chen /* Set the CC. */
3726c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(cc_dst, o->out, mask);
3727c9274b6bSCho, Yu-Chen set_cc_nz_u64(s, cc_dst);
3728c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3729c9274b6bSCho, Yu-Chen }
3730c9274b6bSCho, Yu-Chen
op_rev16(DisasContext * s,DisasOps * o)3731c9274b6bSCho, Yu-Chen static DisasJumpType op_rev16(DisasContext *s, DisasOps *o)
3732c9274b6bSCho, Yu-Chen {
3733c9274b6bSCho, Yu-Chen tcg_gen_bswap16_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
3734c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3735c9274b6bSCho, Yu-Chen }
3736c9274b6bSCho, Yu-Chen
op_rev32(DisasContext * s,DisasOps * o)3737c9274b6bSCho, Yu-Chen static DisasJumpType op_rev32(DisasContext *s, DisasOps *o)
3738c9274b6bSCho, Yu-Chen {
3739c9274b6bSCho, Yu-Chen tcg_gen_bswap32_i64(o->out, o->in2, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
3740c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3741c9274b6bSCho, Yu-Chen }
3742c9274b6bSCho, Yu-Chen
op_rev64(DisasContext * s,DisasOps * o)3743c9274b6bSCho, Yu-Chen static DisasJumpType op_rev64(DisasContext *s, DisasOps *o)
3744c9274b6bSCho, Yu-Chen {
3745c9274b6bSCho, Yu-Chen tcg_gen_bswap64_i64(o->out, o->in2);
3746c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3747c9274b6bSCho, Yu-Chen }
3748c9274b6bSCho, Yu-Chen
op_rll32(DisasContext * s,DisasOps * o)3749c9274b6bSCho, Yu-Chen static DisasJumpType op_rll32(DisasContext *s, DisasOps *o)
3750c9274b6bSCho, Yu-Chen {
3751c9274b6bSCho, Yu-Chen TCGv_i32 t1 = tcg_temp_new_i32();
3752c9274b6bSCho, Yu-Chen TCGv_i32 t2 = tcg_temp_new_i32();
3753c9274b6bSCho, Yu-Chen TCGv_i32 to = tcg_temp_new_i32();
3754c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(t1, o->in1);
3755c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(t2, o->in2);
3756c9274b6bSCho, Yu-Chen tcg_gen_rotl_i32(to, t1, t2);
3757c9274b6bSCho, Yu-Chen tcg_gen_extu_i32_i64(o->out, to);
3758c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3759c9274b6bSCho, Yu-Chen }
3760c9274b6bSCho, Yu-Chen
op_rll64(DisasContext * s,DisasOps * o)3761c9274b6bSCho, Yu-Chen static DisasJumpType op_rll64(DisasContext *s, DisasOps *o)
3762c9274b6bSCho, Yu-Chen {
3763c9274b6bSCho, Yu-Chen tcg_gen_rotl_i64(o->out, o->in1, o->in2);
3764c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3765c9274b6bSCho, Yu-Chen }
3766c9274b6bSCho, Yu-Chen
3767c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_rrbe(DisasContext * s,DisasOps * o)3768c9274b6bSCho, Yu-Chen static DisasJumpType op_rrbe(DisasContext *s, DisasOps *o)
3769c9274b6bSCho, Yu-Chen {
3770ad75a51eSRichard Henderson gen_helper_rrbe(cc_op, tcg_env, o->in2);
3771c9274b6bSCho, Yu-Chen set_cc_static(s);
3772c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3773c9274b6bSCho, Yu-Chen }
3774c9274b6bSCho, Yu-Chen
op_sacf(DisasContext * s,DisasOps * o)3775c9274b6bSCho, Yu-Chen static DisasJumpType op_sacf(DisasContext *s, DisasOps *o)
3776c9274b6bSCho, Yu-Chen {
3777ad75a51eSRichard Henderson gen_helper_sacf(tcg_env, o->in2);
3778c9274b6bSCho, Yu-Chen /* Addressing mode has changed, so end the block. */
37798ec2edacSRichard Henderson return DISAS_TOO_MANY;
3780c9274b6bSCho, Yu-Chen }
3781c9274b6bSCho, Yu-Chen #endif
3782c9274b6bSCho, Yu-Chen
op_sam(DisasContext * s,DisasOps * o)3783c9274b6bSCho, Yu-Chen static DisasJumpType op_sam(DisasContext *s, DisasOps *o)
3784c9274b6bSCho, Yu-Chen {
3785c9274b6bSCho, Yu-Chen int sam = s->insn->data;
3786c9274b6bSCho, Yu-Chen TCGv_i64 tsam;
3787c9274b6bSCho, Yu-Chen uint64_t mask;
3788c9274b6bSCho, Yu-Chen
3789c9274b6bSCho, Yu-Chen switch (sam) {
3790c9274b6bSCho, Yu-Chen case 0:
3791c9274b6bSCho, Yu-Chen mask = 0xffffff;
3792c9274b6bSCho, Yu-Chen break;
3793c9274b6bSCho, Yu-Chen case 1:
3794c9274b6bSCho, Yu-Chen mask = 0x7fffffff;
3795c9274b6bSCho, Yu-Chen break;
3796c9274b6bSCho, Yu-Chen default:
3797c9274b6bSCho, Yu-Chen mask = -1;
3798c9274b6bSCho, Yu-Chen break;
3799c9274b6bSCho, Yu-Chen }
3800c9274b6bSCho, Yu-Chen
3801c9274b6bSCho, Yu-Chen /* Bizarre but true, we check the address of the current insn for the
3802c9274b6bSCho, Yu-Chen specification exception, not the next to be executed. Thus the PoO
3803c9274b6bSCho, Yu-Chen documents that Bad Things Happen two bytes before the end. */
3804c9274b6bSCho, Yu-Chen if (s->base.pc_next & ~mask) {
3805c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
3806c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
3807c9274b6bSCho, Yu-Chen }
3808c9274b6bSCho, Yu-Chen s->pc_tmp &= mask;
3809c9274b6bSCho, Yu-Chen
3810f1ea739bSRichard Henderson tsam = tcg_constant_i64(sam);
3811c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2);
3812c9274b6bSCho, Yu-Chen
3813c9274b6bSCho, Yu-Chen /* Always exit the TB, since we (may have) changed execution mode. */
38148ec2edacSRichard Henderson return DISAS_TOO_MANY;
3815c9274b6bSCho, Yu-Chen }
3816c9274b6bSCho, Yu-Chen
op_sar(DisasContext * s,DisasOps * o)3817c9274b6bSCho, Yu-Chen static DisasJumpType op_sar(DisasContext *s, DisasOps *o)
3818c9274b6bSCho, Yu-Chen {
3819c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
3820ad75a51eSRichard Henderson tcg_gen_st32_i64(o->in2, tcg_env, offsetof(CPUS390XState, aregs[r1]));
3821c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3822c9274b6bSCho, Yu-Chen }
3823c9274b6bSCho, Yu-Chen
op_seb(DisasContext * s,DisasOps * o)3824c9274b6bSCho, Yu-Chen static DisasJumpType op_seb(DisasContext *s, DisasOps *o)
3825c9274b6bSCho, Yu-Chen {
3826ad75a51eSRichard Henderson gen_helper_seb(o->out, tcg_env, o->in1, o->in2);
3827c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3828c9274b6bSCho, Yu-Chen }
3829c9274b6bSCho, Yu-Chen
op_sdb(DisasContext * s,DisasOps * o)3830c9274b6bSCho, Yu-Chen static DisasJumpType op_sdb(DisasContext *s, DisasOps *o)
3831c9274b6bSCho, Yu-Chen {
3832ad75a51eSRichard Henderson gen_helper_sdb(o->out, tcg_env, o->in1, o->in2);
3833c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3834c9274b6bSCho, Yu-Chen }
3835c9274b6bSCho, Yu-Chen
op_sxb(DisasContext * s,DisasOps * o)3836c9274b6bSCho, Yu-Chen static DisasJumpType op_sxb(DisasContext *s, DisasOps *o)
3837c9274b6bSCho, Yu-Chen {
3838ad75a51eSRichard Henderson gen_helper_sxb(o->out_128, tcg_env, o->in1_128, o->in2_128);
3839c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3840c9274b6bSCho, Yu-Chen }
3841c9274b6bSCho, Yu-Chen
op_sqeb(DisasContext * s,DisasOps * o)3842c9274b6bSCho, Yu-Chen static DisasJumpType op_sqeb(DisasContext *s, DisasOps *o)
3843c9274b6bSCho, Yu-Chen {
3844ad75a51eSRichard Henderson gen_helper_sqeb(o->out, tcg_env, o->in2);
3845c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3846c9274b6bSCho, Yu-Chen }
3847c9274b6bSCho, Yu-Chen
op_sqdb(DisasContext * s,DisasOps * o)3848c9274b6bSCho, Yu-Chen static DisasJumpType op_sqdb(DisasContext *s, DisasOps *o)
3849c9274b6bSCho, Yu-Chen {
3850ad75a51eSRichard Henderson gen_helper_sqdb(o->out, tcg_env, o->in2);
3851c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3852c9274b6bSCho, Yu-Chen }
3853c9274b6bSCho, Yu-Chen
op_sqxb(DisasContext * s,DisasOps * o)3854c9274b6bSCho, Yu-Chen static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o)
3855c9274b6bSCho, Yu-Chen {
3856ad75a51eSRichard Henderson gen_helper_sqxb(o->out_128, tcg_env, o->in2_128);
3857c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3858c9274b6bSCho, Yu-Chen }
3859c9274b6bSCho, Yu-Chen
3860c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_servc(DisasContext * s,DisasOps * o)3861c9274b6bSCho, Yu-Chen static DisasJumpType op_servc(DisasContext *s, DisasOps *o)
3862c9274b6bSCho, Yu-Chen {
3863ad75a51eSRichard Henderson gen_helper_servc(cc_op, tcg_env, o->in2, o->in1);
3864c9274b6bSCho, Yu-Chen set_cc_static(s);
3865c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3866c9274b6bSCho, Yu-Chen }
3867c9274b6bSCho, Yu-Chen
op_sigp(DisasContext * s,DisasOps * o)3868c9274b6bSCho, Yu-Chen static DisasJumpType op_sigp(DisasContext *s, DisasOps *o)
3869c9274b6bSCho, Yu-Chen {
3870f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
3871f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
3872f1ea739bSRichard Henderson
3873ad75a51eSRichard Henderson gen_helper_sigp(cc_op, tcg_env, o->in2, r1, r3);
3874c9274b6bSCho, Yu-Chen set_cc_static(s);
3875c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3876c9274b6bSCho, Yu-Chen }
3877c9274b6bSCho, Yu-Chen #endif
3878c9274b6bSCho, Yu-Chen
op_soc(DisasContext * s,DisasOps * o)3879c9274b6bSCho, Yu-Chen static DisasJumpType op_soc(DisasContext *s, DisasOps *o)
3880c9274b6bSCho, Yu-Chen {
3881c9274b6bSCho, Yu-Chen DisasCompare c;
3882c9274b6bSCho, Yu-Chen TCGv_i64 a, h;
3883c9274b6bSCho, Yu-Chen TCGLabel *lab;
3884c9274b6bSCho, Yu-Chen int r1;
3885c9274b6bSCho, Yu-Chen
3886c9274b6bSCho, Yu-Chen disas_jcc(s, &c, get_field(s, m3));
3887c9274b6bSCho, Yu-Chen
3888c9274b6bSCho, Yu-Chen /* We want to store when the condition is fulfilled, so branch
3889c9274b6bSCho, Yu-Chen out when it's not */
3890c9274b6bSCho, Yu-Chen c.cond = tcg_invert_cond(c.cond);
3891c9274b6bSCho, Yu-Chen
3892c9274b6bSCho, Yu-Chen lab = gen_new_label();
3893c9274b6bSCho, Yu-Chen if (c.is_64) {
3894c9274b6bSCho, Yu-Chen tcg_gen_brcond_i64(c.cond, c.u.s64.a, c.u.s64.b, lab);
3895c9274b6bSCho, Yu-Chen } else {
3896c9274b6bSCho, Yu-Chen tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab);
3897c9274b6bSCho, Yu-Chen }
3898c9274b6bSCho, Yu-Chen
3899c9274b6bSCho, Yu-Chen r1 = get_field(s, r1);
3900c9274b6bSCho, Yu-Chen a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
3901c9274b6bSCho, Yu-Chen switch (s->insn->data) {
3902c9274b6bSCho, Yu-Chen case 1: /* STOCG */
3903e87027d0SRichard Henderson tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUQ);
3904c9274b6bSCho, Yu-Chen break;
3905c9274b6bSCho, Yu-Chen case 0: /* STOC */
3906e87027d0SRichard Henderson tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_TEUL);
3907c9274b6bSCho, Yu-Chen break;
3908c9274b6bSCho, Yu-Chen case 2: /* STOCFH */
3909c9274b6bSCho, Yu-Chen h = tcg_temp_new_i64();
3910c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(h, regs[r1], 32);
3911e87027d0SRichard Henderson tcg_gen_qemu_st_i64(h, a, get_mem_index(s), MO_TEUL);
3912c9274b6bSCho, Yu-Chen break;
3913c9274b6bSCho, Yu-Chen default:
3914c9274b6bSCho, Yu-Chen g_assert_not_reached();
3915c9274b6bSCho, Yu-Chen }
3916c9274b6bSCho, Yu-Chen
3917c9274b6bSCho, Yu-Chen gen_set_label(lab);
3918c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3919c9274b6bSCho, Yu-Chen }
3920c9274b6bSCho, Yu-Chen
op_sla(DisasContext * s,DisasOps * o)3921c9274b6bSCho, Yu-Chen static DisasJumpType op_sla(DisasContext *s, DisasOps *o)
3922c9274b6bSCho, Yu-Chen {
39236da170beSIlya Leoshkevich TCGv_i64 t;
3924c9274b6bSCho, Yu-Chen uint64_t sign = 1ull << s->insn->data;
39256da170beSIlya Leoshkevich if (s->insn->data == 31) {
39266da170beSIlya Leoshkevich t = tcg_temp_new_i64();
39276da170beSIlya Leoshkevich tcg_gen_shli_i64(t, o->in1, 32);
39286da170beSIlya Leoshkevich } else {
39296da170beSIlya Leoshkevich t = o->in1;
39306da170beSIlya Leoshkevich }
39316da170beSIlya Leoshkevich gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2);
3932c9274b6bSCho, Yu-Chen tcg_gen_shl_i64(o->out, o->in1, o->in2);
3933c9274b6bSCho, Yu-Chen /* The arithmetic left shift is curious in that it does not affect
3934c9274b6bSCho, Yu-Chen the sign bit. Copy that over from the source unchanged. */
3935c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->out, ~sign);
3936c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->in1, o->in1, sign);
3937c9274b6bSCho, Yu-Chen tcg_gen_or_i64(o->out, o->out, o->in1);
3938c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3939c9274b6bSCho, Yu-Chen }
3940c9274b6bSCho, Yu-Chen
op_sll(DisasContext * s,DisasOps * o)3941c9274b6bSCho, Yu-Chen static DisasJumpType op_sll(DisasContext *s, DisasOps *o)
3942c9274b6bSCho, Yu-Chen {
3943c9274b6bSCho, Yu-Chen tcg_gen_shl_i64(o->out, o->in1, o->in2);
3944c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3945c9274b6bSCho, Yu-Chen }
3946c9274b6bSCho, Yu-Chen
op_sra(DisasContext * s,DisasOps * o)3947c9274b6bSCho, Yu-Chen static DisasJumpType op_sra(DisasContext *s, DisasOps *o)
3948c9274b6bSCho, Yu-Chen {
3949c9274b6bSCho, Yu-Chen tcg_gen_sar_i64(o->out, o->in1, o->in2);
3950c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3951c9274b6bSCho, Yu-Chen }
3952c9274b6bSCho, Yu-Chen
op_srl(DisasContext * s,DisasOps * o)3953c9274b6bSCho, Yu-Chen static DisasJumpType op_srl(DisasContext *s, DisasOps *o)
3954c9274b6bSCho, Yu-Chen {
3955c9274b6bSCho, Yu-Chen tcg_gen_shr_i64(o->out, o->in1, o->in2);
3956c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3957c9274b6bSCho, Yu-Chen }
3958c9274b6bSCho, Yu-Chen
op_sfpc(DisasContext * s,DisasOps * o)3959c9274b6bSCho, Yu-Chen static DisasJumpType op_sfpc(DisasContext *s, DisasOps *o)
3960c9274b6bSCho, Yu-Chen {
3961ad75a51eSRichard Henderson gen_helper_sfpc(tcg_env, o->in2);
3962c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3963c9274b6bSCho, Yu-Chen }
3964c9274b6bSCho, Yu-Chen
op_sfas(DisasContext * s,DisasOps * o)3965c9274b6bSCho, Yu-Chen static DisasJumpType op_sfas(DisasContext *s, DisasOps *o)
3966c9274b6bSCho, Yu-Chen {
3967ad75a51eSRichard Henderson gen_helper_sfas(tcg_env, o->in2);
3968c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3969c9274b6bSCho, Yu-Chen }
3970c9274b6bSCho, Yu-Chen
op_srnm(DisasContext * s,DisasOps * o)3971c9274b6bSCho, Yu-Chen static DisasJumpType op_srnm(DisasContext *s, DisasOps *o)
3972c9274b6bSCho, Yu-Chen {
3973c9274b6bSCho, Yu-Chen /* Bits other than 62 and 63 are ignored. Bit 29 is set to zero. */
3974c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->addr1, o->addr1, 0x3ull);
3975ad75a51eSRichard Henderson gen_helper_srnm(tcg_env, o->addr1);
3976c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3977c9274b6bSCho, Yu-Chen }
3978c9274b6bSCho, Yu-Chen
op_srnmb(DisasContext * s,DisasOps * o)3979c9274b6bSCho, Yu-Chen static DisasJumpType op_srnmb(DisasContext *s, DisasOps *o)
3980c9274b6bSCho, Yu-Chen {
3981c9274b6bSCho, Yu-Chen /* Bits 0-55 are are ignored. */
3982c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->addr1, o->addr1, 0xffull);
3983ad75a51eSRichard Henderson gen_helper_srnm(tcg_env, o->addr1);
3984c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3985c9274b6bSCho, Yu-Chen }
3986c9274b6bSCho, Yu-Chen
op_srnmt(DisasContext * s,DisasOps * o)3987c9274b6bSCho, Yu-Chen static DisasJumpType op_srnmt(DisasContext *s, DisasOps *o)
3988c9274b6bSCho, Yu-Chen {
3989c9274b6bSCho, Yu-Chen TCGv_i64 tmp = tcg_temp_new_i64();
3990c9274b6bSCho, Yu-Chen
3991c9274b6bSCho, Yu-Chen /* Bits other than 61-63 are ignored. */
3992c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->addr1, o->addr1, 0x7ull);
3993c9274b6bSCho, Yu-Chen
3994c9274b6bSCho, Yu-Chen /* No need to call a helper, we don't implement dfp */
3995ad75a51eSRichard Henderson tcg_gen_ld32u_i64(tmp, tcg_env, offsetof(CPUS390XState, fpc));
3996c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3);
3997ad75a51eSRichard Henderson tcg_gen_st32_i64(tmp, tcg_env, offsetof(CPUS390XState, fpc));
3998c9274b6bSCho, Yu-Chen return DISAS_NEXT;
3999c9274b6bSCho, Yu-Chen }
4000c9274b6bSCho, Yu-Chen
op_spm(DisasContext * s,DisasOps * o)4001c9274b6bSCho, Yu-Chen static DisasJumpType op_spm(DisasContext *s, DisasOps *o)
4002c9274b6bSCho, Yu-Chen {
4003c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(cc_op, o->in1);
4004c9274b6bSCho, Yu-Chen tcg_gen_extract_i32(cc_op, cc_op, 28, 2);
4005c9274b6bSCho, Yu-Chen set_cc_static(s);
4006c9274b6bSCho, Yu-Chen
4007c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(o->in1, o->in1, 24);
4008c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(psw_mask, psw_mask, o->in1, PSW_SHIFT_MASK_PM, 4);
4009c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4010c9274b6bSCho, Yu-Chen }
4011c9274b6bSCho, Yu-Chen
op_ectg(DisasContext * s,DisasOps * o)4012c9274b6bSCho, Yu-Chen static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
4013c9274b6bSCho, Yu-Chen {
4014c9274b6bSCho, Yu-Chen int b1 = get_field(s, b1);
4015c9274b6bSCho, Yu-Chen int d1 = get_field(s, d1);
4016c9274b6bSCho, Yu-Chen int b2 = get_field(s, b2);
4017c9274b6bSCho, Yu-Chen int d2 = get_field(s, d2);
4018c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
4019c9274b6bSCho, Yu-Chen TCGv_i64 tmp = tcg_temp_new_i64();
4020c9274b6bSCho, Yu-Chen
4021c9274b6bSCho, Yu-Chen /* fetch all operands first */
4022c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
4023c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->in1, regs[b1], d1);
4024c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
4025c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->in2, regs[b2], d2);
4026c9274b6bSCho, Yu-Chen o->addr1 = tcg_temp_new_i64();
4027c9274b6bSCho, Yu-Chen gen_addi_and_wrap_i64(s, o->addr1, regs[r3], 0);
4028c9274b6bSCho, Yu-Chen
4029c9274b6bSCho, Yu-Chen /* load the third operand into r3 before modifying anything */
4030e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ);
4031c9274b6bSCho, Yu-Chen
4032c9274b6bSCho, Yu-Chen /* subtract CPU timer from first operand and store in GR0 */
4033ad75a51eSRichard Henderson gen_helper_stpt(tmp, tcg_env);
4034c9274b6bSCho, Yu-Chen tcg_gen_sub_i64(regs[0], o->in1, tmp);
4035c9274b6bSCho, Yu-Chen
4036c9274b6bSCho, Yu-Chen /* store second operand in GR1 */
4037c9274b6bSCho, Yu-Chen tcg_gen_mov_i64(regs[1], o->in2);
4038c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4039c9274b6bSCho, Yu-Chen }
4040c9274b6bSCho, Yu-Chen
4041c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_spka(DisasContext * s,DisasOps * o)4042c9274b6bSCho, Yu-Chen static DisasJumpType op_spka(DisasContext *s, DisasOps *o)
4043c9274b6bSCho, Yu-Chen {
4044c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(o->in2, o->in2, 4);
4045c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
4046c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4047c9274b6bSCho, Yu-Chen }
4048c9274b6bSCho, Yu-Chen
op_sske(DisasContext * s,DisasOps * o)4049c9274b6bSCho, Yu-Chen static DisasJumpType op_sske(DisasContext *s, DisasOps *o)
4050c9274b6bSCho, Yu-Chen {
4051ad75a51eSRichard Henderson gen_helper_sske(tcg_env, o->in1, o->in2);
4052c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4053c9274b6bSCho, Yu-Chen }
4054c9274b6bSCho, Yu-Chen
gen_check_psw_mask(DisasContext * s)4055199c42a6SIlya Leoshkevich static void gen_check_psw_mask(DisasContext *s)
4056199c42a6SIlya Leoshkevich {
4057199c42a6SIlya Leoshkevich TCGv_i64 reserved = tcg_temp_new_i64();
4058199c42a6SIlya Leoshkevich TCGLabel *ok = gen_new_label();
4059199c42a6SIlya Leoshkevich
4060199c42a6SIlya Leoshkevich tcg_gen_andi_i64(reserved, psw_mask, PSW_MASK_RESERVED);
4061199c42a6SIlya Leoshkevich tcg_gen_brcondi_i64(TCG_COND_EQ, reserved, 0, ok);
4062199c42a6SIlya Leoshkevich gen_program_exception(s, PGM_SPECIFICATION);
4063199c42a6SIlya Leoshkevich gen_set_label(ok);
4064199c42a6SIlya Leoshkevich }
4065199c42a6SIlya Leoshkevich
op_ssm(DisasContext * s,DisasOps * o)4066c9274b6bSCho, Yu-Chen static DisasJumpType op_ssm(DisasContext *s, DisasOps *o)
4067c9274b6bSCho, Yu-Chen {
4068c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8);
4069199c42a6SIlya Leoshkevich
4070199c42a6SIlya Leoshkevich gen_check_psw_mask(s);
4071199c42a6SIlya Leoshkevich
4072c9274b6bSCho, Yu-Chen /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
4073872e1379SRichard Henderson s->exit_to_mainloop = true;
4074872e1379SRichard Henderson return DISAS_TOO_MANY;
4075c9274b6bSCho, Yu-Chen }
4076c9274b6bSCho, Yu-Chen
op_stap(DisasContext * s,DisasOps * o)4077c9274b6bSCho, Yu-Chen static DisasJumpType op_stap(DisasContext *s, DisasOps *o)
4078c9274b6bSCho, Yu-Chen {
4079ad75a51eSRichard Henderson tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, core_id));
4080c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4081c9274b6bSCho, Yu-Chen }
4082c9274b6bSCho, Yu-Chen #endif
4083c9274b6bSCho, Yu-Chen
op_stck(DisasContext * s,DisasOps * o)4084c9274b6bSCho, Yu-Chen static DisasJumpType op_stck(DisasContext *s, DisasOps *o)
4085c9274b6bSCho, Yu-Chen {
4086ad75a51eSRichard Henderson gen_helper_stck(o->out, tcg_env);
4087c9274b6bSCho, Yu-Chen /* ??? We don't implement clock states. */
4088c9274b6bSCho, Yu-Chen gen_op_movi_cc(s, 0);
4089c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4090c9274b6bSCho, Yu-Chen }
4091c9274b6bSCho, Yu-Chen
op_stcke(DisasContext * s,DisasOps * o)4092c9274b6bSCho, Yu-Chen static DisasJumpType op_stcke(DisasContext *s, DisasOps *o)
4093c9274b6bSCho, Yu-Chen {
4094c9274b6bSCho, Yu-Chen TCGv_i64 c1 = tcg_temp_new_i64();
4095c9274b6bSCho, Yu-Chen TCGv_i64 c2 = tcg_temp_new_i64();
4096c9274b6bSCho, Yu-Chen TCGv_i64 todpr = tcg_temp_new_i64();
4097ad75a51eSRichard Henderson gen_helper_stck(c1, tcg_env);
4098c9274b6bSCho, Yu-Chen /* 16 bit value store in an uint32_t (only valid bits set) */
4099ad75a51eSRichard Henderson tcg_gen_ld32u_i64(todpr, tcg_env, offsetof(CPUS390XState, todpr));
4100c9274b6bSCho, Yu-Chen /* Shift the 64-bit value into its place as a zero-extended
4101c9274b6bSCho, Yu-Chen 104-bit value. Note that "bit positions 64-103 are always
4102c9274b6bSCho, Yu-Chen non-zero so that they compare differently to STCK"; we set
4103c9274b6bSCho, Yu-Chen the least significant bit to 1. */
4104c9274b6bSCho, Yu-Chen tcg_gen_shli_i64(c2, c1, 56);
4105c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(c1, c1, 8);
4106c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(c2, c2, 0x10000);
4107c9274b6bSCho, Yu-Chen tcg_gen_or_i64(c2, c2, todpr);
4108e87027d0SRichard Henderson tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_TEUQ);
4109c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->in2, o->in2, 8);
4110e87027d0SRichard Henderson tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_TEUQ);
4111c9274b6bSCho, Yu-Chen /* ??? We don't implement clock states. */
4112c9274b6bSCho, Yu-Chen gen_op_movi_cc(s, 0);
4113c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4114c9274b6bSCho, Yu-Chen }
4115c9274b6bSCho, Yu-Chen
4116c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_sck(DisasContext * s,DisasOps * o)4117c9274b6bSCho, Yu-Chen static DisasJumpType op_sck(DisasContext *s, DisasOps *o)
4118c9274b6bSCho, Yu-Chen {
4119ad75a51eSRichard Henderson gen_helper_sck(cc_op, tcg_env, o->in2);
4120c9274b6bSCho, Yu-Chen set_cc_static(s);
4121c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4122c9274b6bSCho, Yu-Chen }
4123c9274b6bSCho, Yu-Chen
op_sckc(DisasContext * s,DisasOps * o)4124c9274b6bSCho, Yu-Chen static DisasJumpType op_sckc(DisasContext *s, DisasOps *o)
4125c9274b6bSCho, Yu-Chen {
4126ad75a51eSRichard Henderson gen_helper_sckc(tcg_env, o->in2);
4127c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4128c9274b6bSCho, Yu-Chen }
4129c9274b6bSCho, Yu-Chen
op_sckpf(DisasContext * s,DisasOps * o)4130c9274b6bSCho, Yu-Chen static DisasJumpType op_sckpf(DisasContext *s, DisasOps *o)
4131c9274b6bSCho, Yu-Chen {
4132ad75a51eSRichard Henderson gen_helper_sckpf(tcg_env, regs[0]);
4133c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4134c9274b6bSCho, Yu-Chen }
4135c9274b6bSCho, Yu-Chen
op_stckc(DisasContext * s,DisasOps * o)4136c9274b6bSCho, Yu-Chen static DisasJumpType op_stckc(DisasContext *s, DisasOps *o)
4137c9274b6bSCho, Yu-Chen {
4138ad75a51eSRichard Henderson gen_helper_stckc(o->out, tcg_env);
4139c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4140c9274b6bSCho, Yu-Chen }
4141c9274b6bSCho, Yu-Chen
op_stctg(DisasContext * s,DisasOps * o)4142c9274b6bSCho, Yu-Chen static DisasJumpType op_stctg(DisasContext *s, DisasOps *o)
4143c9274b6bSCho, Yu-Chen {
4144f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4145f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
4146f1ea739bSRichard Henderson
4147ad75a51eSRichard Henderson gen_helper_stctg(tcg_env, r1, o->in2, r3);
4148c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4149c9274b6bSCho, Yu-Chen }
4150c9274b6bSCho, Yu-Chen
op_stctl(DisasContext * s,DisasOps * o)4151c9274b6bSCho, Yu-Chen static DisasJumpType op_stctl(DisasContext *s, DisasOps *o)
4152c9274b6bSCho, Yu-Chen {
4153f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4154f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
4155f1ea739bSRichard Henderson
4156ad75a51eSRichard Henderson gen_helper_stctl(tcg_env, r1, o->in2, r3);
4157c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4158c9274b6bSCho, Yu-Chen }
4159c9274b6bSCho, Yu-Chen
op_stidp(DisasContext * s,DisasOps * o)4160c9274b6bSCho, Yu-Chen static DisasJumpType op_stidp(DisasContext *s, DisasOps *o)
4161c9274b6bSCho, Yu-Chen {
4162ad75a51eSRichard Henderson tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, cpuid));
4163c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4164c9274b6bSCho, Yu-Chen }
4165c9274b6bSCho, Yu-Chen
op_spt(DisasContext * s,DisasOps * o)4166c9274b6bSCho, Yu-Chen static DisasJumpType op_spt(DisasContext *s, DisasOps *o)
4167c9274b6bSCho, Yu-Chen {
4168ad75a51eSRichard Henderson gen_helper_spt(tcg_env, o->in2);
4169c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4170c9274b6bSCho, Yu-Chen }
4171c9274b6bSCho, Yu-Chen
op_stfl(DisasContext * s,DisasOps * o)4172c9274b6bSCho, Yu-Chen static DisasJumpType op_stfl(DisasContext *s, DisasOps *o)
4173c9274b6bSCho, Yu-Chen {
4174ad75a51eSRichard Henderson gen_helper_stfl(tcg_env);
4175c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4176c9274b6bSCho, Yu-Chen }
4177c9274b6bSCho, Yu-Chen
op_stpt(DisasContext * s,DisasOps * o)4178c9274b6bSCho, Yu-Chen static DisasJumpType op_stpt(DisasContext *s, DisasOps *o)
4179c9274b6bSCho, Yu-Chen {
4180ad75a51eSRichard Henderson gen_helper_stpt(o->out, tcg_env);
4181c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4182c9274b6bSCho, Yu-Chen }
4183c9274b6bSCho, Yu-Chen
op_stsi(DisasContext * s,DisasOps * o)4184c9274b6bSCho, Yu-Chen static DisasJumpType op_stsi(DisasContext *s, DisasOps *o)
4185c9274b6bSCho, Yu-Chen {
4186ad75a51eSRichard Henderson gen_helper_stsi(cc_op, tcg_env, o->in2, regs[0], regs[1]);
4187c9274b6bSCho, Yu-Chen set_cc_static(s);
4188c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4189c9274b6bSCho, Yu-Chen }
4190c9274b6bSCho, Yu-Chen
op_spx(DisasContext * s,DisasOps * o)4191c9274b6bSCho, Yu-Chen static DisasJumpType op_spx(DisasContext *s, DisasOps *o)
4192c9274b6bSCho, Yu-Chen {
4193ad75a51eSRichard Henderson gen_helper_spx(tcg_env, o->in2);
4194c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4195c9274b6bSCho, Yu-Chen }
4196c9274b6bSCho, Yu-Chen
op_xsch(DisasContext * s,DisasOps * o)4197c9274b6bSCho, Yu-Chen static DisasJumpType op_xsch(DisasContext *s, DisasOps *o)
4198c9274b6bSCho, Yu-Chen {
4199ad75a51eSRichard Henderson gen_helper_xsch(tcg_env, regs[1]);
4200c9274b6bSCho, Yu-Chen set_cc_static(s);
4201c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4202c9274b6bSCho, Yu-Chen }
4203c9274b6bSCho, Yu-Chen
op_csch(DisasContext * s,DisasOps * o)4204c9274b6bSCho, Yu-Chen static DisasJumpType op_csch(DisasContext *s, DisasOps *o)
4205c9274b6bSCho, Yu-Chen {
4206ad75a51eSRichard Henderson gen_helper_csch(tcg_env, regs[1]);
4207c9274b6bSCho, Yu-Chen set_cc_static(s);
4208c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4209c9274b6bSCho, Yu-Chen }
4210c9274b6bSCho, Yu-Chen
op_hsch(DisasContext * s,DisasOps * o)4211c9274b6bSCho, Yu-Chen static DisasJumpType op_hsch(DisasContext *s, DisasOps *o)
4212c9274b6bSCho, Yu-Chen {
4213ad75a51eSRichard Henderson gen_helper_hsch(tcg_env, regs[1]);
4214c9274b6bSCho, Yu-Chen set_cc_static(s);
4215c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4216c9274b6bSCho, Yu-Chen }
4217c9274b6bSCho, Yu-Chen
op_msch(DisasContext * s,DisasOps * o)4218c9274b6bSCho, Yu-Chen static DisasJumpType op_msch(DisasContext *s, DisasOps *o)
4219c9274b6bSCho, Yu-Chen {
4220ad75a51eSRichard Henderson gen_helper_msch(tcg_env, regs[1], o->in2);
4221c9274b6bSCho, Yu-Chen set_cc_static(s);
4222c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4223c9274b6bSCho, Yu-Chen }
4224c9274b6bSCho, Yu-Chen
op_rchp(DisasContext * s,DisasOps * o)4225c9274b6bSCho, Yu-Chen static DisasJumpType op_rchp(DisasContext *s, DisasOps *o)
4226c9274b6bSCho, Yu-Chen {
4227ad75a51eSRichard Henderson gen_helper_rchp(tcg_env, regs[1]);
4228c9274b6bSCho, Yu-Chen set_cc_static(s);
4229c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4230c9274b6bSCho, Yu-Chen }
4231c9274b6bSCho, Yu-Chen
op_rsch(DisasContext * s,DisasOps * o)4232c9274b6bSCho, Yu-Chen static DisasJumpType op_rsch(DisasContext *s, DisasOps *o)
4233c9274b6bSCho, Yu-Chen {
4234ad75a51eSRichard Henderson gen_helper_rsch(tcg_env, regs[1]);
4235c9274b6bSCho, Yu-Chen set_cc_static(s);
4236c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4237c9274b6bSCho, Yu-Chen }
4238c9274b6bSCho, Yu-Chen
op_sal(DisasContext * s,DisasOps * o)4239c9274b6bSCho, Yu-Chen static DisasJumpType op_sal(DisasContext *s, DisasOps *o)
4240c9274b6bSCho, Yu-Chen {
4241ad75a51eSRichard Henderson gen_helper_sal(tcg_env, regs[1]);
4242c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4243c9274b6bSCho, Yu-Chen }
4244c9274b6bSCho, Yu-Chen
op_schm(DisasContext * s,DisasOps * o)4245c9274b6bSCho, Yu-Chen static DisasJumpType op_schm(DisasContext *s, DisasOps *o)
4246c9274b6bSCho, Yu-Chen {
4247ad75a51eSRichard Henderson gen_helper_schm(tcg_env, regs[1], regs[2], o->in2);
4248c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4249c9274b6bSCho, Yu-Chen }
4250c9274b6bSCho, Yu-Chen
op_siga(DisasContext * s,DisasOps * o)4251c9274b6bSCho, Yu-Chen static DisasJumpType op_siga(DisasContext *s, DisasOps *o)
4252c9274b6bSCho, Yu-Chen {
4253c9274b6bSCho, Yu-Chen /* From KVM code: Not provided, set CC = 3 for subchannel not operational */
4254c9274b6bSCho, Yu-Chen gen_op_movi_cc(s, 3);
4255c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4256c9274b6bSCho, Yu-Chen }
4257c9274b6bSCho, Yu-Chen
op_stcps(DisasContext * s,DisasOps * o)4258c9274b6bSCho, Yu-Chen static DisasJumpType op_stcps(DisasContext *s, DisasOps *o)
4259c9274b6bSCho, Yu-Chen {
4260c9274b6bSCho, Yu-Chen /* The instruction is suppressed if not provided. */
4261c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4262c9274b6bSCho, Yu-Chen }
4263c9274b6bSCho, Yu-Chen
op_ssch(DisasContext * s,DisasOps * o)4264c9274b6bSCho, Yu-Chen static DisasJumpType op_ssch(DisasContext *s, DisasOps *o)
4265c9274b6bSCho, Yu-Chen {
4266ad75a51eSRichard Henderson gen_helper_ssch(tcg_env, regs[1], o->in2);
4267c9274b6bSCho, Yu-Chen set_cc_static(s);
4268c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4269c9274b6bSCho, Yu-Chen }
4270c9274b6bSCho, Yu-Chen
op_stsch(DisasContext * s,DisasOps * o)4271c9274b6bSCho, Yu-Chen static DisasJumpType op_stsch(DisasContext *s, DisasOps *o)
4272c9274b6bSCho, Yu-Chen {
4273ad75a51eSRichard Henderson gen_helper_stsch(tcg_env, regs[1], o->in2);
4274c9274b6bSCho, Yu-Chen set_cc_static(s);
4275c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4276c9274b6bSCho, Yu-Chen }
4277c9274b6bSCho, Yu-Chen
op_stcrw(DisasContext * s,DisasOps * o)4278c9274b6bSCho, Yu-Chen static DisasJumpType op_stcrw(DisasContext *s, DisasOps *o)
4279c9274b6bSCho, Yu-Chen {
4280ad75a51eSRichard Henderson gen_helper_stcrw(tcg_env, o->in2);
4281c9274b6bSCho, Yu-Chen set_cc_static(s);
4282c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4283c9274b6bSCho, Yu-Chen }
4284c9274b6bSCho, Yu-Chen
op_tpi(DisasContext * s,DisasOps * o)4285c9274b6bSCho, Yu-Chen static DisasJumpType op_tpi(DisasContext *s, DisasOps *o)
4286c9274b6bSCho, Yu-Chen {
4287ad75a51eSRichard Henderson gen_helper_tpi(cc_op, tcg_env, o->addr1);
4288c9274b6bSCho, Yu-Chen set_cc_static(s);
4289c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4290c9274b6bSCho, Yu-Chen }
4291c9274b6bSCho, Yu-Chen
op_tsch(DisasContext * s,DisasOps * o)4292c9274b6bSCho, Yu-Chen static DisasJumpType op_tsch(DisasContext *s, DisasOps *o)
4293c9274b6bSCho, Yu-Chen {
4294ad75a51eSRichard Henderson gen_helper_tsch(tcg_env, regs[1], o->in2);
4295c9274b6bSCho, Yu-Chen set_cc_static(s);
4296c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4297c9274b6bSCho, Yu-Chen }
4298c9274b6bSCho, Yu-Chen
op_chsc(DisasContext * s,DisasOps * o)4299c9274b6bSCho, Yu-Chen static DisasJumpType op_chsc(DisasContext *s, DisasOps *o)
4300c9274b6bSCho, Yu-Chen {
4301ad75a51eSRichard Henderson gen_helper_chsc(tcg_env, o->in2);
4302c9274b6bSCho, Yu-Chen set_cc_static(s);
4303c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4304c9274b6bSCho, Yu-Chen }
4305c9274b6bSCho, Yu-Chen
op_stpx(DisasContext * s,DisasOps * o)4306c9274b6bSCho, Yu-Chen static DisasJumpType op_stpx(DisasContext *s, DisasOps *o)
4307c9274b6bSCho, Yu-Chen {
4308ad75a51eSRichard Henderson tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, psa));
4309c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(o->out, o->out, 0x7fffe000);
4310c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4311c9274b6bSCho, Yu-Chen }
4312c9274b6bSCho, Yu-Chen
op_stnosm(DisasContext * s,DisasOps * o)4313c9274b6bSCho, Yu-Chen static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
4314c9274b6bSCho, Yu-Chen {
4315c9274b6bSCho, Yu-Chen uint64_t i2 = get_field(s, i2);
4316c9274b6bSCho, Yu-Chen TCGv_i64 t;
4317c9274b6bSCho, Yu-Chen
4318c9274b6bSCho, Yu-Chen /* It is important to do what the instruction name says: STORE THEN.
4319c9274b6bSCho, Yu-Chen If we let the output hook perform the store then if we fault and
4320c9274b6bSCho, Yu-Chen restart, we'll have the wrong SYSTEM MASK in place. */
4321c9274b6bSCho, Yu-Chen t = tcg_temp_new_i64();
4322c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(t, psw_mask, 56);
4323e87027d0SRichard Henderson tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB);
4324c9274b6bSCho, Yu-Chen
4325c9274b6bSCho, Yu-Chen if (s->fields.op == 0xac) {
4326c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(psw_mask, psw_mask,
4327c9274b6bSCho, Yu-Chen (i2 << 56) | 0x00ffffffffffffffull);
4328c9274b6bSCho, Yu-Chen } else {
4329c9274b6bSCho, Yu-Chen tcg_gen_ori_i64(psw_mask, psw_mask, i2 << 56);
4330c9274b6bSCho, Yu-Chen }
4331c9274b6bSCho, Yu-Chen
4332199c42a6SIlya Leoshkevich gen_check_psw_mask(s);
4333199c42a6SIlya Leoshkevich
4334c9274b6bSCho, Yu-Chen /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
4335872e1379SRichard Henderson s->exit_to_mainloop = true;
4336872e1379SRichard Henderson return DISAS_TOO_MANY;
4337c9274b6bSCho, Yu-Chen }
4338c9274b6bSCho, Yu-Chen
op_stura(DisasContext * s,DisasOps * o)4339c9274b6bSCho, Yu-Chen static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
4340c9274b6bSCho, Yu-Chen {
4341c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->in1, o->in2, MMU_REAL_IDX, s->insn->data);
4342c9274b6bSCho, Yu-Chen
434362613ca0SRichard Henderson if (s->base.tb->flags & FLAG_MASK_PER_STORE_REAL) {
434431b2d4a1SRichard Henderson update_cc_op(s);
4345c9274b6bSCho, Yu-Chen update_psw_addr(s);
434631b2d4a1SRichard Henderson gen_helper_per_store_real(tcg_env, tcg_constant_i32(s->ilen));
434731b2d4a1SRichard Henderson return DISAS_NORETURN;
4348c9274b6bSCho, Yu-Chen }
4349c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4350c9274b6bSCho, Yu-Chen }
4351c9274b6bSCho, Yu-Chen #endif
4352c9274b6bSCho, Yu-Chen
op_stfle(DisasContext * s,DisasOps * o)4353c9274b6bSCho, Yu-Chen static DisasJumpType op_stfle(DisasContext *s, DisasOps *o)
4354c9274b6bSCho, Yu-Chen {
4355ad75a51eSRichard Henderson gen_helper_stfle(cc_op, tcg_env, o->in2);
4356c9274b6bSCho, Yu-Chen set_cc_static(s);
4357c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4358c9274b6bSCho, Yu-Chen }
4359c9274b6bSCho, Yu-Chen
op_st8(DisasContext * s,DisasOps * o)4360c9274b6bSCho, Yu-Chen static DisasJumpType op_st8(DisasContext *s, DisasOps *o)
4361c9274b6bSCho, Yu-Chen {
4362e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB);
4363c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4364c9274b6bSCho, Yu-Chen }
4365c9274b6bSCho, Yu-Chen
op_st16(DisasContext * s,DisasOps * o)4366c9274b6bSCho, Yu-Chen static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
4367c9274b6bSCho, Yu-Chen {
4368e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_TEUW);
4369c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4370c9274b6bSCho, Yu-Chen }
4371c9274b6bSCho, Yu-Chen
op_st32(DisasContext * s,DisasOps * o)4372c9274b6bSCho, Yu-Chen static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
4373c9274b6bSCho, Yu-Chen {
43742bc66225SIlya Leoshkevich tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s),
43752bc66225SIlya Leoshkevich MO_TEUL | s->insn->data);
4376c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4377c9274b6bSCho, Yu-Chen }
4378c9274b6bSCho, Yu-Chen
op_st64(DisasContext * s,DisasOps * o)4379c9274b6bSCho, Yu-Chen static DisasJumpType op_st64(DisasContext *s, DisasOps *o)
4380c9274b6bSCho, Yu-Chen {
438139ad7344SIlya Leoshkevich tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s),
438239ad7344SIlya Leoshkevich MO_TEUQ | s->insn->data);
4383c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4384c9274b6bSCho, Yu-Chen }
4385c9274b6bSCho, Yu-Chen
op_stam(DisasContext * s,DisasOps * o)4386c9274b6bSCho, Yu-Chen static DisasJumpType op_stam(DisasContext *s, DisasOps *o)
4387c9274b6bSCho, Yu-Chen {
4388f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4389f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
4390f1ea739bSRichard Henderson
4391ad75a51eSRichard Henderson gen_helper_stam(tcg_env, r1, o->in2, r3);
4392c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4393c9274b6bSCho, Yu-Chen }
4394c9274b6bSCho, Yu-Chen
op_stcm(DisasContext * s,DisasOps * o)4395c9274b6bSCho, Yu-Chen static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
4396c9274b6bSCho, Yu-Chen {
4397c9274b6bSCho, Yu-Chen int m3 = get_field(s, m3);
4398c9274b6bSCho, Yu-Chen int pos, base = s->insn->data;
4399c9274b6bSCho, Yu-Chen TCGv_i64 tmp = tcg_temp_new_i64();
4400c9274b6bSCho, Yu-Chen
4401c9274b6bSCho, Yu-Chen pos = base + ctz32(m3) * 8;
4402c9274b6bSCho, Yu-Chen switch (m3) {
4403c9274b6bSCho, Yu-Chen case 0xf:
4404c9274b6bSCho, Yu-Chen /* Effectively a 32-bit store. */
4405c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(tmp, o->in1, pos);
4406e87027d0SRichard Henderson tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUL);
4407c9274b6bSCho, Yu-Chen break;
4408c9274b6bSCho, Yu-Chen
4409c9274b6bSCho, Yu-Chen case 0xc:
4410c9274b6bSCho, Yu-Chen case 0x6:
4411c9274b6bSCho, Yu-Chen case 0x3:
4412c9274b6bSCho, Yu-Chen /* Effectively a 16-bit store. */
4413c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(tmp, o->in1, pos);
4414e87027d0SRichard Henderson tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_TEUW);
4415c9274b6bSCho, Yu-Chen break;
4416c9274b6bSCho, Yu-Chen
4417c9274b6bSCho, Yu-Chen case 0x8:
4418c9274b6bSCho, Yu-Chen case 0x4:
4419c9274b6bSCho, Yu-Chen case 0x2:
4420c9274b6bSCho, Yu-Chen case 0x1:
4421c9274b6bSCho, Yu-Chen /* Effectively an 8-bit store. */
4422c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(tmp, o->in1, pos);
4423e87027d0SRichard Henderson tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
4424c9274b6bSCho, Yu-Chen break;
4425c9274b6bSCho, Yu-Chen
4426c9274b6bSCho, Yu-Chen default:
4427c9274b6bSCho, Yu-Chen /* This is going to be a sequence of shifts and stores. */
4428c9274b6bSCho, Yu-Chen pos = base + 32 - 8;
4429c9274b6bSCho, Yu-Chen while (m3) {
4430c9274b6bSCho, Yu-Chen if (m3 & 0x8) {
4431c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(tmp, o->in1, pos);
4432e87027d0SRichard Henderson tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
4433c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->in2, o->in2, 1);
4434c9274b6bSCho, Yu-Chen }
4435c9274b6bSCho, Yu-Chen m3 = (m3 << 1) & 0xf;
4436c9274b6bSCho, Yu-Chen pos -= 8;
4437c9274b6bSCho, Yu-Chen }
4438c9274b6bSCho, Yu-Chen break;
4439c9274b6bSCho, Yu-Chen }
4440c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4441c9274b6bSCho, Yu-Chen }
4442c9274b6bSCho, Yu-Chen
op_stm(DisasContext * s,DisasOps * o)4443c9274b6bSCho, Yu-Chen static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
4444c9274b6bSCho, Yu-Chen {
4445c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
4446c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
4447c9274b6bSCho, Yu-Chen int size = s->insn->data;
4448f1ea739bSRichard Henderson TCGv_i64 tsize = tcg_constant_i64(size);
4449c9274b6bSCho, Yu-Chen
4450c9274b6bSCho, Yu-Chen while (1) {
4451e87027d0SRichard Henderson tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s),
4452e87027d0SRichard Henderson size == 8 ? MO_TEUQ : MO_TEUL);
4453c9274b6bSCho, Yu-Chen if (r1 == r3) {
4454c9274b6bSCho, Yu-Chen break;
4455c9274b6bSCho, Yu-Chen }
4456c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->in2, o->in2, tsize);
4457c9274b6bSCho, Yu-Chen r1 = (r1 + 1) & 15;
4458c9274b6bSCho, Yu-Chen }
4459c9274b6bSCho, Yu-Chen
4460c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4461c9274b6bSCho, Yu-Chen }
4462c9274b6bSCho, Yu-Chen
op_stmh(DisasContext * s,DisasOps * o)4463c9274b6bSCho, Yu-Chen static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
4464c9274b6bSCho, Yu-Chen {
4465c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
4466c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
4467c9274b6bSCho, Yu-Chen TCGv_i64 t = tcg_temp_new_i64();
4468f1ea739bSRichard Henderson TCGv_i64 t4 = tcg_constant_i64(4);
4469f1ea739bSRichard Henderson TCGv_i64 t32 = tcg_constant_i64(32);
4470c9274b6bSCho, Yu-Chen
4471c9274b6bSCho, Yu-Chen while (1) {
4472c9274b6bSCho, Yu-Chen tcg_gen_shl_i64(t, regs[r1], t32);
4473e87027d0SRichard Henderson tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_TEUL);
4474c9274b6bSCho, Yu-Chen if (r1 == r3) {
4475c9274b6bSCho, Yu-Chen break;
4476c9274b6bSCho, Yu-Chen }
4477c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->in2, o->in2, t4);
4478c9274b6bSCho, Yu-Chen r1 = (r1 + 1) & 15;
4479c9274b6bSCho, Yu-Chen }
4480c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4481c9274b6bSCho, Yu-Chen }
4482c9274b6bSCho, Yu-Chen
op_stpq(DisasContext * s,DisasOps * o)4483c9274b6bSCho, Yu-Chen static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
4484c9274b6bSCho, Yu-Chen {
4485d54a20b9SRichard Henderson TCGv_i128 t16 = tcg_temp_new_i128();
4486d54a20b9SRichard Henderson
4487d54a20b9SRichard Henderson tcg_gen_concat_i64_i128(t16, o->out2, o->out);
4488d54a20b9SRichard Henderson tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s),
4489d54a20b9SRichard Henderson MO_TE | MO_128 | MO_ALIGN);
4490c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4491c9274b6bSCho, Yu-Chen }
4492c9274b6bSCho, Yu-Chen
op_srst(DisasContext * s,DisasOps * o)4493c9274b6bSCho, Yu-Chen static DisasJumpType op_srst(DisasContext *s, DisasOps *o)
4494c9274b6bSCho, Yu-Chen {
4495f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4496f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4497c9274b6bSCho, Yu-Chen
4498ad75a51eSRichard Henderson gen_helper_srst(tcg_env, r1, r2);
4499c9274b6bSCho, Yu-Chen set_cc_static(s);
4500c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4501c9274b6bSCho, Yu-Chen }
4502c9274b6bSCho, Yu-Chen
op_srstu(DisasContext * s,DisasOps * o)4503c9274b6bSCho, Yu-Chen static DisasJumpType op_srstu(DisasContext *s, DisasOps *o)
4504c9274b6bSCho, Yu-Chen {
4505f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4506f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4507c9274b6bSCho, Yu-Chen
4508ad75a51eSRichard Henderson gen_helper_srstu(tcg_env, r1, r2);
4509c9274b6bSCho, Yu-Chen set_cc_static(s);
4510c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4511c9274b6bSCho, Yu-Chen }
4512c9274b6bSCho, Yu-Chen
op_sub(DisasContext * s,DisasOps * o)4513c9274b6bSCho, Yu-Chen static DisasJumpType op_sub(DisasContext *s, DisasOps *o)
4514c9274b6bSCho, Yu-Chen {
4515c9274b6bSCho, Yu-Chen tcg_gen_sub_i64(o->out, o->in1, o->in2);
4516c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4517c9274b6bSCho, Yu-Chen }
4518c9274b6bSCho, Yu-Chen
op_subu64(DisasContext * s,DisasOps * o)4519c9274b6bSCho, Yu-Chen static DisasJumpType op_subu64(DisasContext *s, DisasOps *o)
4520c9274b6bSCho, Yu-Chen {
4521c9274b6bSCho, Yu-Chen tcg_gen_movi_i64(cc_src, 0);
4522c9274b6bSCho, Yu-Chen tcg_gen_sub2_i64(o->out, cc_src, o->in1, cc_src, o->in2, cc_src);
4523c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4524c9274b6bSCho, Yu-Chen }
4525c9274b6bSCho, Yu-Chen
4526c9274b6bSCho, Yu-Chen /* Compute borrow (0, -1) into cc_src. */
compute_borrow(DisasContext * s)4527c9274b6bSCho, Yu-Chen static void compute_borrow(DisasContext *s)
4528c9274b6bSCho, Yu-Chen {
4529c9274b6bSCho, Yu-Chen switch (s->cc_op) {
4530c9274b6bSCho, Yu-Chen case CC_OP_SUBU:
4531c9274b6bSCho, Yu-Chen /* The borrow value is already in cc_src (0,-1). */
4532c9274b6bSCho, Yu-Chen break;
4533c9274b6bSCho, Yu-Chen default:
4534c9274b6bSCho, Yu-Chen gen_op_calc_cc(s);
4535c9274b6bSCho, Yu-Chen /* fall through */
4536c9274b6bSCho, Yu-Chen case CC_OP_STATIC:
4537c9274b6bSCho, Yu-Chen /* The carry flag is the msb of CC; compute into cc_src. */
4538c9274b6bSCho, Yu-Chen tcg_gen_extu_i32_i64(cc_src, cc_op);
4539c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(cc_src, cc_src, 1);
4540c9274b6bSCho, Yu-Chen /* fall through */
4541c9274b6bSCho, Yu-Chen case CC_OP_ADDU:
4542c9274b6bSCho, Yu-Chen /* Convert carry (1,0) to borrow (0,-1). */
4543c9274b6bSCho, Yu-Chen tcg_gen_subi_i64(cc_src, cc_src, 1);
4544c9274b6bSCho, Yu-Chen break;
4545c9274b6bSCho, Yu-Chen }
4546c9274b6bSCho, Yu-Chen }
4547c9274b6bSCho, Yu-Chen
op_subb32(DisasContext * s,DisasOps * o)4548c9274b6bSCho, Yu-Chen static DisasJumpType op_subb32(DisasContext *s, DisasOps *o)
4549c9274b6bSCho, Yu-Chen {
4550c9274b6bSCho, Yu-Chen compute_borrow(s);
4551c9274b6bSCho, Yu-Chen
4552c9274b6bSCho, Yu-Chen /* Borrow is {0, -1}, so add to subtract. */
4553c9274b6bSCho, Yu-Chen tcg_gen_add_i64(o->out, o->in1, cc_src);
4554c9274b6bSCho, Yu-Chen tcg_gen_sub_i64(o->out, o->out, o->in2);
4555c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4556c9274b6bSCho, Yu-Chen }
4557c9274b6bSCho, Yu-Chen
op_subb64(DisasContext * s,DisasOps * o)4558c9274b6bSCho, Yu-Chen static DisasJumpType op_subb64(DisasContext *s, DisasOps *o)
4559c9274b6bSCho, Yu-Chen {
4560c9274b6bSCho, Yu-Chen compute_borrow(s);
4561c9274b6bSCho, Yu-Chen
4562c9274b6bSCho, Yu-Chen /*
4563c9274b6bSCho, Yu-Chen * Borrow is {0, -1}, so add to subtract; replicate the
4564c9274b6bSCho, Yu-Chen * borrow input to produce 128-bit -1 for the addition.
4565c9274b6bSCho, Yu-Chen */
4566f1ea739bSRichard Henderson TCGv_i64 zero = tcg_constant_i64(0);
4567c9274b6bSCho, Yu-Chen tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, cc_src);
4568c9274b6bSCho, Yu-Chen tcg_gen_sub2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero);
4569c9274b6bSCho, Yu-Chen
4570c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4571c9274b6bSCho, Yu-Chen }
4572c9274b6bSCho, Yu-Chen
op_svc(DisasContext * s,DisasOps * o)4573c9274b6bSCho, Yu-Chen static DisasJumpType op_svc(DisasContext *s, DisasOps *o)
4574c9274b6bSCho, Yu-Chen {
4575c9274b6bSCho, Yu-Chen TCGv_i32 t;
4576c9274b6bSCho, Yu-Chen
4577c9274b6bSCho, Yu-Chen update_psw_addr(s);
4578c9274b6bSCho, Yu-Chen update_cc_op(s);
4579c9274b6bSCho, Yu-Chen
4580f1ea739bSRichard Henderson t = tcg_constant_i32(get_field(s, i1) & 0xff);
4581ad75a51eSRichard Henderson tcg_gen_st_i32(t, tcg_env, offsetof(CPUS390XState, int_svc_code));
4582c9274b6bSCho, Yu-Chen
4583f1ea739bSRichard Henderson t = tcg_constant_i32(s->ilen);
4584ad75a51eSRichard Henderson tcg_gen_st_i32(t, tcg_env, offsetof(CPUS390XState, int_svc_ilen));
4585c9274b6bSCho, Yu-Chen
4586c9274b6bSCho, Yu-Chen gen_exception(EXCP_SVC);
4587c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
4588c9274b6bSCho, Yu-Chen }
4589c9274b6bSCho, Yu-Chen
op_tam(DisasContext * s,DisasOps * o)4590c9274b6bSCho, Yu-Chen static DisasJumpType op_tam(DisasContext *s, DisasOps *o)
4591c9274b6bSCho, Yu-Chen {
4592c9274b6bSCho, Yu-Chen int cc = 0;
4593c9274b6bSCho, Yu-Chen
4594c9274b6bSCho, Yu-Chen cc |= (s->base.tb->flags & FLAG_MASK_64) ? 2 : 0;
4595c9274b6bSCho, Yu-Chen cc |= (s->base.tb->flags & FLAG_MASK_32) ? 1 : 0;
4596c9274b6bSCho, Yu-Chen gen_op_movi_cc(s, cc);
4597c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4598c9274b6bSCho, Yu-Chen }
4599c9274b6bSCho, Yu-Chen
op_tceb(DisasContext * s,DisasOps * o)4600c9274b6bSCho, Yu-Chen static DisasJumpType op_tceb(DisasContext *s, DisasOps *o)
4601c9274b6bSCho, Yu-Chen {
4602ad75a51eSRichard Henderson gen_helper_tceb(cc_op, tcg_env, o->in1, o->in2);
4603c9274b6bSCho, Yu-Chen set_cc_static(s);
4604c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4605c9274b6bSCho, Yu-Chen }
4606c9274b6bSCho, Yu-Chen
op_tcdb(DisasContext * s,DisasOps * o)4607c9274b6bSCho, Yu-Chen static DisasJumpType op_tcdb(DisasContext *s, DisasOps *o)
4608c9274b6bSCho, Yu-Chen {
4609ad75a51eSRichard Henderson gen_helper_tcdb(cc_op, tcg_env, o->in1, o->in2);
4610c9274b6bSCho, Yu-Chen set_cc_static(s);
4611c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4612c9274b6bSCho, Yu-Chen }
4613c9274b6bSCho, Yu-Chen
op_tcxb(DisasContext * s,DisasOps * o)4614c9274b6bSCho, Yu-Chen static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o)
4615c9274b6bSCho, Yu-Chen {
4616ad75a51eSRichard Henderson gen_helper_tcxb(cc_op, tcg_env, o->in1_128, o->in2);
4617c9274b6bSCho, Yu-Chen set_cc_static(s);
4618c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4619c9274b6bSCho, Yu-Chen }
4620c9274b6bSCho, Yu-Chen
4621c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
4622c9274b6bSCho, Yu-Chen
op_testblock(DisasContext * s,DisasOps * o)4623c9274b6bSCho, Yu-Chen static DisasJumpType op_testblock(DisasContext *s, DisasOps *o)
4624c9274b6bSCho, Yu-Chen {
4625ad75a51eSRichard Henderson gen_helper_testblock(cc_op, tcg_env, o->in2);
4626c9274b6bSCho, Yu-Chen set_cc_static(s);
4627c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4628c9274b6bSCho, Yu-Chen }
4629c9274b6bSCho, Yu-Chen
op_tprot(DisasContext * s,DisasOps * o)4630c9274b6bSCho, Yu-Chen static DisasJumpType op_tprot(DisasContext *s, DisasOps *o)
4631c9274b6bSCho, Yu-Chen {
4632ad75a51eSRichard Henderson gen_helper_tprot(cc_op, tcg_env, o->addr1, o->in2);
4633c9274b6bSCho, Yu-Chen set_cc_static(s);
4634c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4635c9274b6bSCho, Yu-Chen }
4636c9274b6bSCho, Yu-Chen
4637c9274b6bSCho, Yu-Chen #endif
4638c9274b6bSCho, Yu-Chen
op_tp(DisasContext * s,DisasOps * o)4639c9274b6bSCho, Yu-Chen static DisasJumpType op_tp(DisasContext *s, DisasOps *o)
4640c9274b6bSCho, Yu-Chen {
4641f1ea739bSRichard Henderson TCGv_i32 l1 = tcg_constant_i32(get_field(s, l1) + 1);
4642f1ea739bSRichard Henderson
4643ad75a51eSRichard Henderson gen_helper_tp(cc_op, tcg_env, o->addr1, l1);
4644c9274b6bSCho, Yu-Chen set_cc_static(s);
4645c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4646c9274b6bSCho, Yu-Chen }
4647c9274b6bSCho, Yu-Chen
op_tr(DisasContext * s,DisasOps * o)4648c9274b6bSCho, Yu-Chen static DisasJumpType op_tr(DisasContext *s, DisasOps *o)
4649c9274b6bSCho, Yu-Chen {
4650f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
4651f1ea739bSRichard Henderson
4652ad75a51eSRichard Henderson gen_helper_tr(tcg_env, l, o->addr1, o->in2);
4653c9274b6bSCho, Yu-Chen set_cc_static(s);
4654c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4655c9274b6bSCho, Yu-Chen }
4656c9274b6bSCho, Yu-Chen
op_tre(DisasContext * s,DisasOps * o)4657c9274b6bSCho, Yu-Chen static DisasJumpType op_tre(DisasContext *s, DisasOps *o)
4658c9274b6bSCho, Yu-Chen {
4659ef45f5b9SRichard Henderson TCGv_i128 pair = tcg_temp_new_i128();
4660ef45f5b9SRichard Henderson
4661ad75a51eSRichard Henderson gen_helper_tre(pair, tcg_env, o->out, o->out2, o->in2);
4662ef45f5b9SRichard Henderson tcg_gen_extr_i128_i64(o->out2, o->out, pair);
4663c9274b6bSCho, Yu-Chen set_cc_static(s);
4664c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4665c9274b6bSCho, Yu-Chen }
4666c9274b6bSCho, Yu-Chen
op_trt(DisasContext * s,DisasOps * o)4667c9274b6bSCho, Yu-Chen static DisasJumpType op_trt(DisasContext *s, DisasOps *o)
4668c9274b6bSCho, Yu-Chen {
4669f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
4670f1ea739bSRichard Henderson
4671ad75a51eSRichard Henderson gen_helper_trt(cc_op, tcg_env, l, o->addr1, o->in2);
4672c9274b6bSCho, Yu-Chen set_cc_static(s);
4673c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4674c9274b6bSCho, Yu-Chen }
4675c9274b6bSCho, Yu-Chen
op_trtr(DisasContext * s,DisasOps * o)4676c9274b6bSCho, Yu-Chen static DisasJumpType op_trtr(DisasContext *s, DisasOps *o)
4677c9274b6bSCho, Yu-Chen {
4678f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
4679f1ea739bSRichard Henderson
4680ad75a51eSRichard Henderson gen_helper_trtr(cc_op, tcg_env, l, o->addr1, o->in2);
4681c9274b6bSCho, Yu-Chen set_cc_static(s);
4682c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4683c9274b6bSCho, Yu-Chen }
4684c9274b6bSCho, Yu-Chen
op_trXX(DisasContext * s,DisasOps * o)4685c9274b6bSCho, Yu-Chen static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
4686c9274b6bSCho, Yu-Chen {
4687f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4688f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4689f1ea739bSRichard Henderson TCGv_i32 sizes = tcg_constant_i32(s->insn->opc & 3);
4690c9274b6bSCho, Yu-Chen TCGv_i32 tst = tcg_temp_new_i32();
4691c9274b6bSCho, Yu-Chen int m3 = get_field(s, m3);
4692c9274b6bSCho, Yu-Chen
4693c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {
4694c9274b6bSCho, Yu-Chen m3 = 0;
4695c9274b6bSCho, Yu-Chen }
4696c9274b6bSCho, Yu-Chen if (m3 & 1) {
4697c9274b6bSCho, Yu-Chen tcg_gen_movi_i32(tst, -1);
4698c9274b6bSCho, Yu-Chen } else {
4699c9274b6bSCho, Yu-Chen tcg_gen_extrl_i64_i32(tst, regs[0]);
4700c9274b6bSCho, Yu-Chen if (s->insn->opc & 3) {
4701c9274b6bSCho, Yu-Chen tcg_gen_ext8u_i32(tst, tst);
4702c9274b6bSCho, Yu-Chen } else {
4703c9274b6bSCho, Yu-Chen tcg_gen_ext16u_i32(tst, tst);
4704c9274b6bSCho, Yu-Chen }
4705c9274b6bSCho, Yu-Chen }
4706ad75a51eSRichard Henderson gen_helper_trXX(cc_op, tcg_env, r1, r2, tst, sizes);
4707c9274b6bSCho, Yu-Chen
4708c9274b6bSCho, Yu-Chen set_cc_static(s);
4709c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4710c9274b6bSCho, Yu-Chen }
4711c9274b6bSCho, Yu-Chen
op_ts(DisasContext * s,DisasOps * o)4712c9274b6bSCho, Yu-Chen static DisasJumpType op_ts(DisasContext *s, DisasOps *o)
4713c9274b6bSCho, Yu-Chen {
4714272fba97SIdo Plat TCGv_i32 ff = tcg_constant_i32(0xff);
4715272fba97SIdo Plat TCGv_i32 t1 = tcg_temp_new_i32();
4716f1ea739bSRichard Henderson
4717272fba97SIdo Plat tcg_gen_atomic_xchg_i32(t1, o->in2, ff, get_mem_index(s), MO_UB);
4718c9274b6bSCho, Yu-Chen tcg_gen_extract_i32(cc_op, t1, 7, 1);
4719c9274b6bSCho, Yu-Chen set_cc_static(s);
4720c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4721c9274b6bSCho, Yu-Chen }
4722c9274b6bSCho, Yu-Chen
op_unpk(DisasContext * s,DisasOps * o)4723c9274b6bSCho, Yu-Chen static DisasJumpType op_unpk(DisasContext *s, DisasOps *o)
4724c9274b6bSCho, Yu-Chen {
4725f1ea739bSRichard Henderson TCGv_i32 l = tcg_constant_i32(get_field(s, l1));
4726f1ea739bSRichard Henderson
4727ad75a51eSRichard Henderson gen_helper_unpk(tcg_env, l, o->addr1, o->in2);
4728c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4729c9274b6bSCho, Yu-Chen }
4730c9274b6bSCho, Yu-Chen
op_unpka(DisasContext * s,DisasOps * o)4731c9274b6bSCho, Yu-Chen static DisasJumpType op_unpka(DisasContext *s, DisasOps *o)
4732c9274b6bSCho, Yu-Chen {
4733c9274b6bSCho, Yu-Chen int l1 = get_field(s, l1) + 1;
4734c9274b6bSCho, Yu-Chen TCGv_i32 l;
4735c9274b6bSCho, Yu-Chen
4736c9274b6bSCho, Yu-Chen /* The length must not exceed 32 bytes. */
4737c9274b6bSCho, Yu-Chen if (l1 > 32) {
4738c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
4739c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
4740c9274b6bSCho, Yu-Chen }
4741f1ea739bSRichard Henderson l = tcg_constant_i32(l1);
4742ad75a51eSRichard Henderson gen_helper_unpka(cc_op, tcg_env, o->addr1, l, o->in2);
4743c9274b6bSCho, Yu-Chen set_cc_static(s);
4744c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4745c9274b6bSCho, Yu-Chen }
4746c9274b6bSCho, Yu-Chen
op_unpku(DisasContext * s,DisasOps * o)4747c9274b6bSCho, Yu-Chen static DisasJumpType op_unpku(DisasContext *s, DisasOps *o)
4748c9274b6bSCho, Yu-Chen {
4749c9274b6bSCho, Yu-Chen int l1 = get_field(s, l1) + 1;
4750c9274b6bSCho, Yu-Chen TCGv_i32 l;
4751c9274b6bSCho, Yu-Chen
4752c9274b6bSCho, Yu-Chen /* The length must be even and should not exceed 64 bytes. */
4753c9274b6bSCho, Yu-Chen if ((l1 & 1) || (l1 > 64)) {
4754c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
4755c9274b6bSCho, Yu-Chen return DISAS_NORETURN;
4756c9274b6bSCho, Yu-Chen }
4757f1ea739bSRichard Henderson l = tcg_constant_i32(l1);
4758ad75a51eSRichard Henderson gen_helper_unpku(cc_op, tcg_env, o->addr1, l, o->in2);
4759c9274b6bSCho, Yu-Chen set_cc_static(s);
4760c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4761c9274b6bSCho, Yu-Chen }
4762c9274b6bSCho, Yu-Chen
4763c9274b6bSCho, Yu-Chen
op_xc(DisasContext * s,DisasOps * o)4764c9274b6bSCho, Yu-Chen static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
4765c9274b6bSCho, Yu-Chen {
4766c9274b6bSCho, Yu-Chen int d1 = get_field(s, d1);
4767c9274b6bSCho, Yu-Chen int d2 = get_field(s, d2);
4768c9274b6bSCho, Yu-Chen int b1 = get_field(s, b1);
4769c9274b6bSCho, Yu-Chen int b2 = get_field(s, b2);
4770c9274b6bSCho, Yu-Chen int l = get_field(s, l1);
4771c9274b6bSCho, Yu-Chen TCGv_i32 t32;
4772c9274b6bSCho, Yu-Chen
4773c9274b6bSCho, Yu-Chen o->addr1 = get_address(s, 0, b1, d1);
4774c9274b6bSCho, Yu-Chen
4775c9274b6bSCho, Yu-Chen /* If the addresses are identical, this is a store/memset of zero. */
4776c9274b6bSCho, Yu-Chen if (b1 == b2 && d1 == d2 && (l + 1) <= 32) {
4777f1ea739bSRichard Henderson o->in2 = tcg_constant_i64(0);
4778c9274b6bSCho, Yu-Chen
4779c9274b6bSCho, Yu-Chen l++;
4780c9274b6bSCho, Yu-Chen while (l >= 8) {
4781e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UQ);
4782c9274b6bSCho, Yu-Chen l -= 8;
4783c9274b6bSCho, Yu-Chen if (l > 0) {
4784c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->addr1, o->addr1, 8);
4785c9274b6bSCho, Yu-Chen }
4786c9274b6bSCho, Yu-Chen }
4787c9274b6bSCho, Yu-Chen if (l >= 4) {
4788e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UL);
4789c9274b6bSCho, Yu-Chen l -= 4;
4790c9274b6bSCho, Yu-Chen if (l > 0) {
4791c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->addr1, o->addr1, 4);
4792c9274b6bSCho, Yu-Chen }
4793c9274b6bSCho, Yu-Chen }
4794c9274b6bSCho, Yu-Chen if (l >= 2) {
4795e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UW);
4796c9274b6bSCho, Yu-Chen l -= 2;
4797c9274b6bSCho, Yu-Chen if (l > 0) {
4798c9274b6bSCho, Yu-Chen tcg_gen_addi_i64(o->addr1, o->addr1, 2);
4799c9274b6bSCho, Yu-Chen }
4800c9274b6bSCho, Yu-Chen }
4801c9274b6bSCho, Yu-Chen if (l) {
4802e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB);
4803c9274b6bSCho, Yu-Chen }
4804c9274b6bSCho, Yu-Chen gen_op_movi_cc(s, 0);
4805c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4806c9274b6bSCho, Yu-Chen }
4807c9274b6bSCho, Yu-Chen
4808c9274b6bSCho, Yu-Chen /* But in general we'll defer to a helper. */
4809c9274b6bSCho, Yu-Chen o->in2 = get_address(s, 0, b2, d2);
4810f1ea739bSRichard Henderson t32 = tcg_constant_i32(l);
4811ad75a51eSRichard Henderson gen_helper_xc(cc_op, tcg_env, t32, o->addr1, o->in2);
4812c9274b6bSCho, Yu-Chen set_cc_static(s);
4813c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4814c9274b6bSCho, Yu-Chen }
4815c9274b6bSCho, Yu-Chen
op_xor(DisasContext * s,DisasOps * o)4816c9274b6bSCho, Yu-Chen static DisasJumpType op_xor(DisasContext *s, DisasOps *o)
4817c9274b6bSCho, Yu-Chen {
4818c9274b6bSCho, Yu-Chen tcg_gen_xor_i64(o->out, o->in1, o->in2);
4819c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4820c9274b6bSCho, Yu-Chen }
4821c9274b6bSCho, Yu-Chen
op_xori(DisasContext * s,DisasOps * o)4822c9274b6bSCho, Yu-Chen static DisasJumpType op_xori(DisasContext *s, DisasOps *o)
4823c9274b6bSCho, Yu-Chen {
4824c9274b6bSCho, Yu-Chen int shift = s->insn->data & 0xff;
4825c9274b6bSCho, Yu-Chen int size = s->insn->data >> 8;
4826c9274b6bSCho, Yu-Chen uint64_t mask = ((1ull << size) - 1) << shift;
4827ab9984bdSRichard Henderson TCGv_i64 t = tcg_temp_new_i64();
4828c9274b6bSCho, Yu-Chen
4829ab9984bdSRichard Henderson tcg_gen_shli_i64(t, o->in2, shift);
4830ab9984bdSRichard Henderson tcg_gen_xor_i64(o->out, o->in1, t);
4831c9274b6bSCho, Yu-Chen
4832c9274b6bSCho, Yu-Chen /* Produce the CC from only the bits manipulated. */
4833c9274b6bSCho, Yu-Chen tcg_gen_andi_i64(cc_dst, o->out, mask);
4834c9274b6bSCho, Yu-Chen set_cc_nz_u64(s, cc_dst);
4835c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4836c9274b6bSCho, Yu-Chen }
4837c9274b6bSCho, Yu-Chen
op_xi(DisasContext * s,DisasOps * o)4838c9274b6bSCho, Yu-Chen static DisasJumpType op_xi(DisasContext *s, DisasOps *o)
4839c9274b6bSCho, Yu-Chen {
4840c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
4841c9274b6bSCho, Yu-Chen
4842c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
4843c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->in1, o->addr1, get_mem_index(s), s->insn->data);
4844c9274b6bSCho, Yu-Chen } else {
4845c9274b6bSCho, Yu-Chen /* Perform the atomic operation in memory. */
4846c9274b6bSCho, Yu-Chen tcg_gen_atomic_fetch_xor_i64(o->in1, o->addr1, o->in2, get_mem_index(s),
4847c9274b6bSCho, Yu-Chen s->insn->data);
4848c9274b6bSCho, Yu-Chen }
4849c9274b6bSCho, Yu-Chen
4850c9274b6bSCho, Yu-Chen /* Recompute also for atomic case: needed for setting CC. */
4851c9274b6bSCho, Yu-Chen tcg_gen_xor_i64(o->out, o->in1, o->in2);
4852c9274b6bSCho, Yu-Chen
4853c9274b6bSCho, Yu-Chen if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2)) {
4854c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), s->insn->data);
4855c9274b6bSCho, Yu-Chen }
4856c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4857c9274b6bSCho, Yu-Chen }
4858c9274b6bSCho, Yu-Chen
op_zero(DisasContext * s,DisasOps * o)4859c9274b6bSCho, Yu-Chen static DisasJumpType op_zero(DisasContext *s, DisasOps *o)
4860c9274b6bSCho, Yu-Chen {
48615bd9790eSRichard Henderson o->out = tcg_constant_i64(0);
4862c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4863c9274b6bSCho, Yu-Chen }
4864c9274b6bSCho, Yu-Chen
op_zero2(DisasContext * s,DisasOps * o)4865c9274b6bSCho, Yu-Chen static DisasJumpType op_zero2(DisasContext *s, DisasOps *o)
4866c9274b6bSCho, Yu-Chen {
48675bd9790eSRichard Henderson o->out = tcg_constant_i64(0);
4868c9274b6bSCho, Yu-Chen o->out2 = o->out;
4869c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4870c9274b6bSCho, Yu-Chen }
4871c9274b6bSCho, Yu-Chen
4872c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
op_clp(DisasContext * s,DisasOps * o)4873c9274b6bSCho, Yu-Chen static DisasJumpType op_clp(DisasContext *s, DisasOps *o)
4874c9274b6bSCho, Yu-Chen {
4875f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4876c9274b6bSCho, Yu-Chen
4877ad75a51eSRichard Henderson gen_helper_clp(tcg_env, r2);
4878c9274b6bSCho, Yu-Chen set_cc_static(s);
4879c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4880c9274b6bSCho, Yu-Chen }
4881c9274b6bSCho, Yu-Chen
op_pcilg(DisasContext * s,DisasOps * o)4882c9274b6bSCho, Yu-Chen static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o)
4883c9274b6bSCho, Yu-Chen {
4884f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4885f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4886c9274b6bSCho, Yu-Chen
4887ad75a51eSRichard Henderson gen_helper_pcilg(tcg_env, r1, r2);
4888c9274b6bSCho, Yu-Chen set_cc_static(s);
4889c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4890c9274b6bSCho, Yu-Chen }
4891c9274b6bSCho, Yu-Chen
op_pcistg(DisasContext * s,DisasOps * o)4892c9274b6bSCho, Yu-Chen static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o)
4893c9274b6bSCho, Yu-Chen {
4894f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4895f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4896c9274b6bSCho, Yu-Chen
4897ad75a51eSRichard Henderson gen_helper_pcistg(tcg_env, r1, r2);
4898c9274b6bSCho, Yu-Chen set_cc_static(s);
4899c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4900c9274b6bSCho, Yu-Chen }
4901c9274b6bSCho, Yu-Chen
op_stpcifc(DisasContext * s,DisasOps * o)4902c9274b6bSCho, Yu-Chen static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o)
4903c9274b6bSCho, Yu-Chen {
4904f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4905f1ea739bSRichard Henderson TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
4906c9274b6bSCho, Yu-Chen
4907ad75a51eSRichard Henderson gen_helper_stpcifc(tcg_env, r1, o->addr1, ar);
4908c9274b6bSCho, Yu-Chen set_cc_static(s);
4909c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4910c9274b6bSCho, Yu-Chen }
4911c9274b6bSCho, Yu-Chen
op_sic(DisasContext * s,DisasOps * o)4912c9274b6bSCho, Yu-Chen static DisasJumpType op_sic(DisasContext *s, DisasOps *o)
4913c9274b6bSCho, Yu-Chen {
4914ad75a51eSRichard Henderson gen_helper_sic(tcg_env, o->in1, o->in2);
4915c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4916c9274b6bSCho, Yu-Chen }
4917c9274b6bSCho, Yu-Chen
op_rpcit(DisasContext * s,DisasOps * o)4918c9274b6bSCho, Yu-Chen static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o)
4919c9274b6bSCho, Yu-Chen {
4920f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4921f1ea739bSRichard Henderson TCGv_i32 r2 = tcg_constant_i32(get_field(s, r2));
4922c9274b6bSCho, Yu-Chen
4923ad75a51eSRichard Henderson gen_helper_rpcit(tcg_env, r1, r2);
4924c9274b6bSCho, Yu-Chen set_cc_static(s);
4925c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4926c9274b6bSCho, Yu-Chen }
4927c9274b6bSCho, Yu-Chen
op_pcistb(DisasContext * s,DisasOps * o)4928c9274b6bSCho, Yu-Chen static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o)
4929c9274b6bSCho, Yu-Chen {
4930f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4931f1ea739bSRichard Henderson TCGv_i32 r3 = tcg_constant_i32(get_field(s, r3));
4932f1ea739bSRichard Henderson TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
4933c9274b6bSCho, Yu-Chen
4934ad75a51eSRichard Henderson gen_helper_pcistb(tcg_env, r1, r3, o->addr1, ar);
4935c9274b6bSCho, Yu-Chen set_cc_static(s);
4936c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4937c9274b6bSCho, Yu-Chen }
4938c9274b6bSCho, Yu-Chen
op_mpcifc(DisasContext * s,DisasOps * o)4939c9274b6bSCho, Yu-Chen static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
4940c9274b6bSCho, Yu-Chen {
4941f1ea739bSRichard Henderson TCGv_i32 r1 = tcg_constant_i32(get_field(s, r1));
4942f1ea739bSRichard Henderson TCGv_i32 ar = tcg_constant_i32(get_field(s, b2));
4943c9274b6bSCho, Yu-Chen
4944ad75a51eSRichard Henderson gen_helper_mpcifc(tcg_env, r1, o->addr1, ar);
4945c9274b6bSCho, Yu-Chen set_cc_static(s);
4946c9274b6bSCho, Yu-Chen return DISAS_NEXT;
4947c9274b6bSCho, Yu-Chen }
4948c9274b6bSCho, Yu-Chen #endif
4949c9274b6bSCho, Yu-Chen
4950c9274b6bSCho, Yu-Chen #include "translate_vx.c.inc"
4951c9274b6bSCho, Yu-Chen
4952c9274b6bSCho, Yu-Chen /* ====================================================================== */
4953c9274b6bSCho, Yu-Chen /* The "Cc OUTput" generators. Given the generated output (and in some cases
4954c9274b6bSCho, Yu-Chen the original inputs), update the various cc data structures in order to
4955c9274b6bSCho, Yu-Chen be able to compute the new condition code. */
4956c9274b6bSCho, Yu-Chen
cout_abs32(DisasContext * s,DisasOps * o)4957c9274b6bSCho, Yu-Chen static void cout_abs32(DisasContext *s, DisasOps *o)
4958c9274b6bSCho, Yu-Chen {
4959c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_ABS_32, o->out);
4960c9274b6bSCho, Yu-Chen }
4961c9274b6bSCho, Yu-Chen
cout_abs64(DisasContext * s,DisasOps * o)4962c9274b6bSCho, Yu-Chen static void cout_abs64(DisasContext *s, DisasOps *o)
4963c9274b6bSCho, Yu-Chen {
4964c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_ABS_64, o->out);
4965c9274b6bSCho, Yu-Chen }
4966c9274b6bSCho, Yu-Chen
cout_adds32(DisasContext * s,DisasOps * o)4967c9274b6bSCho, Yu-Chen static void cout_adds32(DisasContext *s, DisasOps *o)
4968c9274b6bSCho, Yu-Chen {
4969c9274b6bSCho, Yu-Chen gen_op_update3_cc_i64(s, CC_OP_ADD_32, o->in1, o->in2, o->out);
4970c9274b6bSCho, Yu-Chen }
4971c9274b6bSCho, Yu-Chen
cout_adds64(DisasContext * s,DisasOps * o)4972c9274b6bSCho, Yu-Chen static void cout_adds64(DisasContext *s, DisasOps *o)
4973c9274b6bSCho, Yu-Chen {
4974c9274b6bSCho, Yu-Chen gen_op_update3_cc_i64(s, CC_OP_ADD_64, o->in1, o->in2, o->out);
4975c9274b6bSCho, Yu-Chen }
4976c9274b6bSCho, Yu-Chen
cout_addu32(DisasContext * s,DisasOps * o)4977c9274b6bSCho, Yu-Chen static void cout_addu32(DisasContext *s, DisasOps *o)
4978c9274b6bSCho, Yu-Chen {
4979c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(cc_src, o->out, 32);
4980c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(cc_dst, o->out);
4981c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_ADDU, cc_src, cc_dst);
4982c9274b6bSCho, Yu-Chen }
4983c9274b6bSCho, Yu-Chen
cout_addu64(DisasContext * s,DisasOps * o)4984c9274b6bSCho, Yu-Chen static void cout_addu64(DisasContext *s, DisasOps *o)
4985c9274b6bSCho, Yu-Chen {
4986c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_ADDU, cc_src, o->out);
4987c9274b6bSCho, Yu-Chen }
4988c9274b6bSCho, Yu-Chen
cout_cmps32(DisasContext * s,DisasOps * o)4989c9274b6bSCho, Yu-Chen static void cout_cmps32(DisasContext *s, DisasOps *o)
4990c9274b6bSCho, Yu-Chen {
4991c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_LTGT_32, o->in1, o->in2);
4992c9274b6bSCho, Yu-Chen }
4993c9274b6bSCho, Yu-Chen
cout_cmps64(DisasContext * s,DisasOps * o)4994c9274b6bSCho, Yu-Chen static void cout_cmps64(DisasContext *s, DisasOps *o)
4995c9274b6bSCho, Yu-Chen {
4996c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_LTGT_64, o->in1, o->in2);
4997c9274b6bSCho, Yu-Chen }
4998c9274b6bSCho, Yu-Chen
cout_cmpu32(DisasContext * s,DisasOps * o)4999c9274b6bSCho, Yu-Chen static void cout_cmpu32(DisasContext *s, DisasOps *o)
5000c9274b6bSCho, Yu-Chen {
5001c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_LTUGTU_32, o->in1, o->in2);
5002c9274b6bSCho, Yu-Chen }
5003c9274b6bSCho, Yu-Chen
cout_cmpu64(DisasContext * s,DisasOps * o)5004c9274b6bSCho, Yu-Chen static void cout_cmpu64(DisasContext *s, DisasOps *o)
5005c9274b6bSCho, Yu-Chen {
5006c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, o->in1, o->in2);
5007c9274b6bSCho, Yu-Chen }
5008c9274b6bSCho, Yu-Chen
cout_f32(DisasContext * s,DisasOps * o)5009c9274b6bSCho, Yu-Chen static void cout_f32(DisasContext *s, DisasOps *o)
5010c9274b6bSCho, Yu-Chen {
5011c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NZ_F32, o->out);
5012c9274b6bSCho, Yu-Chen }
5013c9274b6bSCho, Yu-Chen
cout_f64(DisasContext * s,DisasOps * o)5014c9274b6bSCho, Yu-Chen static void cout_f64(DisasContext *s, DisasOps *o)
5015c9274b6bSCho, Yu-Chen {
5016c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NZ_F64, o->out);
5017c9274b6bSCho, Yu-Chen }
5018c9274b6bSCho, Yu-Chen
cout_f128(DisasContext * s,DisasOps * o)5019c9274b6bSCho, Yu-Chen static void cout_f128(DisasContext *s, DisasOps *o)
5020c9274b6bSCho, Yu-Chen {
5021c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_NZ_F128, o->out, o->out2);
5022c9274b6bSCho, Yu-Chen }
5023c9274b6bSCho, Yu-Chen
cout_nabs32(DisasContext * s,DisasOps * o)5024c9274b6bSCho, Yu-Chen static void cout_nabs32(DisasContext *s, DisasOps *o)
5025c9274b6bSCho, Yu-Chen {
5026c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NABS_32, o->out);
5027c9274b6bSCho, Yu-Chen }
5028c9274b6bSCho, Yu-Chen
cout_nabs64(DisasContext * s,DisasOps * o)5029c9274b6bSCho, Yu-Chen static void cout_nabs64(DisasContext *s, DisasOps *o)
5030c9274b6bSCho, Yu-Chen {
5031c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NABS_64, o->out);
5032c9274b6bSCho, Yu-Chen }
5033c9274b6bSCho, Yu-Chen
cout_neg32(DisasContext * s,DisasOps * o)5034c9274b6bSCho, Yu-Chen static void cout_neg32(DisasContext *s, DisasOps *o)
5035c9274b6bSCho, Yu-Chen {
5036c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_COMP_32, o->out);
5037c9274b6bSCho, Yu-Chen }
5038c9274b6bSCho, Yu-Chen
cout_neg64(DisasContext * s,DisasOps * o)5039c9274b6bSCho, Yu-Chen static void cout_neg64(DisasContext *s, DisasOps *o)
5040c9274b6bSCho, Yu-Chen {
5041c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_COMP_64, o->out);
5042c9274b6bSCho, Yu-Chen }
5043c9274b6bSCho, Yu-Chen
cout_nz32(DisasContext * s,DisasOps * o)5044c9274b6bSCho, Yu-Chen static void cout_nz32(DisasContext *s, DisasOps *o)
5045c9274b6bSCho, Yu-Chen {
5046c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(cc_dst, o->out);
5047c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NZ, cc_dst);
5048c9274b6bSCho, Yu-Chen }
5049c9274b6bSCho, Yu-Chen
cout_nz64(DisasContext * s,DisasOps * o)5050c9274b6bSCho, Yu-Chen static void cout_nz64(DisasContext *s, DisasOps *o)
5051c9274b6bSCho, Yu-Chen {
5052c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_NZ, o->out);
5053c9274b6bSCho, Yu-Chen }
5054c9274b6bSCho, Yu-Chen
cout_s32(DisasContext * s,DisasOps * o)5055c9274b6bSCho, Yu-Chen static void cout_s32(DisasContext *s, DisasOps *o)
5056c9274b6bSCho, Yu-Chen {
5057c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_LTGT0_32, o->out);
5058c9274b6bSCho, Yu-Chen }
5059c9274b6bSCho, Yu-Chen
cout_s64(DisasContext * s,DisasOps * o)5060c9274b6bSCho, Yu-Chen static void cout_s64(DisasContext *s, DisasOps *o)
5061c9274b6bSCho, Yu-Chen {
5062c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, o->out);
5063c9274b6bSCho, Yu-Chen }
5064c9274b6bSCho, Yu-Chen
cout_subs32(DisasContext * s,DisasOps * o)5065c9274b6bSCho, Yu-Chen static void cout_subs32(DisasContext *s, DisasOps *o)
5066c9274b6bSCho, Yu-Chen {
5067c9274b6bSCho, Yu-Chen gen_op_update3_cc_i64(s, CC_OP_SUB_32, o->in1, o->in2, o->out);
5068c9274b6bSCho, Yu-Chen }
5069c9274b6bSCho, Yu-Chen
cout_subs64(DisasContext * s,DisasOps * o)5070c9274b6bSCho, Yu-Chen static void cout_subs64(DisasContext *s, DisasOps *o)
5071c9274b6bSCho, Yu-Chen {
5072c9274b6bSCho, Yu-Chen gen_op_update3_cc_i64(s, CC_OP_SUB_64, o->in1, o->in2, o->out);
5073c9274b6bSCho, Yu-Chen }
5074c9274b6bSCho, Yu-Chen
cout_subu32(DisasContext * s,DisasOps * o)5075c9274b6bSCho, Yu-Chen static void cout_subu32(DisasContext *s, DisasOps *o)
5076c9274b6bSCho, Yu-Chen {
5077c9274b6bSCho, Yu-Chen tcg_gen_sari_i64(cc_src, o->out, 32);
5078c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(cc_dst, o->out);
5079c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_SUBU, cc_src, cc_dst);
5080c9274b6bSCho, Yu-Chen }
5081c9274b6bSCho, Yu-Chen
cout_subu64(DisasContext * s,DisasOps * o)5082c9274b6bSCho, Yu-Chen static void cout_subu64(DisasContext *s, DisasOps *o)
5083c9274b6bSCho, Yu-Chen {
5084c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_SUBU, cc_src, o->out);
5085c9274b6bSCho, Yu-Chen }
5086c9274b6bSCho, Yu-Chen
cout_tm32(DisasContext * s,DisasOps * o)5087c9274b6bSCho, Yu-Chen static void cout_tm32(DisasContext *s, DisasOps *o)
5088c9274b6bSCho, Yu-Chen {
5089c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_TM_32, o->in1, o->in2);
5090c9274b6bSCho, Yu-Chen }
5091c9274b6bSCho, Yu-Chen
cout_tm64(DisasContext * s,DisasOps * o)5092c9274b6bSCho, Yu-Chen static void cout_tm64(DisasContext *s, DisasOps *o)
5093c9274b6bSCho, Yu-Chen {
5094c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_TM_64, o->in1, o->in2);
5095c9274b6bSCho, Yu-Chen }
5096c9274b6bSCho, Yu-Chen
cout_muls32(DisasContext * s,DisasOps * o)5097c9274b6bSCho, Yu-Chen static void cout_muls32(DisasContext *s, DisasOps *o)
5098c9274b6bSCho, Yu-Chen {
5099c9274b6bSCho, Yu-Chen gen_op_update1_cc_i64(s, CC_OP_MULS_32, o->out);
5100c9274b6bSCho, Yu-Chen }
5101c9274b6bSCho, Yu-Chen
cout_muls64(DisasContext * s,DisasOps * o)5102c9274b6bSCho, Yu-Chen static void cout_muls64(DisasContext *s, DisasOps *o)
5103c9274b6bSCho, Yu-Chen {
5104c9274b6bSCho, Yu-Chen /* out contains "high" part, out2 contains "low" part of 128 bit result */
5105c9274b6bSCho, Yu-Chen gen_op_update2_cc_i64(s, CC_OP_MULS_64, o->out, o->out2);
5106c9274b6bSCho, Yu-Chen }
5107c9274b6bSCho, Yu-Chen
5108c9274b6bSCho, Yu-Chen /* ====================================================================== */
5109c9274b6bSCho, Yu-Chen /* The "PREParation" generators. These initialize the DisasOps.OUT fields
5110c9274b6bSCho, Yu-Chen with the TCG register to which we will write. Used in combination with
5111c9274b6bSCho, Yu-Chen the "wout" generators, in some cases we need a new temporary, and in
5112c9274b6bSCho, Yu-Chen some cases we can write to a TCG global. */
5113c9274b6bSCho, Yu-Chen
prep_new(DisasContext * s,DisasOps * o)5114c9274b6bSCho, Yu-Chen static void prep_new(DisasContext *s, DisasOps *o)
5115c9274b6bSCho, Yu-Chen {
5116c9274b6bSCho, Yu-Chen o->out = tcg_temp_new_i64();
5117c9274b6bSCho, Yu-Chen }
5118c9274b6bSCho, Yu-Chen #define SPEC_prep_new 0
5119c9274b6bSCho, Yu-Chen
prep_new_P(DisasContext * s,DisasOps * o)5120c9274b6bSCho, Yu-Chen static void prep_new_P(DisasContext *s, DisasOps *o)
5121c9274b6bSCho, Yu-Chen {
5122c9274b6bSCho, Yu-Chen o->out = tcg_temp_new_i64();
5123c9274b6bSCho, Yu-Chen o->out2 = tcg_temp_new_i64();
5124c9274b6bSCho, Yu-Chen }
5125c9274b6bSCho, Yu-Chen #define SPEC_prep_new_P 0
5126c9274b6bSCho, Yu-Chen
prep_new_x(DisasContext * s,DisasOps * o)5127ee5e866fSRichard Henderson static void prep_new_x(DisasContext *s, DisasOps *o)
5128ee5e866fSRichard Henderson {
5129ee5e866fSRichard Henderson o->out_128 = tcg_temp_new_i128();
5130ee5e866fSRichard Henderson }
5131ee5e866fSRichard Henderson #define SPEC_prep_new_x 0
5132ee5e866fSRichard Henderson
prep_r1(DisasContext * s,DisasOps * o)5133c9274b6bSCho, Yu-Chen static void prep_r1(DisasContext *s, DisasOps *o)
5134c9274b6bSCho, Yu-Chen {
5135c9274b6bSCho, Yu-Chen o->out = regs[get_field(s, r1)];
5136c9274b6bSCho, Yu-Chen }
5137c9274b6bSCho, Yu-Chen #define SPEC_prep_r1 0
5138c9274b6bSCho, Yu-Chen
prep_r1_P(DisasContext * s,DisasOps * o)5139c9274b6bSCho, Yu-Chen static void prep_r1_P(DisasContext *s, DisasOps *o)
5140c9274b6bSCho, Yu-Chen {
5141c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
5142c9274b6bSCho, Yu-Chen o->out = regs[r1];
5143c9274b6bSCho, Yu-Chen o->out2 = regs[r1 + 1];
5144c9274b6bSCho, Yu-Chen }
5145c9274b6bSCho, Yu-Chen #define SPEC_prep_r1_P SPEC_r1_even
5146c9274b6bSCho, Yu-Chen
5147c9274b6bSCho, Yu-Chen /* ====================================================================== */
5148c9274b6bSCho, Yu-Chen /* The "Write OUTput" generators. These generally perform some non-trivial
5149c9274b6bSCho, Yu-Chen copy of data to TCG globals, or to main memory. The trivial cases are
5150c9274b6bSCho, Yu-Chen generally handled by having a "prep" generator install the TCG global
5151c9274b6bSCho, Yu-Chen as the destination of the operation. */
5152c9274b6bSCho, Yu-Chen
wout_r1(DisasContext * s,DisasOps * o)5153c9274b6bSCho, Yu-Chen static void wout_r1(DisasContext *s, DisasOps *o)
5154c9274b6bSCho, Yu-Chen {
5155c9274b6bSCho, Yu-Chen store_reg(get_field(s, r1), o->out);
5156c9274b6bSCho, Yu-Chen }
5157c9274b6bSCho, Yu-Chen #define SPEC_wout_r1 0
5158c9274b6bSCho, Yu-Chen
wout_out2_r1(DisasContext * s,DisasOps * o)5159c9274b6bSCho, Yu-Chen static void wout_out2_r1(DisasContext *s, DisasOps *o)
5160c9274b6bSCho, Yu-Chen {
5161c9274b6bSCho, Yu-Chen store_reg(get_field(s, r1), o->out2);
5162c9274b6bSCho, Yu-Chen }
5163c9274b6bSCho, Yu-Chen #define SPEC_wout_out2_r1 0
5164c9274b6bSCho, Yu-Chen
wout_r1_8(DisasContext * s,DisasOps * o)5165c9274b6bSCho, Yu-Chen static void wout_r1_8(DisasContext *s, DisasOps *o)
5166c9274b6bSCho, Yu-Chen {
5167c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
5168c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
5169c9274b6bSCho, Yu-Chen }
5170c9274b6bSCho, Yu-Chen #define SPEC_wout_r1_8 0
5171c9274b6bSCho, Yu-Chen
wout_r1_16(DisasContext * s,DisasOps * o)5172c9274b6bSCho, Yu-Chen static void wout_r1_16(DisasContext *s, DisasOps *o)
5173c9274b6bSCho, Yu-Chen {
5174c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
5175c9274b6bSCho, Yu-Chen tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
5176c9274b6bSCho, Yu-Chen }
5177c9274b6bSCho, Yu-Chen #define SPEC_wout_r1_16 0
5178c9274b6bSCho, Yu-Chen
wout_r1_32(DisasContext * s,DisasOps * o)5179c9274b6bSCho, Yu-Chen static void wout_r1_32(DisasContext *s, DisasOps *o)
5180c9274b6bSCho, Yu-Chen {
5181c9274b6bSCho, Yu-Chen store_reg32_i64(get_field(s, r1), o->out);
5182c9274b6bSCho, Yu-Chen }
5183c9274b6bSCho, Yu-Chen #define SPEC_wout_r1_32 0
5184c9274b6bSCho, Yu-Chen
wout_r1_32h(DisasContext * s,DisasOps * o)5185c9274b6bSCho, Yu-Chen static void wout_r1_32h(DisasContext *s, DisasOps *o)
5186c9274b6bSCho, Yu-Chen {
5187c9274b6bSCho, Yu-Chen store_reg32h_i64(get_field(s, r1), o->out);
5188c9274b6bSCho, Yu-Chen }
5189c9274b6bSCho, Yu-Chen #define SPEC_wout_r1_32h 0
5190c9274b6bSCho, Yu-Chen
wout_r1_P32(DisasContext * s,DisasOps * o)5191c9274b6bSCho, Yu-Chen static void wout_r1_P32(DisasContext *s, DisasOps *o)
5192c9274b6bSCho, Yu-Chen {
5193c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
5194c9274b6bSCho, Yu-Chen store_reg32_i64(r1, o->out);
5195c9274b6bSCho, Yu-Chen store_reg32_i64(r1 + 1, o->out2);
5196c9274b6bSCho, Yu-Chen }
5197c9274b6bSCho, Yu-Chen #define SPEC_wout_r1_P32 SPEC_r1_even
5198c9274b6bSCho, Yu-Chen
wout_r1_D32(DisasContext * s,DisasOps * o)5199c9274b6bSCho, Yu-Chen static void wout_r1_D32(DisasContext *s, DisasOps *o)
5200c9274b6bSCho, Yu-Chen {
5201c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
520257556b28SIlya Leoshkevich TCGv_i64 t = tcg_temp_new_i64();
5203c9274b6bSCho, Yu-Chen store_reg32_i64(r1 + 1, o->out);
520457556b28SIlya Leoshkevich tcg_gen_shri_i64(t, o->out, 32);
520557556b28SIlya Leoshkevich store_reg32_i64(r1, t);
5206c9274b6bSCho, Yu-Chen }
5207c9274b6bSCho, Yu-Chen #define SPEC_wout_r1_D32 SPEC_r1_even
5208c9274b6bSCho, Yu-Chen
wout_r1_D64(DisasContext * s,DisasOps * o)52091fcd84faSRichard Henderson static void wout_r1_D64(DisasContext *s, DisasOps *o)
52101fcd84faSRichard Henderson {
52111fcd84faSRichard Henderson int r1 = get_field(s, r1);
52121fcd84faSRichard Henderson tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128);
52131fcd84faSRichard Henderson }
52141fcd84faSRichard Henderson #define SPEC_wout_r1_D64 SPEC_r1_even
52151fcd84faSRichard Henderson
wout_r3_P32(DisasContext * s,DisasOps * o)5216c9274b6bSCho, Yu-Chen static void wout_r3_P32(DisasContext *s, DisasOps *o)
5217c9274b6bSCho, Yu-Chen {
5218c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
5219c9274b6bSCho, Yu-Chen store_reg32_i64(r3, o->out);
5220c9274b6bSCho, Yu-Chen store_reg32_i64(r3 + 1, o->out2);
5221c9274b6bSCho, Yu-Chen }
5222c9274b6bSCho, Yu-Chen #define SPEC_wout_r3_P32 SPEC_r3_even
5223c9274b6bSCho, Yu-Chen
wout_r3_P64(DisasContext * s,DisasOps * o)5224c9274b6bSCho, Yu-Chen static void wout_r3_P64(DisasContext *s, DisasOps *o)
5225c9274b6bSCho, Yu-Chen {
5226c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
5227c9274b6bSCho, Yu-Chen store_reg(r3, o->out);
5228c9274b6bSCho, Yu-Chen store_reg(r3 + 1, o->out2);
5229c9274b6bSCho, Yu-Chen }
5230c9274b6bSCho, Yu-Chen #define SPEC_wout_r3_P64 SPEC_r3_even
5231c9274b6bSCho, Yu-Chen
wout_e1(DisasContext * s,DisasOps * o)5232c9274b6bSCho, Yu-Chen static void wout_e1(DisasContext *s, DisasOps *o)
5233c9274b6bSCho, Yu-Chen {
5234c9274b6bSCho, Yu-Chen store_freg32_i64(get_field(s, r1), o->out);
5235c9274b6bSCho, Yu-Chen }
5236c9274b6bSCho, Yu-Chen #define SPEC_wout_e1 0
5237c9274b6bSCho, Yu-Chen
wout_f1(DisasContext * s,DisasOps * o)5238c9274b6bSCho, Yu-Chen static void wout_f1(DisasContext *s, DisasOps *o)
5239c9274b6bSCho, Yu-Chen {
5240c9274b6bSCho, Yu-Chen store_freg(get_field(s, r1), o->out);
5241c9274b6bSCho, Yu-Chen }
5242c9274b6bSCho, Yu-Chen #define SPEC_wout_f1 0
5243c9274b6bSCho, Yu-Chen
wout_x1(DisasContext * s,DisasOps * o)5244c9274b6bSCho, Yu-Chen static void wout_x1(DisasContext *s, DisasOps *o)
5245c9274b6bSCho, Yu-Chen {
5246c9274b6bSCho, Yu-Chen int f1 = get_field(s, r1);
5247ee5e866fSRichard Henderson
52482b91240fSRichard Henderson /* Split out_128 into out+out2 for cout_f128. */
52492b91240fSRichard Henderson tcg_debug_assert(o->out == NULL);
52502b91240fSRichard Henderson o->out = tcg_temp_new_i64();
52512b91240fSRichard Henderson o->out2 = tcg_temp_new_i64();
52522b91240fSRichard Henderson
5253ee5e866fSRichard Henderson tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128);
5254c9274b6bSCho, Yu-Chen store_freg(f1, o->out);
5255c9274b6bSCho, Yu-Chen store_freg(f1 + 2, o->out2);
5256c9274b6bSCho, Yu-Chen }
5257c9274b6bSCho, Yu-Chen #define SPEC_wout_x1 SPEC_r1_f128
5258c9274b6bSCho, Yu-Chen
wout_x1_P(DisasContext * s,DisasOps * o)5259f4031d96SRichard Henderson static void wout_x1_P(DisasContext *s, DisasOps *o)
5260f4031d96SRichard Henderson {
5261f4031d96SRichard Henderson int f1 = get_field(s, r1);
5262f4031d96SRichard Henderson store_freg(f1, o->out);
5263f4031d96SRichard Henderson store_freg(f1 + 2, o->out2);
5264f4031d96SRichard Henderson }
5265f4031d96SRichard Henderson #define SPEC_wout_x1_P SPEC_r1_f128
5266f4031d96SRichard Henderson
wout_cond_r1r2_32(DisasContext * s,DisasOps * o)5267c9274b6bSCho, Yu-Chen static void wout_cond_r1r2_32(DisasContext *s, DisasOps *o)
5268c9274b6bSCho, Yu-Chen {
5269c9274b6bSCho, Yu-Chen if (get_field(s, r1) != get_field(s, r2)) {
5270c9274b6bSCho, Yu-Chen store_reg32_i64(get_field(s, r1), o->out);
5271c9274b6bSCho, Yu-Chen }
5272c9274b6bSCho, Yu-Chen }
5273c9274b6bSCho, Yu-Chen #define SPEC_wout_cond_r1r2_32 0
5274c9274b6bSCho, Yu-Chen
wout_cond_e1e2(DisasContext * s,DisasOps * o)5275c9274b6bSCho, Yu-Chen static void wout_cond_e1e2(DisasContext *s, DisasOps *o)
5276c9274b6bSCho, Yu-Chen {
5277c9274b6bSCho, Yu-Chen if (get_field(s, r1) != get_field(s, r2)) {
5278c9274b6bSCho, Yu-Chen store_freg32_i64(get_field(s, r1), o->out);
5279c9274b6bSCho, Yu-Chen }
5280c9274b6bSCho, Yu-Chen }
5281c9274b6bSCho, Yu-Chen #define SPEC_wout_cond_e1e2 0
5282c9274b6bSCho, Yu-Chen
wout_m1_8(DisasContext * s,DisasOps * o)5283c9274b6bSCho, Yu-Chen static void wout_m1_8(DisasContext *s, DisasOps *o)
5284c9274b6bSCho, Yu-Chen {
5285e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB);
5286c9274b6bSCho, Yu-Chen }
5287c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_8 0
5288c9274b6bSCho, Yu-Chen
wout_m1_16(DisasContext * s,DisasOps * o)5289c9274b6bSCho, Yu-Chen static void wout_m1_16(DisasContext *s, DisasOps *o)
5290c9274b6bSCho, Yu-Chen {
5291e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUW);
5292c9274b6bSCho, Yu-Chen }
5293c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_16 0
5294c9274b6bSCho, Yu-Chen
5295c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
wout_m1_16a(DisasContext * s,DisasOps * o)5296c9274b6bSCho, Yu-Chen static void wout_m1_16a(DisasContext *s, DisasOps *o)
5297c9274b6bSCho, Yu-Chen {
5298c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUW | MO_ALIGN);
5299c9274b6bSCho, Yu-Chen }
5300c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_16a 0
5301c9274b6bSCho, Yu-Chen #endif
5302c9274b6bSCho, Yu-Chen
wout_m1_32(DisasContext * s,DisasOps * o)5303c9274b6bSCho, Yu-Chen static void wout_m1_32(DisasContext *s, DisasOps *o)
5304c9274b6bSCho, Yu-Chen {
5305e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUL);
5306c9274b6bSCho, Yu-Chen }
5307c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_32 0
5308c9274b6bSCho, Yu-Chen
5309c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
wout_m1_32a(DisasContext * s,DisasOps * o)5310c9274b6bSCho, Yu-Chen static void wout_m1_32a(DisasContext *s, DisasOps *o)
5311c9274b6bSCho, Yu-Chen {
5312c9274b6bSCho, Yu-Chen tcg_gen_qemu_st_tl(o->out, o->addr1, get_mem_index(s), MO_TEUL | MO_ALIGN);
5313c9274b6bSCho, Yu-Chen }
5314c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_32a 0
5315c9274b6bSCho, Yu-Chen #endif
5316c9274b6bSCho, Yu-Chen
wout_m1_64(DisasContext * s,DisasOps * o)5317c9274b6bSCho, Yu-Chen static void wout_m1_64(DisasContext *s, DisasOps *o)
5318c9274b6bSCho, Yu-Chen {
5319e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ);
5320c9274b6bSCho, Yu-Chen }
5321c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_64 0
5322c9274b6bSCho, Yu-Chen
5323c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
wout_m1_64a(DisasContext * s,DisasOps * o)5324c9274b6bSCho, Yu-Chen static void wout_m1_64a(DisasContext *s, DisasOps *o)
5325c9274b6bSCho, Yu-Chen {
5326fc313c64SFrédéric Pétrot tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_TEUQ | MO_ALIGN);
5327c9274b6bSCho, Yu-Chen }
5328c9274b6bSCho, Yu-Chen #define SPEC_wout_m1_64a 0
5329c9274b6bSCho, Yu-Chen #endif
5330c9274b6bSCho, Yu-Chen
wout_m2_32(DisasContext * s,DisasOps * o)5331c9274b6bSCho, Yu-Chen static void wout_m2_32(DisasContext *s, DisasOps *o)
5332c9274b6bSCho, Yu-Chen {
5333e87027d0SRichard Henderson tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_TEUL);
5334c9274b6bSCho, Yu-Chen }
5335c9274b6bSCho, Yu-Chen #define SPEC_wout_m2_32 0
5336c9274b6bSCho, Yu-Chen
wout_in2_r1(DisasContext * s,DisasOps * o)5337c9274b6bSCho, Yu-Chen static void wout_in2_r1(DisasContext *s, DisasOps *o)
5338c9274b6bSCho, Yu-Chen {
5339c9274b6bSCho, Yu-Chen store_reg(get_field(s, r1), o->in2);
5340c9274b6bSCho, Yu-Chen }
5341c9274b6bSCho, Yu-Chen #define SPEC_wout_in2_r1 0
5342c9274b6bSCho, Yu-Chen
wout_in2_r1_32(DisasContext * s,DisasOps * o)5343c9274b6bSCho, Yu-Chen static void wout_in2_r1_32(DisasContext *s, DisasOps *o)
5344c9274b6bSCho, Yu-Chen {
5345c9274b6bSCho, Yu-Chen store_reg32_i64(get_field(s, r1), o->in2);
5346c9274b6bSCho, Yu-Chen }
5347c9274b6bSCho, Yu-Chen #define SPEC_wout_in2_r1_32 0
5348c9274b6bSCho, Yu-Chen
5349c9274b6bSCho, Yu-Chen /* ====================================================================== */
5350c9274b6bSCho, Yu-Chen /* The "INput 1" generators. These load the first operand to an insn. */
5351c9274b6bSCho, Yu-Chen
in1_r1(DisasContext * s,DisasOps * o)5352c9274b6bSCho, Yu-Chen static void in1_r1(DisasContext *s, DisasOps *o)
5353c9274b6bSCho, Yu-Chen {
5354c9274b6bSCho, Yu-Chen o->in1 = load_reg(get_field(s, r1));
5355c9274b6bSCho, Yu-Chen }
5356c9274b6bSCho, Yu-Chen #define SPEC_in1_r1 0
5357c9274b6bSCho, Yu-Chen
in1_r1_o(DisasContext * s,DisasOps * o)5358c9274b6bSCho, Yu-Chen static void in1_r1_o(DisasContext *s, DisasOps *o)
5359c9274b6bSCho, Yu-Chen {
5360c9274b6bSCho, Yu-Chen o->in1 = regs[get_field(s, r1)];
5361c9274b6bSCho, Yu-Chen }
5362c9274b6bSCho, Yu-Chen #define SPEC_in1_r1_o 0
5363c9274b6bSCho, Yu-Chen
in1_r1_32s(DisasContext * s,DisasOps * o)5364c9274b6bSCho, Yu-Chen static void in1_r1_32s(DisasContext *s, DisasOps *o)
5365c9274b6bSCho, Yu-Chen {
5366c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5367c9274b6bSCho, Yu-Chen tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r1)]);
5368c9274b6bSCho, Yu-Chen }
5369c9274b6bSCho, Yu-Chen #define SPEC_in1_r1_32s 0
5370c9274b6bSCho, Yu-Chen
in1_r1_32u(DisasContext * s,DisasOps * o)5371c9274b6bSCho, Yu-Chen static void in1_r1_32u(DisasContext *s, DisasOps *o)
5372c9274b6bSCho, Yu-Chen {
5373c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5374c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r1)]);
5375c9274b6bSCho, Yu-Chen }
5376c9274b6bSCho, Yu-Chen #define SPEC_in1_r1_32u 0
5377c9274b6bSCho, Yu-Chen
in1_r1_sr32(DisasContext * s,DisasOps * o)5378c9274b6bSCho, Yu-Chen static void in1_r1_sr32(DisasContext *s, DisasOps *o)
5379c9274b6bSCho, Yu-Chen {
5380c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5381c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(o->in1, regs[get_field(s, r1)], 32);
5382c9274b6bSCho, Yu-Chen }
5383c9274b6bSCho, Yu-Chen #define SPEC_in1_r1_sr32 0
5384c9274b6bSCho, Yu-Chen
in1_r1p1(DisasContext * s,DisasOps * o)5385c9274b6bSCho, Yu-Chen static void in1_r1p1(DisasContext *s, DisasOps *o)
5386c9274b6bSCho, Yu-Chen {
5387c9274b6bSCho, Yu-Chen o->in1 = load_reg(get_field(s, r1) + 1);
5388c9274b6bSCho, Yu-Chen }
5389c9274b6bSCho, Yu-Chen #define SPEC_in1_r1p1 SPEC_r1_even
5390c9274b6bSCho, Yu-Chen
in1_r1p1_o(DisasContext * s,DisasOps * o)5391c9274b6bSCho, Yu-Chen static void in1_r1p1_o(DisasContext *s, DisasOps *o)
5392c9274b6bSCho, Yu-Chen {
5393c9274b6bSCho, Yu-Chen o->in1 = regs[get_field(s, r1) + 1];
5394c9274b6bSCho, Yu-Chen }
5395c9274b6bSCho, Yu-Chen #define SPEC_in1_r1p1_o SPEC_r1_even
5396c9274b6bSCho, Yu-Chen
in1_r1p1_32s(DisasContext * s,DisasOps * o)5397c9274b6bSCho, Yu-Chen static void in1_r1p1_32s(DisasContext *s, DisasOps *o)
5398c9274b6bSCho, Yu-Chen {
5399c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5400c9274b6bSCho, Yu-Chen tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r1) + 1]);
5401c9274b6bSCho, Yu-Chen }
5402c9274b6bSCho, Yu-Chen #define SPEC_in1_r1p1_32s SPEC_r1_even
5403c9274b6bSCho, Yu-Chen
in1_r1p1_32u(DisasContext * s,DisasOps * o)5404c9274b6bSCho, Yu-Chen static void in1_r1p1_32u(DisasContext *s, DisasOps *o)
5405c9274b6bSCho, Yu-Chen {
5406c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5407c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r1) + 1]);
5408c9274b6bSCho, Yu-Chen }
5409c9274b6bSCho, Yu-Chen #define SPEC_in1_r1p1_32u SPEC_r1_even
5410c9274b6bSCho, Yu-Chen
in1_r1_D32(DisasContext * s,DisasOps * o)5411c9274b6bSCho, Yu-Chen static void in1_r1_D32(DisasContext *s, DisasOps *o)
5412c9274b6bSCho, Yu-Chen {
5413c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
5414c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5415c9274b6bSCho, Yu-Chen tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
5416c9274b6bSCho, Yu-Chen }
5417c9274b6bSCho, Yu-Chen #define SPEC_in1_r1_D32 SPEC_r1_even
5418c9274b6bSCho, Yu-Chen
in1_r2(DisasContext * s,DisasOps * o)5419c9274b6bSCho, Yu-Chen static void in1_r2(DisasContext *s, DisasOps *o)
5420c9274b6bSCho, Yu-Chen {
5421c9274b6bSCho, Yu-Chen o->in1 = load_reg(get_field(s, r2));
5422c9274b6bSCho, Yu-Chen }
5423c9274b6bSCho, Yu-Chen #define SPEC_in1_r2 0
5424c9274b6bSCho, Yu-Chen
in1_r2_sr32(DisasContext * s,DisasOps * o)5425c9274b6bSCho, Yu-Chen static void in1_r2_sr32(DisasContext *s, DisasOps *o)
5426c9274b6bSCho, Yu-Chen {
5427c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5428c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(o->in1, regs[get_field(s, r2)], 32);
5429c9274b6bSCho, Yu-Chen }
5430c9274b6bSCho, Yu-Chen #define SPEC_in1_r2_sr32 0
5431c9274b6bSCho, Yu-Chen
in1_r2_32u(DisasContext * s,DisasOps * o)5432c9274b6bSCho, Yu-Chen static void in1_r2_32u(DisasContext *s, DisasOps *o)
5433c9274b6bSCho, Yu-Chen {
5434c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5435c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r2)]);
5436c9274b6bSCho, Yu-Chen }
5437c9274b6bSCho, Yu-Chen #define SPEC_in1_r2_32u 0
5438c9274b6bSCho, Yu-Chen
in1_r3(DisasContext * s,DisasOps * o)5439c9274b6bSCho, Yu-Chen static void in1_r3(DisasContext *s, DisasOps *o)
5440c9274b6bSCho, Yu-Chen {
5441c9274b6bSCho, Yu-Chen o->in1 = load_reg(get_field(s, r3));
5442c9274b6bSCho, Yu-Chen }
5443c9274b6bSCho, Yu-Chen #define SPEC_in1_r3 0
5444c9274b6bSCho, Yu-Chen
in1_r3_o(DisasContext * s,DisasOps * o)5445c9274b6bSCho, Yu-Chen static void in1_r3_o(DisasContext *s, DisasOps *o)
5446c9274b6bSCho, Yu-Chen {
5447c9274b6bSCho, Yu-Chen o->in1 = regs[get_field(s, r3)];
5448c9274b6bSCho, Yu-Chen }
5449c9274b6bSCho, Yu-Chen #define SPEC_in1_r3_o 0
5450c9274b6bSCho, Yu-Chen
in1_r3_32s(DisasContext * s,DisasOps * o)5451c9274b6bSCho, Yu-Chen static void in1_r3_32s(DisasContext *s, DisasOps *o)
5452c9274b6bSCho, Yu-Chen {
5453c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5454c9274b6bSCho, Yu-Chen tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r3)]);
5455c9274b6bSCho, Yu-Chen }
5456c9274b6bSCho, Yu-Chen #define SPEC_in1_r3_32s 0
5457c9274b6bSCho, Yu-Chen
in1_r3_32u(DisasContext * s,DisasOps * o)5458c9274b6bSCho, Yu-Chen static void in1_r3_32u(DisasContext *s, DisasOps *o)
5459c9274b6bSCho, Yu-Chen {
5460c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5461c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r3)]);
5462c9274b6bSCho, Yu-Chen }
5463c9274b6bSCho, Yu-Chen #define SPEC_in1_r3_32u 0
5464c9274b6bSCho, Yu-Chen
in1_r3_D32(DisasContext * s,DisasOps * o)5465c9274b6bSCho, Yu-Chen static void in1_r3_D32(DisasContext *s, DisasOps *o)
5466c9274b6bSCho, Yu-Chen {
5467c9274b6bSCho, Yu-Chen int r3 = get_field(s, r3);
5468c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5469c9274b6bSCho, Yu-Chen tcg_gen_concat32_i64(o->in1, regs[r3 + 1], regs[r3]);
5470c9274b6bSCho, Yu-Chen }
5471c9274b6bSCho, Yu-Chen #define SPEC_in1_r3_D32 SPEC_r3_even
5472c9274b6bSCho, Yu-Chen
in1_r3_sr32(DisasContext * s,DisasOps * o)5473ea0a1053SDavid Miller static void in1_r3_sr32(DisasContext *s, DisasOps *o)
5474ea0a1053SDavid Miller {
5475ea0a1053SDavid Miller o->in1 = tcg_temp_new_i64();
5476ea0a1053SDavid Miller tcg_gen_shri_i64(o->in1, regs[get_field(s, r3)], 32);
5477ea0a1053SDavid Miller }
5478ea0a1053SDavid Miller #define SPEC_in1_r3_sr32 0
5479ea0a1053SDavid Miller
in1_e1(DisasContext * s,DisasOps * o)5480c9274b6bSCho, Yu-Chen static void in1_e1(DisasContext *s, DisasOps *o)
5481c9274b6bSCho, Yu-Chen {
5482c9274b6bSCho, Yu-Chen o->in1 = load_freg32_i64(get_field(s, r1));
5483c9274b6bSCho, Yu-Chen }
5484c9274b6bSCho, Yu-Chen #define SPEC_in1_e1 0
5485c9274b6bSCho, Yu-Chen
in1_f1(DisasContext * s,DisasOps * o)5486c9274b6bSCho, Yu-Chen static void in1_f1(DisasContext *s, DisasOps *o)
5487c9274b6bSCho, Yu-Chen {
5488c9274b6bSCho, Yu-Chen o->in1 = load_freg(get_field(s, r1));
5489c9274b6bSCho, Yu-Chen }
5490c9274b6bSCho, Yu-Chen #define SPEC_in1_f1 0
5491c9274b6bSCho, Yu-Chen
in1_x1(DisasContext * s,DisasOps * o)54922b91240fSRichard Henderson static void in1_x1(DisasContext *s, DisasOps *o)
54932b91240fSRichard Henderson {
54942b91240fSRichard Henderson o->in1_128 = load_freg_128(get_field(s, r1));
54952b91240fSRichard Henderson }
54962b91240fSRichard Henderson #define SPEC_in1_x1 SPEC_r1_f128
54972b91240fSRichard Henderson
5498c9274b6bSCho, Yu-Chen /* Load the high double word of an extended (128-bit) format FP number */
in1_x2h(DisasContext * s,DisasOps * o)5499c9274b6bSCho, Yu-Chen static void in1_x2h(DisasContext *s, DisasOps *o)
5500c9274b6bSCho, Yu-Chen {
5501c9274b6bSCho, Yu-Chen o->in1 = load_freg(get_field(s, r2));
5502c9274b6bSCho, Yu-Chen }
5503c9274b6bSCho, Yu-Chen #define SPEC_in1_x2h SPEC_r2_f128
5504c9274b6bSCho, Yu-Chen
in1_f3(DisasContext * s,DisasOps * o)5505c9274b6bSCho, Yu-Chen static void in1_f3(DisasContext *s, DisasOps *o)
5506c9274b6bSCho, Yu-Chen {
5507c9274b6bSCho, Yu-Chen o->in1 = load_freg(get_field(s, r3));
5508c9274b6bSCho, Yu-Chen }
5509c9274b6bSCho, Yu-Chen #define SPEC_in1_f3 0
5510c9274b6bSCho, Yu-Chen
in1_la1(DisasContext * s,DisasOps * o)5511c9274b6bSCho, Yu-Chen static void in1_la1(DisasContext *s, DisasOps *o)
5512c9274b6bSCho, Yu-Chen {
5513c9274b6bSCho, Yu-Chen o->addr1 = get_address(s, 0, get_field(s, b1), get_field(s, d1));
5514c9274b6bSCho, Yu-Chen }
5515c9274b6bSCho, Yu-Chen #define SPEC_in1_la1 0
5516c9274b6bSCho, Yu-Chen
in1_la2(DisasContext * s,DisasOps * o)5517c9274b6bSCho, Yu-Chen static void in1_la2(DisasContext *s, DisasOps *o)
5518c9274b6bSCho, Yu-Chen {
5519c9274b6bSCho, Yu-Chen int x2 = have_field(s, x2) ? get_field(s, x2) : 0;
5520c9274b6bSCho, Yu-Chen o->addr1 = get_address(s, x2, get_field(s, b2), get_field(s, d2));
5521c9274b6bSCho, Yu-Chen }
5522c9274b6bSCho, Yu-Chen #define SPEC_in1_la2 0
5523c9274b6bSCho, Yu-Chen
in1_m1_8u(DisasContext * s,DisasOps * o)5524c9274b6bSCho, Yu-Chen static void in1_m1_8u(DisasContext *s, DisasOps *o)
5525c9274b6bSCho, Yu-Chen {
5526c9274b6bSCho, Yu-Chen in1_la1(s, o);
5527c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5528e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB);
5529c9274b6bSCho, Yu-Chen }
5530c9274b6bSCho, Yu-Chen #define SPEC_in1_m1_8u 0
5531c9274b6bSCho, Yu-Chen
in1_m1_16s(DisasContext * s,DisasOps * o)5532c9274b6bSCho, Yu-Chen static void in1_m1_16s(DisasContext *s, DisasOps *o)
5533c9274b6bSCho, Yu-Chen {
5534c9274b6bSCho, Yu-Chen in1_la1(s, o);
5535c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5536e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESW);
5537c9274b6bSCho, Yu-Chen }
5538c9274b6bSCho, Yu-Chen #define SPEC_in1_m1_16s 0
5539c9274b6bSCho, Yu-Chen
in1_m1_16u(DisasContext * s,DisasOps * o)5540c9274b6bSCho, Yu-Chen static void in1_m1_16u(DisasContext *s, DisasOps *o)
5541c9274b6bSCho, Yu-Chen {
5542c9274b6bSCho, Yu-Chen in1_la1(s, o);
5543c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5544e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUW);
5545c9274b6bSCho, Yu-Chen }
5546c9274b6bSCho, Yu-Chen #define SPEC_in1_m1_16u 0
5547c9274b6bSCho, Yu-Chen
in1_m1_32s(DisasContext * s,DisasOps * o)5548c9274b6bSCho, Yu-Chen static void in1_m1_32s(DisasContext *s, DisasOps *o)
5549c9274b6bSCho, Yu-Chen {
5550c9274b6bSCho, Yu-Chen in1_la1(s, o);
5551c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5552e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TESL);
5553c9274b6bSCho, Yu-Chen }
5554c9274b6bSCho, Yu-Chen #define SPEC_in1_m1_32s 0
5555c9274b6bSCho, Yu-Chen
in1_m1_32u(DisasContext * s,DisasOps * o)5556c9274b6bSCho, Yu-Chen static void in1_m1_32u(DisasContext *s, DisasOps *o)
5557c9274b6bSCho, Yu-Chen {
5558c9274b6bSCho, Yu-Chen in1_la1(s, o);
5559c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5560e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUL);
5561c9274b6bSCho, Yu-Chen }
5562c9274b6bSCho, Yu-Chen #define SPEC_in1_m1_32u 0
5563c9274b6bSCho, Yu-Chen
in1_m1_64(DisasContext * s,DisasOps * o)5564c9274b6bSCho, Yu-Chen static void in1_m1_64(DisasContext *s, DisasOps *o)
5565c9274b6bSCho, Yu-Chen {
5566c9274b6bSCho, Yu-Chen in1_la1(s, o);
5567c9274b6bSCho, Yu-Chen o->in1 = tcg_temp_new_i64();
5568e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_TEUQ);
5569c9274b6bSCho, Yu-Chen }
5570c9274b6bSCho, Yu-Chen #define SPEC_in1_m1_64 0
5571c9274b6bSCho, Yu-Chen
5572c9274b6bSCho, Yu-Chen /* ====================================================================== */
5573c9274b6bSCho, Yu-Chen /* The "INput 2" generators. These load the second operand to an insn. */
5574c9274b6bSCho, Yu-Chen
in2_r1_o(DisasContext * s,DisasOps * o)5575c9274b6bSCho, Yu-Chen static void in2_r1_o(DisasContext *s, DisasOps *o)
5576c9274b6bSCho, Yu-Chen {
5577c9274b6bSCho, Yu-Chen o->in2 = regs[get_field(s, r1)];
5578c9274b6bSCho, Yu-Chen }
5579c9274b6bSCho, Yu-Chen #define SPEC_in2_r1_o 0
5580c9274b6bSCho, Yu-Chen
in2_r1_16u(DisasContext * s,DisasOps * o)5581c9274b6bSCho, Yu-Chen static void in2_r1_16u(DisasContext *s, DisasOps *o)
5582c9274b6bSCho, Yu-Chen {
5583c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5584c9274b6bSCho, Yu-Chen tcg_gen_ext16u_i64(o->in2, regs[get_field(s, r1)]);
5585c9274b6bSCho, Yu-Chen }
5586c9274b6bSCho, Yu-Chen #define SPEC_in2_r1_16u 0
5587c9274b6bSCho, Yu-Chen
in2_r1_32u(DisasContext * s,DisasOps * o)5588c9274b6bSCho, Yu-Chen static void in2_r1_32u(DisasContext *s, DisasOps *o)
5589c9274b6bSCho, Yu-Chen {
5590c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5591c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r1)]);
5592c9274b6bSCho, Yu-Chen }
5593c9274b6bSCho, Yu-Chen #define SPEC_in2_r1_32u 0
5594c9274b6bSCho, Yu-Chen
in2_r1_D32(DisasContext * s,DisasOps * o)5595c9274b6bSCho, Yu-Chen static void in2_r1_D32(DisasContext *s, DisasOps *o)
5596c9274b6bSCho, Yu-Chen {
5597c9274b6bSCho, Yu-Chen int r1 = get_field(s, r1);
5598c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5599c9274b6bSCho, Yu-Chen tcg_gen_concat32_i64(o->in2, regs[r1 + 1], regs[r1]);
5600c9274b6bSCho, Yu-Chen }
5601c9274b6bSCho, Yu-Chen #define SPEC_in2_r1_D32 SPEC_r1_even
5602c9274b6bSCho, Yu-Chen
in2_r2(DisasContext * s,DisasOps * o)5603c9274b6bSCho, Yu-Chen static void in2_r2(DisasContext *s, DisasOps *o)
5604c9274b6bSCho, Yu-Chen {
5605c9274b6bSCho, Yu-Chen o->in2 = load_reg(get_field(s, r2));
5606c9274b6bSCho, Yu-Chen }
5607c9274b6bSCho, Yu-Chen #define SPEC_in2_r2 0
5608c9274b6bSCho, Yu-Chen
in2_r2_o(DisasContext * s,DisasOps * o)5609c9274b6bSCho, Yu-Chen static void in2_r2_o(DisasContext *s, DisasOps *o)
5610c9274b6bSCho, Yu-Chen {
5611c9274b6bSCho, Yu-Chen o->in2 = regs[get_field(s, r2)];
5612c9274b6bSCho, Yu-Chen }
5613c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_o 0
5614c9274b6bSCho, Yu-Chen
in2_r2_nz(DisasContext * s,DisasOps * o)5615c9274b6bSCho, Yu-Chen static void in2_r2_nz(DisasContext *s, DisasOps *o)
5616c9274b6bSCho, Yu-Chen {
5617c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
5618c9274b6bSCho, Yu-Chen if (r2 != 0) {
5619c9274b6bSCho, Yu-Chen o->in2 = load_reg(r2);
5620c9274b6bSCho, Yu-Chen }
5621c9274b6bSCho, Yu-Chen }
5622c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_nz 0
5623c9274b6bSCho, Yu-Chen
in2_r2_8s(DisasContext * s,DisasOps * o)5624c9274b6bSCho, Yu-Chen static void in2_r2_8s(DisasContext *s, DisasOps *o)
5625c9274b6bSCho, Yu-Chen {
5626c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5627c9274b6bSCho, Yu-Chen tcg_gen_ext8s_i64(o->in2, regs[get_field(s, r2)]);
5628c9274b6bSCho, Yu-Chen }
5629c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_8s 0
5630c9274b6bSCho, Yu-Chen
in2_r2_8u(DisasContext * s,DisasOps * o)5631c9274b6bSCho, Yu-Chen static void in2_r2_8u(DisasContext *s, DisasOps *o)
5632c9274b6bSCho, Yu-Chen {
5633c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5634c9274b6bSCho, Yu-Chen tcg_gen_ext8u_i64(o->in2, regs[get_field(s, r2)]);
5635c9274b6bSCho, Yu-Chen }
5636c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_8u 0
5637c9274b6bSCho, Yu-Chen
in2_r2_16s(DisasContext * s,DisasOps * o)5638c9274b6bSCho, Yu-Chen static void in2_r2_16s(DisasContext *s, DisasOps *o)
5639c9274b6bSCho, Yu-Chen {
5640c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5641c9274b6bSCho, Yu-Chen tcg_gen_ext16s_i64(o->in2, regs[get_field(s, r2)]);
5642c9274b6bSCho, Yu-Chen }
5643c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_16s 0
5644c9274b6bSCho, Yu-Chen
in2_r2_16u(DisasContext * s,DisasOps * o)5645c9274b6bSCho, Yu-Chen static void in2_r2_16u(DisasContext *s, DisasOps *o)
5646c9274b6bSCho, Yu-Chen {
5647c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5648c9274b6bSCho, Yu-Chen tcg_gen_ext16u_i64(o->in2, regs[get_field(s, r2)]);
5649c9274b6bSCho, Yu-Chen }
5650c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_16u 0
5651c9274b6bSCho, Yu-Chen
in2_r3(DisasContext * s,DisasOps * o)5652c9274b6bSCho, Yu-Chen static void in2_r3(DisasContext *s, DisasOps *o)
5653c9274b6bSCho, Yu-Chen {
5654c9274b6bSCho, Yu-Chen o->in2 = load_reg(get_field(s, r3));
5655c9274b6bSCho, Yu-Chen }
5656c9274b6bSCho, Yu-Chen #define SPEC_in2_r3 0
5657c9274b6bSCho, Yu-Chen
in2_r3_D64(DisasContext * s,DisasOps * o)56581fcd84faSRichard Henderson static void in2_r3_D64(DisasContext *s, DisasOps *o)
56591fcd84faSRichard Henderson {
56601fcd84faSRichard Henderson int r3 = get_field(s, r3);
56611fcd84faSRichard Henderson o->in2_128 = tcg_temp_new_i128();
56621fcd84faSRichard Henderson tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]);
56631fcd84faSRichard Henderson }
56641fcd84faSRichard Henderson #define SPEC_in2_r3_D64 SPEC_r3_even
56651fcd84faSRichard Henderson
in2_r3_sr32(DisasContext * s,DisasOps * o)5666c9274b6bSCho, Yu-Chen static void in2_r3_sr32(DisasContext *s, DisasOps *o)
5667c9274b6bSCho, Yu-Chen {
5668c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5669c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(o->in2, regs[get_field(s, r3)], 32);
5670c9274b6bSCho, Yu-Chen }
5671c9274b6bSCho, Yu-Chen #define SPEC_in2_r3_sr32 0
5672c9274b6bSCho, Yu-Chen
in2_r3_32u(DisasContext * s,DisasOps * o)5673c9274b6bSCho, Yu-Chen static void in2_r3_32u(DisasContext *s, DisasOps *o)
5674c9274b6bSCho, Yu-Chen {
5675c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5676c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r3)]);
5677c9274b6bSCho, Yu-Chen }
5678c9274b6bSCho, Yu-Chen #define SPEC_in2_r3_32u 0
5679c9274b6bSCho, Yu-Chen
in2_r2_32s(DisasContext * s,DisasOps * o)5680c9274b6bSCho, Yu-Chen static void in2_r2_32s(DisasContext *s, DisasOps *o)
5681c9274b6bSCho, Yu-Chen {
5682c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5683c9274b6bSCho, Yu-Chen tcg_gen_ext32s_i64(o->in2, regs[get_field(s, r2)]);
5684c9274b6bSCho, Yu-Chen }
5685c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_32s 0
5686c9274b6bSCho, Yu-Chen
in2_r2_32u(DisasContext * s,DisasOps * o)5687c9274b6bSCho, Yu-Chen static void in2_r2_32u(DisasContext *s, DisasOps *o)
5688c9274b6bSCho, Yu-Chen {
5689c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5690c9274b6bSCho, Yu-Chen tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r2)]);
5691c9274b6bSCho, Yu-Chen }
5692c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_32u 0
5693c9274b6bSCho, Yu-Chen
in2_r2_sr32(DisasContext * s,DisasOps * o)5694c9274b6bSCho, Yu-Chen static void in2_r2_sr32(DisasContext *s, DisasOps *o)
5695c9274b6bSCho, Yu-Chen {
5696c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5697c9274b6bSCho, Yu-Chen tcg_gen_shri_i64(o->in2, regs[get_field(s, r2)], 32);
5698c9274b6bSCho, Yu-Chen }
5699c9274b6bSCho, Yu-Chen #define SPEC_in2_r2_sr32 0
5700c9274b6bSCho, Yu-Chen
in2_e2(DisasContext * s,DisasOps * o)5701c9274b6bSCho, Yu-Chen static void in2_e2(DisasContext *s, DisasOps *o)
5702c9274b6bSCho, Yu-Chen {
5703c9274b6bSCho, Yu-Chen o->in2 = load_freg32_i64(get_field(s, r2));
5704c9274b6bSCho, Yu-Chen }
5705c9274b6bSCho, Yu-Chen #define SPEC_in2_e2 0
5706c9274b6bSCho, Yu-Chen
in2_f2(DisasContext * s,DisasOps * o)5707c9274b6bSCho, Yu-Chen static void in2_f2(DisasContext *s, DisasOps *o)
5708c9274b6bSCho, Yu-Chen {
5709c9274b6bSCho, Yu-Chen o->in2 = load_freg(get_field(s, r2));
5710c9274b6bSCho, Yu-Chen }
5711c9274b6bSCho, Yu-Chen #define SPEC_in2_f2 0
5712c9274b6bSCho, Yu-Chen
in2_x2(DisasContext * s,DisasOps * o)57132b91240fSRichard Henderson static void in2_x2(DisasContext *s, DisasOps *o)
57142b91240fSRichard Henderson {
57152b91240fSRichard Henderson o->in2_128 = load_freg_128(get_field(s, r2));
57162b91240fSRichard Henderson }
57172b91240fSRichard Henderson #define SPEC_in2_x2 SPEC_r2_f128
57182b91240fSRichard Henderson
5719c9274b6bSCho, Yu-Chen /* Load the low double word of an extended (128-bit) format FP number */
in2_x2l(DisasContext * s,DisasOps * o)5720c9274b6bSCho, Yu-Chen static void in2_x2l(DisasContext *s, DisasOps *o)
5721c9274b6bSCho, Yu-Chen {
5722c9274b6bSCho, Yu-Chen o->in2 = load_freg(get_field(s, r2) + 2);
5723c9274b6bSCho, Yu-Chen }
5724c9274b6bSCho, Yu-Chen #define SPEC_in2_x2l SPEC_r2_f128
5725c9274b6bSCho, Yu-Chen
in2_ra2(DisasContext * s,DisasOps * o)5726c9274b6bSCho, Yu-Chen static void in2_ra2(DisasContext *s, DisasOps *o)
5727c9274b6bSCho, Yu-Chen {
5728c9274b6bSCho, Yu-Chen int r2 = get_field(s, r2);
5729c9274b6bSCho, Yu-Chen
5730c9274b6bSCho, Yu-Chen /* Note: *don't* treat !r2 as 0, use the reg value. */
5731c9274b6bSCho, Yu-Chen o->in2 = tcg_temp_new_i64();
5732c9274b6bSCho, Yu-Chen gen_addi_and_wrap_i64(s, o->in2, regs[r2], 0);
5733c9274b6bSCho, Yu-Chen }
5734c9274b6bSCho, Yu-Chen #define SPEC_in2_ra2 0
5735c9274b6bSCho, Yu-Chen
in2_ra2_E(DisasContext * s,DisasOps * o)5736761b0aa9SIlya Leoshkevich static void in2_ra2_E(DisasContext *s, DisasOps *o)
5737761b0aa9SIlya Leoshkevich {
5738761b0aa9SIlya Leoshkevich return in2_ra2(s, o);
5739761b0aa9SIlya Leoshkevich }
5740761b0aa9SIlya Leoshkevich #define SPEC_in2_ra2_E SPEC_r2_even
5741761b0aa9SIlya Leoshkevich
in2_a2(DisasContext * s,DisasOps * o)5742c9274b6bSCho, Yu-Chen static void in2_a2(DisasContext *s, DisasOps *o)
5743c9274b6bSCho, Yu-Chen {
5744c9274b6bSCho, Yu-Chen int x2 = have_field(s, x2) ? get_field(s, x2) : 0;
5745c9274b6bSCho, Yu-Chen o->in2 = get_address(s, x2, get_field(s, b2), get_field(s, d2));
5746c9274b6bSCho, Yu-Chen }
5747c9274b6bSCho, Yu-Chen #define SPEC_in2_a2 0
5748c9274b6bSCho, Yu-Chen
gen_ri2(DisasContext * s)5749bdbc87e3SRichard Henderson static TCGv gen_ri2(DisasContext *s)
5750bdbc87e3SRichard Henderson {
5751e8ecdfebSIlya Leoshkevich TCGv ri2 = NULL;
5752e8ecdfebSIlya Leoshkevich bool is_imm;
5753e8ecdfebSIlya Leoshkevich int imm;
5754703d03a4SIlya Leoshkevich
5755e8ecdfebSIlya Leoshkevich disas_jdest(s, i2, is_imm, imm, ri2);
5756e8ecdfebSIlya Leoshkevich if (is_imm) {
5757349372ffSIlya Leoshkevich ri2 = tcg_constant_i64(s->base.pc_next + (int64_t)imm * 2);
5758703d03a4SIlya Leoshkevich }
5759703d03a4SIlya Leoshkevich
5760703d03a4SIlya Leoshkevich return ri2;
5761bdbc87e3SRichard Henderson }
5762bdbc87e3SRichard Henderson
in2_ri2(DisasContext * s,DisasOps * o)5763c9274b6bSCho, Yu-Chen static void in2_ri2(DisasContext *s, DisasOps *o)
5764c9274b6bSCho, Yu-Chen {
5765bdbc87e3SRichard Henderson o->in2 = gen_ri2(s);
5766c9274b6bSCho, Yu-Chen }
5767c9274b6bSCho, Yu-Chen #define SPEC_in2_ri2 0
5768c9274b6bSCho, Yu-Chen
in2_sh(DisasContext * s,DisasOps * o)57696da170beSIlya Leoshkevich static void in2_sh(DisasContext *s, DisasOps *o)
5770c9274b6bSCho, Yu-Chen {
57716da170beSIlya Leoshkevich int b2 = get_field(s, b2);
57726da170beSIlya Leoshkevich int d2 = get_field(s, d2);
5773c9274b6bSCho, Yu-Chen
57746da170beSIlya Leoshkevich if (b2 == 0) {
57755bd9790eSRichard Henderson o->in2 = tcg_constant_i64(d2 & 0x3f);
57766da170beSIlya Leoshkevich } else {
57776da170beSIlya Leoshkevich o->in2 = get_address(s, 0, b2, d2);
57786da170beSIlya Leoshkevich tcg_gen_andi_i64(o->in2, o->in2, 0x3f);
5779c9274b6bSCho, Yu-Chen }
57806da170beSIlya Leoshkevich }
57816da170beSIlya Leoshkevich #define SPEC_in2_sh 0
5782c9274b6bSCho, Yu-Chen
in2_m2_8u(DisasContext * s,DisasOps * o)5783c9274b6bSCho, Yu-Chen static void in2_m2_8u(DisasContext *s, DisasOps *o)
5784c9274b6bSCho, Yu-Chen {
5785c9274b6bSCho, Yu-Chen in2_a2(s, o);
5786e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB);
5787c9274b6bSCho, Yu-Chen }
5788c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_8u 0
5789c9274b6bSCho, Yu-Chen
in2_m2_16s(DisasContext * s,DisasOps * o)5790c9274b6bSCho, Yu-Chen static void in2_m2_16s(DisasContext *s, DisasOps *o)
5791c9274b6bSCho, Yu-Chen {
5792c9274b6bSCho, Yu-Chen in2_a2(s, o);
5793e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESW);
5794c9274b6bSCho, Yu-Chen }
5795c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_16s 0
5796c9274b6bSCho, Yu-Chen
in2_m2_16u(DisasContext * s,DisasOps * o)5797c9274b6bSCho, Yu-Chen static void in2_m2_16u(DisasContext *s, DisasOps *o)
5798c9274b6bSCho, Yu-Chen {
5799c9274b6bSCho, Yu-Chen in2_a2(s, o);
5800e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUW);
5801c9274b6bSCho, Yu-Chen }
5802c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_16u 0
5803c9274b6bSCho, Yu-Chen
in2_m2_32s(DisasContext * s,DisasOps * o)5804c9274b6bSCho, Yu-Chen static void in2_m2_32s(DisasContext *s, DisasOps *o)
5805c9274b6bSCho, Yu-Chen {
5806c9274b6bSCho, Yu-Chen in2_a2(s, o);
5807e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TESL);
5808c9274b6bSCho, Yu-Chen }
5809c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_32s 0
5810c9274b6bSCho, Yu-Chen
in2_m2_32u(DisasContext * s,DisasOps * o)5811c9274b6bSCho, Yu-Chen static void in2_m2_32u(DisasContext *s, DisasOps *o)
5812c9274b6bSCho, Yu-Chen {
5813c9274b6bSCho, Yu-Chen in2_a2(s, o);
5814e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUL);
5815c9274b6bSCho, Yu-Chen }
5816c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_32u 0
5817c9274b6bSCho, Yu-Chen
5818c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
in2_m2_32ua(DisasContext * s,DisasOps * o)5819c9274b6bSCho, Yu-Chen static void in2_m2_32ua(DisasContext *s, DisasOps *o)
5820c9274b6bSCho, Yu-Chen {
5821c9274b6bSCho, Yu-Chen in2_a2(s, o);
5822c9274b6bSCho, Yu-Chen tcg_gen_qemu_ld_tl(o->in2, o->in2, get_mem_index(s), MO_TEUL | MO_ALIGN);
5823c9274b6bSCho, Yu-Chen }
5824c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_32ua 0
5825c9274b6bSCho, Yu-Chen #endif
5826c9274b6bSCho, Yu-Chen
in2_m2_64(DisasContext * s,DisasOps * o)5827c9274b6bSCho, Yu-Chen static void in2_m2_64(DisasContext *s, DisasOps *o)
5828c9274b6bSCho, Yu-Chen {
5829c9274b6bSCho, Yu-Chen in2_a2(s, o);
5830e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
5831c9274b6bSCho, Yu-Chen }
5832c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_64 0
5833c9274b6bSCho, Yu-Chen
in2_m2_64w(DisasContext * s,DisasOps * o)5834c9274b6bSCho, Yu-Chen static void in2_m2_64w(DisasContext *s, DisasOps *o)
5835c9274b6bSCho, Yu-Chen {
5836c9274b6bSCho, Yu-Chen in2_a2(s, o);
5837e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ);
5838c9274b6bSCho, Yu-Chen gen_addi_and_wrap_i64(s, o->in2, o->in2, 0);
5839c9274b6bSCho, Yu-Chen }
5840c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_64w 0
5841c9274b6bSCho, Yu-Chen
5842c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
in2_m2_64a(DisasContext * s,DisasOps * o)5843c9274b6bSCho, Yu-Chen static void in2_m2_64a(DisasContext *s, DisasOps *o)
5844c9274b6bSCho, Yu-Chen {
5845c9274b6bSCho, Yu-Chen in2_a2(s, o);
5846fc313c64SFrédéric Pétrot tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_TEUQ | MO_ALIGN);
5847c9274b6bSCho, Yu-Chen }
5848c9274b6bSCho, Yu-Chen #define SPEC_in2_m2_64a 0
5849c9274b6bSCho, Yu-Chen #endif
5850c9274b6bSCho, Yu-Chen
in2_mri2_16s(DisasContext * s,DisasOps * o)585154fce97cSNina Schoetterl-Glausch static void in2_mri2_16s(DisasContext *s, DisasOps *o)
585254fce97cSNina Schoetterl-Glausch {
585354fce97cSNina Schoetterl-Glausch o->in2 = tcg_temp_new_i64();
5854e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TESW);
585554fce97cSNina Schoetterl-Glausch }
585654fce97cSNina Schoetterl-Glausch #define SPEC_in2_mri2_16s 0
585754fce97cSNina Schoetterl-Glausch
in2_mri2_16u(DisasContext * s,DisasOps * o)5858c9274b6bSCho, Yu-Chen static void in2_mri2_16u(DisasContext *s, DisasOps *o)
5859c9274b6bSCho, Yu-Chen {
5860bdbc87e3SRichard Henderson o->in2 = tcg_temp_new_i64();
5861e87027d0SRichard Henderson tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s), MO_TEUW);
5862c9274b6bSCho, Yu-Chen }
5863c9274b6bSCho, Yu-Chen #define SPEC_in2_mri2_16u 0
5864c9274b6bSCho, Yu-Chen
in2_mri2_32s(DisasContext * s,DisasOps * o)5865c9274b6bSCho, Yu-Chen static void in2_mri2_32s(DisasContext *s, DisasOps *o)
5866c9274b6bSCho, Yu-Chen {
5867bdbc87e3SRichard Henderson o->in2 = tcg_temp_new_i64();
5868227a9f79SIlya Leoshkevich tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s),
5869227a9f79SIlya Leoshkevich MO_TESL | MO_ALIGN);
5870c9274b6bSCho, Yu-Chen }
5871c9274b6bSCho, Yu-Chen #define SPEC_in2_mri2_32s 0
5872c9274b6bSCho, Yu-Chen
in2_mri2_32u(DisasContext * s,DisasOps * o)5873c9274b6bSCho, Yu-Chen static void in2_mri2_32u(DisasContext *s, DisasOps *o)
5874c9274b6bSCho, Yu-Chen {
5875bdbc87e3SRichard Henderson o->in2 = tcg_temp_new_i64();
58760708220cSIlya Leoshkevich tcg_gen_qemu_ld_tl(o->in2, gen_ri2(s), get_mem_index(s),
58770708220cSIlya Leoshkevich MO_TEUL | MO_ALIGN);
5878c9274b6bSCho, Yu-Chen }
5879c9274b6bSCho, Yu-Chen #define SPEC_in2_mri2_32u 0
5880c9274b6bSCho, Yu-Chen
in2_mri2_64(DisasContext * s,DisasOps * o)5881c9274b6bSCho, Yu-Chen static void in2_mri2_64(DisasContext *s, DisasOps *o)
5882c9274b6bSCho, Yu-Chen {
5883bdbc87e3SRichard Henderson o->in2 = tcg_temp_new_i64();
58842b25c824SIlya Leoshkevich tcg_gen_qemu_ld_i64(o->in2, gen_ri2(s), get_mem_index(s),
58852b25c824SIlya Leoshkevich MO_TEUQ | MO_ALIGN);
5886c9274b6bSCho, Yu-Chen }
5887c9274b6bSCho, Yu-Chen #define SPEC_in2_mri2_64 0
5888c9274b6bSCho, Yu-Chen
in2_i2(DisasContext * s,DisasOps * o)5889c9274b6bSCho, Yu-Chen static void in2_i2(DisasContext *s, DisasOps *o)
5890c9274b6bSCho, Yu-Chen {
58915bd9790eSRichard Henderson o->in2 = tcg_constant_i64(get_field(s, i2));
5892c9274b6bSCho, Yu-Chen }
5893c9274b6bSCho, Yu-Chen #define SPEC_in2_i2 0
5894c9274b6bSCho, Yu-Chen
in2_i2_8u(DisasContext * s,DisasOps * o)5895c9274b6bSCho, Yu-Chen static void in2_i2_8u(DisasContext *s, DisasOps *o)
5896c9274b6bSCho, Yu-Chen {
58975bd9790eSRichard Henderson o->in2 = tcg_constant_i64((uint8_t)get_field(s, i2));
5898c9274b6bSCho, Yu-Chen }
5899c9274b6bSCho, Yu-Chen #define SPEC_in2_i2_8u 0
5900c9274b6bSCho, Yu-Chen
in2_i2_16u(DisasContext * s,DisasOps * o)5901c9274b6bSCho, Yu-Chen static void in2_i2_16u(DisasContext *s, DisasOps *o)
5902c9274b6bSCho, Yu-Chen {
59035bd9790eSRichard Henderson o->in2 = tcg_constant_i64((uint16_t)get_field(s, i2));
5904c9274b6bSCho, Yu-Chen }
5905c9274b6bSCho, Yu-Chen #define SPEC_in2_i2_16u 0
5906c9274b6bSCho, Yu-Chen
in2_i2_32u(DisasContext * s,DisasOps * o)5907c9274b6bSCho, Yu-Chen static void in2_i2_32u(DisasContext *s, DisasOps *o)
5908c9274b6bSCho, Yu-Chen {
59095bd9790eSRichard Henderson o->in2 = tcg_constant_i64((uint32_t)get_field(s, i2));
5910c9274b6bSCho, Yu-Chen }
5911c9274b6bSCho, Yu-Chen #define SPEC_in2_i2_32u 0
5912c9274b6bSCho, Yu-Chen
in2_i2_16u_shl(DisasContext * s,DisasOps * o)5913c9274b6bSCho, Yu-Chen static void in2_i2_16u_shl(DisasContext *s, DisasOps *o)
5914c9274b6bSCho, Yu-Chen {
5915c9274b6bSCho, Yu-Chen uint64_t i2 = (uint16_t)get_field(s, i2);
59165bd9790eSRichard Henderson o->in2 = tcg_constant_i64(i2 << s->insn->data);
5917c9274b6bSCho, Yu-Chen }
5918c9274b6bSCho, Yu-Chen #define SPEC_in2_i2_16u_shl 0
5919c9274b6bSCho, Yu-Chen
in2_i2_32u_shl(DisasContext * s,DisasOps * o)5920c9274b6bSCho, Yu-Chen static void in2_i2_32u_shl(DisasContext *s, DisasOps *o)
5921c9274b6bSCho, Yu-Chen {
5922c9274b6bSCho, Yu-Chen uint64_t i2 = (uint32_t)get_field(s, i2);
59235bd9790eSRichard Henderson o->in2 = tcg_constant_i64(i2 << s->insn->data);
5924c9274b6bSCho, Yu-Chen }
5925c9274b6bSCho, Yu-Chen #define SPEC_in2_i2_32u_shl 0
5926c9274b6bSCho, Yu-Chen
5927c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
in2_insn(DisasContext * s,DisasOps * o)5928c9274b6bSCho, Yu-Chen static void in2_insn(DisasContext *s, DisasOps *o)
5929c9274b6bSCho, Yu-Chen {
59305bd9790eSRichard Henderson o->in2 = tcg_constant_i64(s->fields.raw_insn);
5931c9274b6bSCho, Yu-Chen }
5932c9274b6bSCho, Yu-Chen #define SPEC_in2_insn 0
5933c9274b6bSCho, Yu-Chen #endif
5934c9274b6bSCho, Yu-Chen
5935c9274b6bSCho, Yu-Chen /* ====================================================================== */
5936c9274b6bSCho, Yu-Chen
5937c9274b6bSCho, Yu-Chen /* Find opc within the table of insns. This is formulated as a switch
5938c9274b6bSCho, Yu-Chen statement so that (1) we get compile-time notice of cut-paste errors
5939c9274b6bSCho, Yu-Chen for duplicated opcodes, and (2) the compiler generates the binary
5940c9274b6bSCho, Yu-Chen search tree, rather than us having to post-process the table. */
5941c9274b6bSCho, Yu-Chen
5942c9274b6bSCho, Yu-Chen #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
5943c9274b6bSCho, Yu-Chen E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0, 0)
5944c9274b6bSCho, Yu-Chen
5945c9274b6bSCho, Yu-Chen #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
5946c9274b6bSCho, Yu-Chen E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, 0)
5947c9274b6bSCho, Yu-Chen
5948c9274b6bSCho, Yu-Chen #define F(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, FL) \
5949c9274b6bSCho, Yu-Chen E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0, FL)
5950c9274b6bSCho, Yu-Chen
5951c9274b6bSCho, Yu-Chen #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) insn_ ## NM,
5952c9274b6bSCho, Yu-Chen
5953c9274b6bSCho, Yu-Chen enum DisasInsnEnum {
59549cef8d99SPhilippe Mathieu-Daudé #include "insn-data.h.inc"
5955c9274b6bSCho, Yu-Chen };
5956c9274b6bSCho, Yu-Chen
5957c9274b6bSCho, Yu-Chen #undef E
5958c9274b6bSCho, Yu-Chen #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) { \
5959c9274b6bSCho, Yu-Chen .opc = OPC, \
5960c9274b6bSCho, Yu-Chen .flags = FL, \
5961c9274b6bSCho, Yu-Chen .fmt = FMT_##FT, \
5962c9274b6bSCho, Yu-Chen .fac = FAC_##FC, \
5963c9274b6bSCho, Yu-Chen .spec = SPEC_in1_##I1 | SPEC_in2_##I2 | SPEC_prep_##P | SPEC_wout_##W, \
5964c9274b6bSCho, Yu-Chen .name = #NM, \
5965c9274b6bSCho, Yu-Chen .help_in1 = in1_##I1, \
5966c9274b6bSCho, Yu-Chen .help_in2 = in2_##I2, \
5967c9274b6bSCho, Yu-Chen .help_prep = prep_##P, \
5968c9274b6bSCho, Yu-Chen .help_wout = wout_##W, \
5969c9274b6bSCho, Yu-Chen .help_cout = cout_##CC, \
5970c9274b6bSCho, Yu-Chen .help_op = op_##OP, \
5971c9274b6bSCho, Yu-Chen .data = D \
5972c9274b6bSCho, Yu-Chen },
5973c9274b6bSCho, Yu-Chen
5974c9274b6bSCho, Yu-Chen /* Allow 0 to be used for NULL in the table below. */
5975c9274b6bSCho, Yu-Chen #define in1_0 NULL
5976c9274b6bSCho, Yu-Chen #define in2_0 NULL
5977c9274b6bSCho, Yu-Chen #define prep_0 NULL
5978c9274b6bSCho, Yu-Chen #define wout_0 NULL
5979c9274b6bSCho, Yu-Chen #define cout_0 NULL
5980c9274b6bSCho, Yu-Chen #define op_0 NULL
5981c9274b6bSCho, Yu-Chen
5982c9274b6bSCho, Yu-Chen #define SPEC_in1_0 0
5983c9274b6bSCho, Yu-Chen #define SPEC_in2_0 0
5984c9274b6bSCho, Yu-Chen #define SPEC_prep_0 0
5985c9274b6bSCho, Yu-Chen #define SPEC_wout_0 0
5986c9274b6bSCho, Yu-Chen
5987c9274b6bSCho, Yu-Chen /* Give smaller names to the various facilities. */
5988c9274b6bSCho, Yu-Chen #define FAC_Z S390_FEAT_ZARCH
5989c9274b6bSCho, Yu-Chen #define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
5990c9274b6bSCho, Yu-Chen #define FAC_DFP S390_FEAT_DFP
599100011706SDr. David Alan Gilbert #define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* DFP-rounding */
5992c9274b6bSCho, Yu-Chen #define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
5993c9274b6bSCho, Yu-Chen #define FAC_EE S390_FEAT_EXECUTE_EXT
5994c9274b6bSCho, Yu-Chen #define FAC_EI S390_FEAT_EXTENDED_IMMEDIATE
5995c9274b6bSCho, Yu-Chen #define FAC_FPE S390_FEAT_FLOATING_POINT_EXT
599600011706SDr. David Alan Gilbert #define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPS-sign-handling */
599700011706SDr. David Alan Gilbert #define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPR-GR-transfer */
5998c9274b6bSCho, Yu-Chen #define FAC_GIE S390_FEAT_GENERAL_INSTRUCTIONS_EXT
5999c9274b6bSCho, Yu-Chen #define FAC_HFP_MA S390_FEAT_HFP_MADDSUB
6000c9274b6bSCho, Yu-Chen #define FAC_HW S390_FEAT_STFLE_45 /* high-word */
600100011706SDr. David Alan Gilbert #define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* IEEE-exception-simulation */
6002c9274b6bSCho, Yu-Chen #define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
6003c9274b6bSCho, Yu-Chen #define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
6004c9274b6bSCho, Yu-Chen #define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
6005c9274b6bSCho, Yu-Chen #define FAC_LOC2 S390_FEAT_STFLE_53 /* load/store on condition 2 */
6006c9274b6bSCho, Yu-Chen #define FAC_LD S390_FEAT_LONG_DISPLACEMENT
6007c9274b6bSCho, Yu-Chen #define FAC_PC S390_FEAT_STFLE_45 /* population count */
6008c9274b6bSCho, Yu-Chen #define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
6009c9274b6bSCho, Yu-Chen #define FAC_SFLE S390_FEAT_STFLE
6010c9274b6bSCho, Yu-Chen #define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
6011c9274b6bSCho, Yu-Chen #define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
6012c9274b6bSCho, Yu-Chen #define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
6013c9274b6bSCho, Yu-Chen #define FAC_DAT_ENH S390_FEAT_DAT_ENH
6014c9274b6bSCho, Yu-Chen #define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
6015c9274b6bSCho, Yu-Chen #define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
6016c9274b6bSCho, Yu-Chen #define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
6017c9274b6bSCho, Yu-Chen #define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
6018c9274b6bSCho, Yu-Chen #define FAC_ETF3 S390_FEAT_EXTENDED_TRANSLATION_3
6019c9274b6bSCho, Yu-Chen #define FAC_MSA S390_FEAT_MSA /* message-security-assist facility */
6020c9274b6bSCho, Yu-Chen #define FAC_MSA3 S390_FEAT_MSA_EXT_3 /* msa-extension-3 facility */
6021c9274b6bSCho, Yu-Chen #define FAC_MSA4 S390_FEAT_MSA_EXT_4 /* msa-extension-4 facility */
6022c9274b6bSCho, Yu-Chen #define FAC_MSA5 S390_FEAT_MSA_EXT_5 /* msa-extension-5 facility */
6023c9274b6bSCho, Yu-Chen #define FAC_MSA8 S390_FEAT_MSA_EXT_8 /* msa-extension-8 facility */
6024c9274b6bSCho, Yu-Chen #define FAC_ECT S390_FEAT_EXTRACT_CPU_TIME
6025c9274b6bSCho, Yu-Chen #define FAC_PCI S390_FEAT_ZPCI /* z/PCI facility */
6026c9274b6bSCho, Yu-Chen #define FAC_AIS S390_FEAT_ADAPTER_INT_SUPPRESSION
6027c9274b6bSCho, Yu-Chen #define FAC_V S390_FEAT_VECTOR /* vector facility */
6028c9274b6bSCho, Yu-Chen #define FAC_VE S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
60291d706f31SDavid Miller #define FAC_VE2 S390_FEAT_VECTOR_ENH2 /* vector enhancements facility 2 */
6030c9274b6bSCho, Yu-Chen #define FAC_MIE2 S390_FEAT_MISC_INSTRUCTION_EXT2 /* miscellaneous-instruction-extensions facility 2 */
6031ea0a1053SDavid Miller #define FAC_MIE3 S390_FEAT_MISC_INSTRUCTION_EXT3 /* miscellaneous-instruction-extensions facility 3 */
6032c9274b6bSCho, Yu-Chen
6033c9274b6bSCho, Yu-Chen static const DisasInsn insn_info[] = {
60349cef8d99SPhilippe Mathieu-Daudé #include "insn-data.h.inc"
6035c9274b6bSCho, Yu-Chen };
6036c9274b6bSCho, Yu-Chen
6037c9274b6bSCho, Yu-Chen #undef E
6038c9274b6bSCho, Yu-Chen #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) \
6039c9274b6bSCho, Yu-Chen case OPC: return &insn_info[insn_ ## NM];
6040c9274b6bSCho, Yu-Chen
lookup_opc(uint16_t opc)6041c9274b6bSCho, Yu-Chen static const DisasInsn *lookup_opc(uint16_t opc)
6042c9274b6bSCho, Yu-Chen {
6043c9274b6bSCho, Yu-Chen switch (opc) {
60449cef8d99SPhilippe Mathieu-Daudé #include "insn-data.h.inc"
6045c9274b6bSCho, Yu-Chen default:
6046c9274b6bSCho, Yu-Chen return NULL;
6047c9274b6bSCho, Yu-Chen }
6048c9274b6bSCho, Yu-Chen }
6049c9274b6bSCho, Yu-Chen
6050c9274b6bSCho, Yu-Chen #undef F
6051c9274b6bSCho, Yu-Chen #undef E
6052c9274b6bSCho, Yu-Chen #undef D
6053c9274b6bSCho, Yu-Chen #undef C
6054c9274b6bSCho, Yu-Chen
6055c9274b6bSCho, Yu-Chen /* Extract a field from the insn. The INSN should be left-aligned in
6056c9274b6bSCho, Yu-Chen the uint64_t so that we can more easily utilize the big-bit-endian
6057c9274b6bSCho, Yu-Chen definitions we extract from the Principals of Operation. */
6058c9274b6bSCho, Yu-Chen
extract_field(DisasFields * o,const DisasField * f,uint64_t insn)6059c9274b6bSCho, Yu-Chen static void extract_field(DisasFields *o, const DisasField *f, uint64_t insn)
6060c9274b6bSCho, Yu-Chen {
6061c9274b6bSCho, Yu-Chen uint32_t r, m;
6062c9274b6bSCho, Yu-Chen
6063c9274b6bSCho, Yu-Chen if (f->size == 0) {
6064c9274b6bSCho, Yu-Chen return;
6065c9274b6bSCho, Yu-Chen }
6066c9274b6bSCho, Yu-Chen
6067c9274b6bSCho, Yu-Chen /* Zero extract the field from the insn. */
6068c9274b6bSCho, Yu-Chen r = (insn << f->beg) >> (64 - f->size);
6069c9274b6bSCho, Yu-Chen
6070c9274b6bSCho, Yu-Chen /* Sign-extend, or un-swap the field as necessary. */
6071c9274b6bSCho, Yu-Chen switch (f->type) {
6072c9274b6bSCho, Yu-Chen case 0: /* unsigned */
6073c9274b6bSCho, Yu-Chen break;
6074c9274b6bSCho, Yu-Chen case 1: /* signed */
6075c9274b6bSCho, Yu-Chen assert(f->size <= 32);
6076c9274b6bSCho, Yu-Chen m = 1u << (f->size - 1);
6077c9274b6bSCho, Yu-Chen r = (r ^ m) - m;
6078c9274b6bSCho, Yu-Chen break;
6079c9274b6bSCho, Yu-Chen case 2: /* dl+dh split, signed 20 bit. */
6080c9274b6bSCho, Yu-Chen r = ((int8_t)r << 12) | (r >> 8);
6081c9274b6bSCho, Yu-Chen break;
6082c9274b6bSCho, Yu-Chen case 3: /* MSB stored in RXB */
6083c9274b6bSCho, Yu-Chen g_assert(f->size == 4);
6084c9274b6bSCho, Yu-Chen switch (f->beg) {
6085c9274b6bSCho, Yu-Chen case 8:
6086c9274b6bSCho, Yu-Chen r |= extract64(insn, 63 - 36, 1) << 4;
6087c9274b6bSCho, Yu-Chen break;
6088c9274b6bSCho, Yu-Chen case 12:
6089c9274b6bSCho, Yu-Chen r |= extract64(insn, 63 - 37, 1) << 4;
6090c9274b6bSCho, Yu-Chen break;
6091c9274b6bSCho, Yu-Chen case 16:
6092c9274b6bSCho, Yu-Chen r |= extract64(insn, 63 - 38, 1) << 4;
6093c9274b6bSCho, Yu-Chen break;
6094c9274b6bSCho, Yu-Chen case 32:
6095c9274b6bSCho, Yu-Chen r |= extract64(insn, 63 - 39, 1) << 4;
6096c9274b6bSCho, Yu-Chen break;
6097c9274b6bSCho, Yu-Chen default:
6098c9274b6bSCho, Yu-Chen g_assert_not_reached();
6099c9274b6bSCho, Yu-Chen }
6100c9274b6bSCho, Yu-Chen break;
6101c9274b6bSCho, Yu-Chen default:
6102c9274b6bSCho, Yu-Chen abort();
6103c9274b6bSCho, Yu-Chen }
6104c9274b6bSCho, Yu-Chen
610557e28d34SPeter Maydell /*
610657e28d34SPeter Maydell * Validate that the "compressed" encoding we selected above is valid.
610757e28d34SPeter Maydell * I.e. we haven't made two different original fields overlap.
610857e28d34SPeter Maydell */
6109c9274b6bSCho, Yu-Chen assert(((o->presentC >> f->indexC) & 1) == 0);
6110c9274b6bSCho, Yu-Chen o->presentC |= 1 << f->indexC;
6111c9274b6bSCho, Yu-Chen o->presentO |= 1 << f->indexO;
6112c9274b6bSCho, Yu-Chen
6113c9274b6bSCho, Yu-Chen o->c[f->indexC] = r;
6114c9274b6bSCho, Yu-Chen }
6115c9274b6bSCho, Yu-Chen
6116c9274b6bSCho, Yu-Chen /* Lookup the insn at the current PC, extracting the operands into O and
6117c9274b6bSCho, Yu-Chen returning the info struct for the insn. Returns NULL for invalid insn. */
6118c9274b6bSCho, Yu-Chen
extract_insn(CPUS390XState * env,DisasContext * s)6119c9274b6bSCho, Yu-Chen static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s)
6120c9274b6bSCho, Yu-Chen {
6121c9274b6bSCho, Yu-Chen uint64_t insn, pc = s->base.pc_next;
6122c9274b6bSCho, Yu-Chen int op, op2, ilen;
6123c9274b6bSCho, Yu-Chen const DisasInsn *info;
6124c9274b6bSCho, Yu-Chen
6125c9274b6bSCho, Yu-Chen if (unlikely(s->ex_value)) {
61264c6163eaSRichard Henderson uint64_t be_insn;
61274c6163eaSRichard Henderson
6128c9274b6bSCho, Yu-Chen /* Drop the EX data now, so that it's clear on exception paths. */
6129ad75a51eSRichard Henderson tcg_gen_st_i64(tcg_constant_i64(0), tcg_env,
6130f1ea739bSRichard Henderson offsetof(CPUS390XState, ex_value));
6131c9274b6bSCho, Yu-Chen
6132c9274b6bSCho, Yu-Chen /* Extract the values saved by EXECUTE. */
6133c9274b6bSCho, Yu-Chen insn = s->ex_value & 0xffffffffffff0000ull;
6134c9274b6bSCho, Yu-Chen ilen = s->ex_value & 0xf;
6135171ce939SRichard Henderson op = insn >> 56;
6136f1ea739bSRichard Henderson
6137f1ea739bSRichard Henderson /* Register insn bytes with translator so plugins work. */
61384c6163eaSRichard Henderson be_insn = cpu_to_be64(insn);
6139171ce939SRichard Henderson translator_fake_ld(&s->base, &be_insn, get_ilen(op));
6140c9274b6bSCho, Yu-Chen } else {
61414e116893SIlya Leoshkevich insn = ld_code2(env, s, pc);
6142c9274b6bSCho, Yu-Chen op = (insn >> 8) & 0xff;
6143c9274b6bSCho, Yu-Chen ilen = get_ilen(op);
6144c9274b6bSCho, Yu-Chen switch (ilen) {
6145c9274b6bSCho, Yu-Chen case 2:
6146c9274b6bSCho, Yu-Chen insn = insn << 48;
6147c9274b6bSCho, Yu-Chen break;
6148c9274b6bSCho, Yu-Chen case 4:
61494e116893SIlya Leoshkevich insn = ld_code4(env, s, pc) << 32;
6150c9274b6bSCho, Yu-Chen break;
6151c9274b6bSCho, Yu-Chen case 6:
61524e116893SIlya Leoshkevich insn = (insn << 48) | (ld_code4(env, s, pc + 2) << 16);
6153c9274b6bSCho, Yu-Chen break;
6154c9274b6bSCho, Yu-Chen default:
6155c9274b6bSCho, Yu-Chen g_assert_not_reached();
6156c9274b6bSCho, Yu-Chen }
6157c9274b6bSCho, Yu-Chen }
6158c9274b6bSCho, Yu-Chen s->pc_tmp = s->base.pc_next + ilen;
6159c9274b6bSCho, Yu-Chen s->ilen = ilen;
6160c9274b6bSCho, Yu-Chen
6161c9274b6bSCho, Yu-Chen /* We can't actually determine the insn format until we've looked up
6162c9274b6bSCho, Yu-Chen the full insn opcode. Which we can't do without locating the
6163c9274b6bSCho, Yu-Chen secondary opcode. Assume by default that OP2 is at bit 40; for
6164c9274b6bSCho, Yu-Chen those smaller insns that don't actually have a secondary opcode
6165c9274b6bSCho, Yu-Chen this will correctly result in OP2 = 0. */
6166c9274b6bSCho, Yu-Chen switch (op) {
6167c9274b6bSCho, Yu-Chen case 0x01: /* E */
6168c9274b6bSCho, Yu-Chen case 0x80: /* S */
6169c9274b6bSCho, Yu-Chen case 0x82: /* S */
6170c9274b6bSCho, Yu-Chen case 0x93: /* S */
6171c9274b6bSCho, Yu-Chen case 0xb2: /* S, RRF, RRE, IE */
6172c9274b6bSCho, Yu-Chen case 0xb3: /* RRE, RRD, RRF */
6173c9274b6bSCho, Yu-Chen case 0xb9: /* RRE, RRF */
6174c9274b6bSCho, Yu-Chen case 0xe5: /* SSE, SIL */
6175c9274b6bSCho, Yu-Chen op2 = (insn << 8) >> 56;
6176c9274b6bSCho, Yu-Chen break;
6177c9274b6bSCho, Yu-Chen case 0xa5: /* RI */
6178c9274b6bSCho, Yu-Chen case 0xa7: /* RI */
6179c9274b6bSCho, Yu-Chen case 0xc0: /* RIL */
6180c9274b6bSCho, Yu-Chen case 0xc2: /* RIL */
6181c9274b6bSCho, Yu-Chen case 0xc4: /* RIL */
6182c9274b6bSCho, Yu-Chen case 0xc6: /* RIL */
6183c9274b6bSCho, Yu-Chen case 0xc8: /* SSF */
6184c9274b6bSCho, Yu-Chen case 0xcc: /* RIL */
6185c9274b6bSCho, Yu-Chen op2 = (insn << 12) >> 60;
6186c9274b6bSCho, Yu-Chen break;
6187c9274b6bSCho, Yu-Chen case 0xc5: /* MII */
6188c9274b6bSCho, Yu-Chen case 0xc7: /* SMI */
6189c9274b6bSCho, Yu-Chen case 0xd0 ... 0xdf: /* SS */
6190c9274b6bSCho, Yu-Chen case 0xe1: /* SS */
6191c9274b6bSCho, Yu-Chen case 0xe2: /* SS */
6192c9274b6bSCho, Yu-Chen case 0xe8: /* SS */
6193c9274b6bSCho, Yu-Chen case 0xe9: /* SS */
6194c9274b6bSCho, Yu-Chen case 0xea: /* SS */
6195c9274b6bSCho, Yu-Chen case 0xee ... 0xf3: /* SS */
6196c9274b6bSCho, Yu-Chen case 0xf8 ... 0xfd: /* SS */
6197c9274b6bSCho, Yu-Chen op2 = 0;
6198c9274b6bSCho, Yu-Chen break;
6199c9274b6bSCho, Yu-Chen default:
6200c9274b6bSCho, Yu-Chen op2 = (insn << 40) >> 56;
6201c9274b6bSCho, Yu-Chen break;
6202c9274b6bSCho, Yu-Chen }
6203c9274b6bSCho, Yu-Chen
6204c9274b6bSCho, Yu-Chen memset(&s->fields, 0, sizeof(s->fields));
6205c9274b6bSCho, Yu-Chen s->fields.raw_insn = insn;
6206c9274b6bSCho, Yu-Chen s->fields.op = op;
6207c9274b6bSCho, Yu-Chen s->fields.op2 = op2;
6208c9274b6bSCho, Yu-Chen
6209c9274b6bSCho, Yu-Chen /* Lookup the instruction. */
6210c9274b6bSCho, Yu-Chen info = lookup_opc(op << 8 | op2);
6211c9274b6bSCho, Yu-Chen s->insn = info;
6212c9274b6bSCho, Yu-Chen
6213c9274b6bSCho, Yu-Chen /* If we found it, extract the operands. */
6214c9274b6bSCho, Yu-Chen if (info != NULL) {
6215c9274b6bSCho, Yu-Chen DisasFormat fmt = info->fmt;
6216c9274b6bSCho, Yu-Chen int i;
6217c9274b6bSCho, Yu-Chen
6218c9274b6bSCho, Yu-Chen for (i = 0; i < NUM_C_FIELD; ++i) {
6219c9274b6bSCho, Yu-Chen extract_field(&s->fields, &format_info[fmt].op[i], insn);
6220c9274b6bSCho, Yu-Chen }
6221c9274b6bSCho, Yu-Chen }
6222c9274b6bSCho, Yu-Chen return info;
6223c9274b6bSCho, Yu-Chen }
6224c9274b6bSCho, Yu-Chen
is_afp_reg(int reg)6225c9274b6bSCho, Yu-Chen static bool is_afp_reg(int reg)
6226c9274b6bSCho, Yu-Chen {
6227c9274b6bSCho, Yu-Chen return reg % 2 || reg > 6;
6228c9274b6bSCho, Yu-Chen }
6229c9274b6bSCho, Yu-Chen
is_fp_pair(int reg)6230c9274b6bSCho, Yu-Chen static bool is_fp_pair(int reg)
6231c9274b6bSCho, Yu-Chen {
6232c9274b6bSCho, Yu-Chen /* 0,1,4,5,8,9,12,13: to exclude the others, check for single bit */
6233c9274b6bSCho, Yu-Chen return !(reg & 0x2);
6234c9274b6bSCho, Yu-Chen }
6235c9274b6bSCho, Yu-Chen
translate_one(CPUS390XState * env,DisasContext * s)6236c9274b6bSCho, Yu-Chen static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s)
6237c9274b6bSCho, Yu-Chen {
6238c9274b6bSCho, Yu-Chen const DisasInsn *insn;
6239c9274b6bSCho, Yu-Chen DisasJumpType ret = DISAS_NEXT;
6240c9274b6bSCho, Yu-Chen DisasOps o = {};
6241c9274b6bSCho, Yu-Chen bool icount = false;
6242c9274b6bSCho, Yu-Chen
6243c9274b6bSCho, Yu-Chen /* Search for the insn in the table. */
6244c9274b6bSCho, Yu-Chen insn = extract_insn(env, s);
6245c9274b6bSCho, Yu-Chen
62465d23d530SRichard Henderson /* Update insn_start now that we know the ILEN. */
6247b338970fSRichard Henderson tcg_set_insn_start_param(s->base.insn_start, 2, s->ilen);
6248c9274b6bSCho, Yu-Chen
6249c9274b6bSCho, Yu-Chen /* Not found means unimplemented/illegal opcode. */
6250c9274b6bSCho, Yu-Chen if (insn == NULL) {
6251c9274b6bSCho, Yu-Chen qemu_log_mask(LOG_UNIMP, "unimplemented opcode 0x%02x%02x\n",
6252c9274b6bSCho, Yu-Chen s->fields.op, s->fields.op2);
6253c9274b6bSCho, Yu-Chen gen_illegal_opcode(s);
6254c9274b6bSCho, Yu-Chen ret = DISAS_NORETURN;
6255c9274b6bSCho, Yu-Chen goto out;
6256c9274b6bSCho, Yu-Chen }
6257c9274b6bSCho, Yu-Chen
6258c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
625962613ca0SRichard Henderson if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) {
6260a47d08eeSRichard Henderson /* With ifetch set, psw_addr and cc_op are always up-to-date. */
6261a47d08eeSRichard Henderson gen_helper_per_ifetch(tcg_env, tcg_constant_i32(s->ilen));
6262c9274b6bSCho, Yu-Chen }
6263c9274b6bSCho, Yu-Chen #endif
6264c9274b6bSCho, Yu-Chen
6265c9274b6bSCho, Yu-Chen /* process flags */
6266c9274b6bSCho, Yu-Chen if (insn->flags) {
6267c9274b6bSCho, Yu-Chen /* privileged instruction */
6268c9274b6bSCho, Yu-Chen if ((s->base.tb->flags & FLAG_MASK_PSTATE) && (insn->flags & IF_PRIV)) {
6269c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_PRIVILEGED);
6270c9274b6bSCho, Yu-Chen ret = DISAS_NORETURN;
6271c9274b6bSCho, Yu-Chen goto out;
6272c9274b6bSCho, Yu-Chen }
6273c9274b6bSCho, Yu-Chen
6274c9274b6bSCho, Yu-Chen /* if AFP is not enabled, instructions and registers are forbidden */
6275c9274b6bSCho, Yu-Chen if (!(s->base.tb->flags & FLAG_MASK_AFP)) {
6276c9274b6bSCho, Yu-Chen uint8_t dxc = 0;
6277c9274b6bSCho, Yu-Chen
6278c9274b6bSCho, Yu-Chen if ((insn->flags & IF_AFP1) && is_afp_reg(get_field(s, r1))) {
6279c9274b6bSCho, Yu-Chen dxc = 1;
6280c9274b6bSCho, Yu-Chen }
6281c9274b6bSCho, Yu-Chen if ((insn->flags & IF_AFP2) && is_afp_reg(get_field(s, r2))) {
6282c9274b6bSCho, Yu-Chen dxc = 1;
6283c9274b6bSCho, Yu-Chen }
6284c9274b6bSCho, Yu-Chen if ((insn->flags & IF_AFP3) && is_afp_reg(get_field(s, r3))) {
6285c9274b6bSCho, Yu-Chen dxc = 1;
6286c9274b6bSCho, Yu-Chen }
6287c9274b6bSCho, Yu-Chen if (insn->flags & IF_BFP) {
6288c9274b6bSCho, Yu-Chen dxc = 2;
6289c9274b6bSCho, Yu-Chen }
6290c9274b6bSCho, Yu-Chen if (insn->flags & IF_DFP) {
6291c9274b6bSCho, Yu-Chen dxc = 3;
6292c9274b6bSCho, Yu-Chen }
6293c9274b6bSCho, Yu-Chen if (insn->flags & IF_VEC) {
6294c9274b6bSCho, Yu-Chen dxc = 0xfe;
6295c9274b6bSCho, Yu-Chen }
6296c9274b6bSCho, Yu-Chen if (dxc) {
6297c9274b6bSCho, Yu-Chen gen_data_exception(dxc);
6298c9274b6bSCho, Yu-Chen ret = DISAS_NORETURN;
6299c9274b6bSCho, Yu-Chen goto out;
6300c9274b6bSCho, Yu-Chen }
6301c9274b6bSCho, Yu-Chen }
6302c9274b6bSCho, Yu-Chen
6303c9274b6bSCho, Yu-Chen /* if vector instructions not enabled, executing them is forbidden */
6304c9274b6bSCho, Yu-Chen if (insn->flags & IF_VEC) {
6305c9274b6bSCho, Yu-Chen if (!((s->base.tb->flags & FLAG_MASK_VECTOR))) {
6306c9274b6bSCho, Yu-Chen gen_data_exception(0xfe);
6307c9274b6bSCho, Yu-Chen ret = DISAS_NORETURN;
6308c9274b6bSCho, Yu-Chen goto out;
6309c9274b6bSCho, Yu-Chen }
6310c9274b6bSCho, Yu-Chen }
6311c9274b6bSCho, Yu-Chen
6312c9274b6bSCho, Yu-Chen /* input/output is the special case for icount mode */
6313c9274b6bSCho, Yu-Chen if (unlikely(insn->flags & IF_IO)) {
6314dfd1b812SRichard Henderson icount = translator_io_start(&s->base);
6315c9274b6bSCho, Yu-Chen }
6316c9274b6bSCho, Yu-Chen }
6317c9274b6bSCho, Yu-Chen
6318c9274b6bSCho, Yu-Chen /* Check for insn specification exceptions. */
6319c9274b6bSCho, Yu-Chen if (insn->spec) {
6320c9274b6bSCho, Yu-Chen if ((insn->spec & SPEC_r1_even && get_field(s, r1) & 1) ||
6321c9274b6bSCho, Yu-Chen (insn->spec & SPEC_r2_even && get_field(s, r2) & 1) ||
6322c9274b6bSCho, Yu-Chen (insn->spec & SPEC_r3_even && get_field(s, r3) & 1) ||
6323c9274b6bSCho, Yu-Chen (insn->spec & SPEC_r1_f128 && !is_fp_pair(get_field(s, r1))) ||
6324c9274b6bSCho, Yu-Chen (insn->spec & SPEC_r2_f128 && !is_fp_pair(get_field(s, r2)))) {
6325c9274b6bSCho, Yu-Chen gen_program_exception(s, PGM_SPECIFICATION);
6326c9274b6bSCho, Yu-Chen ret = DISAS_NORETURN;
6327c9274b6bSCho, Yu-Chen goto out;
6328c9274b6bSCho, Yu-Chen }
6329c9274b6bSCho, Yu-Chen }
6330c9274b6bSCho, Yu-Chen
6331c9274b6bSCho, Yu-Chen /* Implement the instruction. */
6332c9274b6bSCho, Yu-Chen if (insn->help_in1) {
6333c9274b6bSCho, Yu-Chen insn->help_in1(s, &o);
6334c9274b6bSCho, Yu-Chen }
6335c9274b6bSCho, Yu-Chen if (insn->help_in2) {
6336c9274b6bSCho, Yu-Chen insn->help_in2(s, &o);
6337c9274b6bSCho, Yu-Chen }
6338c9274b6bSCho, Yu-Chen if (insn->help_prep) {
6339c9274b6bSCho, Yu-Chen insn->help_prep(s, &o);
6340c9274b6bSCho, Yu-Chen }
6341c9274b6bSCho, Yu-Chen if (insn->help_op) {
6342c9274b6bSCho, Yu-Chen ret = insn->help_op(s, &o);
6343*be0fcbc4SRichard Henderson if (ret == DISAS_NORETURN) {
6344*be0fcbc4SRichard Henderson goto out;
6345c9274b6bSCho, Yu-Chen }
6346*be0fcbc4SRichard Henderson }
6347c9274b6bSCho, Yu-Chen if (insn->help_wout) {
6348c9274b6bSCho, Yu-Chen insn->help_wout(s, &o);
6349c9274b6bSCho, Yu-Chen }
6350c9274b6bSCho, Yu-Chen if (insn->help_cout) {
6351c9274b6bSCho, Yu-Chen insn->help_cout(s, &o);
6352c9274b6bSCho, Yu-Chen }
6353c9274b6bSCho, Yu-Chen
6354c9274b6bSCho, Yu-Chen /* io should be the last instruction in tb when icount is enabled */
6355c9274b6bSCho, Yu-Chen if (unlikely(icount && ret == DISAS_NEXT)) {
63568ec2edacSRichard Henderson ret = DISAS_TOO_MANY;
6357c9274b6bSCho, Yu-Chen }
6358c9274b6bSCho, Yu-Chen
6359c9274b6bSCho, Yu-Chen #ifndef CONFIG_USER_ONLY
636031b2d4a1SRichard Henderson if (s->base.tb->flags & FLAG_MASK_PER_IFETCH) {
6361a47d08eeSRichard Henderson switch (ret) {
6362a47d08eeSRichard Henderson case DISAS_TOO_MANY:
6363a47d08eeSRichard Henderson s->base.is_jmp = DISAS_PC_CC_UPDATED;
6364a47d08eeSRichard Henderson /* fall through */
6365a47d08eeSRichard Henderson case DISAS_NEXT:
6366a47d08eeSRichard Henderson tcg_gen_movi_i64(psw_addr, s->pc_tmp);
6367a47d08eeSRichard Henderson break;
6368a47d08eeSRichard Henderson default:
6369a47d08eeSRichard Henderson break;
6370a6a33760SRichard Henderson }
6371a6a33760SRichard Henderson update_cc_op(s);
6372a47d08eeSRichard Henderson gen_helper_per_check_exception(tcg_env);
6373c9274b6bSCho, Yu-Chen }
6374c9274b6bSCho, Yu-Chen #endif
6375c9274b6bSCho, Yu-Chen
6376c9274b6bSCho, Yu-Chen out:
6377c9274b6bSCho, Yu-Chen /* Advance to the next instruction. */
6378c9274b6bSCho, Yu-Chen s->base.pc_next = s->pc_tmp;
6379c9274b6bSCho, Yu-Chen return ret;
6380c9274b6bSCho, Yu-Chen }
6381c9274b6bSCho, Yu-Chen
s390x_tr_init_disas_context(DisasContextBase * dcbase,CPUState * cs)6382c9274b6bSCho, Yu-Chen static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
6383c9274b6bSCho, Yu-Chen {
6384c9274b6bSCho, Yu-Chen DisasContext *dc = container_of(dcbase, DisasContext, base);
6385c9274b6bSCho, Yu-Chen
6386c9274b6bSCho, Yu-Chen /* 31-bit mode */
6387c9274b6bSCho, Yu-Chen if (!(dc->base.tb->flags & FLAG_MASK_64)) {
6388c9274b6bSCho, Yu-Chen dc->base.pc_first &= 0x7fffffff;
6389c9274b6bSCho, Yu-Chen dc->base.pc_next = dc->base.pc_first;
6390c9274b6bSCho, Yu-Chen }
6391c9274b6bSCho, Yu-Chen
6392c9274b6bSCho, Yu-Chen dc->cc_op = CC_OP_DYNAMIC;
6393c9274b6bSCho, Yu-Chen dc->ex_value = dc->base.tb->cs_base;
639453313396SRichard Henderson dc->exit_to_mainloop = dc->ex_value;
6395c9274b6bSCho, Yu-Chen }
6396c9274b6bSCho, Yu-Chen
s390x_tr_tb_start(DisasContextBase * db,CPUState * cs)6397c9274b6bSCho, Yu-Chen static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
6398c9274b6bSCho, Yu-Chen {
6399c9274b6bSCho, Yu-Chen }
6400c9274b6bSCho, Yu-Chen
s390x_tr_insn_start(DisasContextBase * dcbase,CPUState * cs)6401c9274b6bSCho, Yu-Chen static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
6402c9274b6bSCho, Yu-Chen {
64035d23d530SRichard Henderson DisasContext *dc = container_of(dcbase, DisasContext, base);
64045d23d530SRichard Henderson
64055d23d530SRichard Henderson /* Delay the set of ilen until we've read the insn. */
64065d23d530SRichard Henderson tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);
6407c9274b6bSCho, Yu-Chen }
6408c9274b6bSCho, Yu-Chen
get_next_pc(CPUS390XState * env,DisasContext * s,uint64_t pc)6409ab12c95dSIlya Leoshkevich static target_ulong get_next_pc(CPUS390XState *env, DisasContext *s,
6410ab12c95dSIlya Leoshkevich uint64_t pc)
6411ab12c95dSIlya Leoshkevich {
6412763f2413SRichard Henderson uint64_t insn = translator_lduw(env, &s->base, pc);
6413ab12c95dSIlya Leoshkevich
6414ab12c95dSIlya Leoshkevich return pc + get_ilen((insn >> 8) & 0xff);
6415ab12c95dSIlya Leoshkevich }
6416ab12c95dSIlya Leoshkevich
s390x_tr_translate_insn(DisasContextBase * dcbase,CPUState * cs)6417c9274b6bSCho, Yu-Chen static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
6418c9274b6bSCho, Yu-Chen {
6419b77af26eSRichard Henderson CPUS390XState *env = cpu_env(cs);
6420c9274b6bSCho, Yu-Chen DisasContext *dc = container_of(dcbase, DisasContext, base);
6421c9274b6bSCho, Yu-Chen
6422c9274b6bSCho, Yu-Chen dc->base.is_jmp = translate_one(env, dc);
6423c9274b6bSCho, Yu-Chen if (dc->base.is_jmp == DISAS_NEXT) {
6424621aab6cSAlex Bennée if (dc->ex_value ||
6425621aab6cSAlex Bennée !is_same_page(dcbase, dc->base.pc_next) ||
6426621aab6cSAlex Bennée !is_same_page(dcbase, get_next_pc(env, dc, dc->base.pc_next))) {
6427c9274b6bSCho, Yu-Chen dc->base.is_jmp = DISAS_TOO_MANY;
6428c9274b6bSCho, Yu-Chen }
6429c9274b6bSCho, Yu-Chen }
6430c9274b6bSCho, Yu-Chen }
6431c9274b6bSCho, Yu-Chen
s390x_tr_tb_stop(DisasContextBase * dcbase,CPUState * cs)6432c9274b6bSCho, Yu-Chen static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
6433c9274b6bSCho, Yu-Chen {
6434c9274b6bSCho, Yu-Chen DisasContext *dc = container_of(dcbase, DisasContext, base);
6435c9274b6bSCho, Yu-Chen
6436c9274b6bSCho, Yu-Chen switch (dc->base.is_jmp) {
6437c9274b6bSCho, Yu-Chen case DISAS_NORETURN:
6438c9274b6bSCho, Yu-Chen break;
6439c9274b6bSCho, Yu-Chen case DISAS_TOO_MANY:
6440c9274b6bSCho, Yu-Chen update_psw_addr(dc);
6441c9274b6bSCho, Yu-Chen /* FALLTHRU */
6442c9274b6bSCho, Yu-Chen case DISAS_PC_UPDATED:
6443c9274b6bSCho, Yu-Chen /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
6444c9274b6bSCho, Yu-Chen cc op type is in env */
6445c9274b6bSCho, Yu-Chen update_cc_op(dc);
6446c9274b6bSCho, Yu-Chen /* FALLTHRU */
6447c9274b6bSCho, Yu-Chen case DISAS_PC_CC_UPDATED:
6448c9274b6bSCho, Yu-Chen /* Exit the TB, either by raising a debug exception or by return. */
6449872e1379SRichard Henderson if (dc->exit_to_mainloop) {
6450c9274b6bSCho, Yu-Chen tcg_gen_exit_tb(NULL, 0);
6451c9274b6bSCho, Yu-Chen } else {
6452c9274b6bSCho, Yu-Chen tcg_gen_lookup_and_goto_ptr();
6453c9274b6bSCho, Yu-Chen }
6454c9274b6bSCho, Yu-Chen break;
6455c9274b6bSCho, Yu-Chen default:
6456c9274b6bSCho, Yu-Chen g_assert_not_reached();
6457c9274b6bSCho, Yu-Chen }
6458c9274b6bSCho, Yu-Chen }
6459c9274b6bSCho, Yu-Chen
s390x_tr_disas_log(const DisasContextBase * dcbase,CPUState * cs,FILE * logfile)6460b67c567bSRichard Henderson static bool s390x_tr_disas_log(const DisasContextBase *dcbase,
64618eb806a7SRichard Henderson CPUState *cs, FILE *logfile)
6462c9274b6bSCho, Yu-Chen {
6463c9274b6bSCho, Yu-Chen DisasContext *dc = container_of(dcbase, DisasContext, base);
6464c9274b6bSCho, Yu-Chen
6465c9274b6bSCho, Yu-Chen if (unlikely(dc->ex_value)) {
646674e98b9bSRichard Henderson /* The ex_value has been recorded with translator_fake_ld. */
646774e98b9bSRichard Henderson fprintf(logfile, "IN: EXECUTE\n");
646874e98b9bSRichard Henderson target_disas(logfile, cs, &dc->base);
6469b67c567bSRichard Henderson return true;
6470c9274b6bSCho, Yu-Chen }
6471b67c567bSRichard Henderson return false;
6472c9274b6bSCho, Yu-Chen }
6473c9274b6bSCho, Yu-Chen
6474c9274b6bSCho, Yu-Chen static const TranslatorOps s390x_tr_ops = {
6475c9274b6bSCho, Yu-Chen .init_disas_context = s390x_tr_init_disas_context,
6476c9274b6bSCho, Yu-Chen .tb_start = s390x_tr_tb_start,
6477c9274b6bSCho, Yu-Chen .insn_start = s390x_tr_insn_start,
6478c9274b6bSCho, Yu-Chen .translate_insn = s390x_tr_translate_insn,
6479c9274b6bSCho, Yu-Chen .tb_stop = s390x_tr_tb_stop,
6480c9274b6bSCho, Yu-Chen .disas_log = s390x_tr_disas_log,
6481c9274b6bSCho, Yu-Chen };
6482c9274b6bSCho, Yu-Chen
gen_intermediate_code(CPUState * cs,TranslationBlock * tb,int * max_insns,vaddr pc,void * host_pc)6483597f9b2dSRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
648432f0c394SAnton Johansson vaddr pc, void *host_pc)
6485c9274b6bSCho, Yu-Chen {
6486c9274b6bSCho, Yu-Chen DisasContext dc;
6487c9274b6bSCho, Yu-Chen
6488306c8721SRichard Henderson translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base);
6489c9274b6bSCho, Yu-Chen }
6490c9274b6bSCho, Yu-Chen
s390x_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)64913479783bSRichard Henderson void s390x_restore_state_to_opc(CPUState *cs,
64923479783bSRichard Henderson const TranslationBlock *tb,
64933479783bSRichard Henderson const uint64_t *data)
6494c9274b6bSCho, Yu-Chen {
6495d0143fa9SPhilippe Mathieu-Daudé CPUS390XState *env = cpu_env(cs);
6496c9274b6bSCho, Yu-Chen int cc_op = data[1];
6497c9274b6bSCho, Yu-Chen
6498c9274b6bSCho, Yu-Chen env->psw.addr = data[0];
6499c9274b6bSCho, Yu-Chen
6500c9274b6bSCho, Yu-Chen /* Update the CC opcode if it is not already up-to-date. */
6501c9274b6bSCho, Yu-Chen if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) {
6502c9274b6bSCho, Yu-Chen env->cc_op = cc_op;
6503c9274b6bSCho, Yu-Chen }
6504c9274b6bSCho, Yu-Chen
6505c9274b6bSCho, Yu-Chen /* Record ILEN. */
6506c9274b6bSCho, Yu-Chen env->int_pgm_ilen = data[2];
6507c9274b6bSCho, Yu-Chen }
6508