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/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S82 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
83 ori t1, t1, 0x0800
84 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
86 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
88 and t1, t1, t2
89 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
101 andi t1, t5, 0x10
102 bnez t1, 2b
105 li t1, 0x02110E
106 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
[all …]
/openbmc/linux/arch/loongarch/mm/
H A Dtlbex.S48 csrwr t1, EXCEPTION_KS1
56 csrrd t1, LOONGARCH_CSR_PGDL
61 alsl.d t1, ra, t1, 3
63 ld.d t1, t1, 0
65 alsl.d t1, ra, t1, 3
68 ld.d t1, t1, 0
70 alsl.d t1, ra, t1, 3
72 ld.d ra, t1, 0
84 alsl.d t1, t0, ra, _PTE_T_LOG2
88 ll.d t0, t1, 0
[all …]
/openbmc/u-boot/board/imgtec/malta/
H A Dlowlevel_init.S38 li t1, MALTA_REVISION_CORID_CORE_LV
39 beq t0, t1, _gt64120
42 li t1, MALTA_REVISION_CORID_CORE_FPGA6
43 beq t0, t1, _msc01
65 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
67 sw t0, GT_ISD_OFS(t1)
70 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
74 sw t0, GT_PCI0IOLD_OFS(t1)
76 sw t0, GT_PCI0IOHD_OFS(t1)
80 sw t0, GT_PCI0M0LD_OFS(t1)
[all …]
/openbmc/linux/arch/loongarch/kernel/
H A Dlbt.S26 movscr2gr t1, $scr0 # save scr
27 stptr.d t1, a0, THREAD_SCR0
28 movscr2gr t1, $scr1
29 stptr.d t1, a0, THREAD_SCR1
30 movscr2gr t1, $scr2
31 stptr.d t1, a0, THREAD_SCR2
32 movscr2gr t1, $scr3
33 stptr.d t1, a0, THREAD_SCR3
35 x86mfflag t1, 0x3f # save eflags
36 stptr.d t1, a0, THREAD_EFLAGS
[all …]
/openbmc/linux/arch/arm/crypto/
H A Dsha512-armv4.pl74 $t1="r10";
99 mov $t1,$Ehi,lsr#14
103 eor $t1,$t1,$Elo,lsl#18
106 eor $t1,$t1,$Ehi,lsr#18
108 eor $t1,$t1,$Elo,lsl#14
110 eor $t1,$t1,$Elo,lsr#9
112 eor $t1,$t1,$Ehi,lsl#23 @ Sigma1(e)
115 adc $Thi,$Thi,$t1 @ T += Sigma1(e)
116 ldr $t1,[sp,#$Foff+4] @ f.hi
124 eor $t1,$t1,$t3
[all …]
H A Dsha256-armv4.pl52 $len="r2"; $t1="r2";
76 @ ldr $t1,[$inp],#4 @ $i
84 rev $t1,$t1
87 @ ldrb $t1,[$inp,#3] @ $i
91 orr $t1,$t1,$t2,lsl#8
93 orr $t1,$t1,$t0,lsl#16
98 orr $t1,$t1,$t2,lsl#24
104 add $h,$h,$t1 @ h+=X[i]
105 str $t1,[sp,#`$i%16`*4]
106 eor $t1,$f,$g
[all …]
/openbmc/linux/arch/mips/kernel/
H A Dcps-vec.S176 1: PTR_L t1, VPEBOOTCFG_PC(v1)
179 jr t1
239 PTR_LA t1, 1f
240 jr.hb t1
270 sll t1, ta1, VPECONF0_XTC_SHIFT
271 or t0, t0, t1
307 li t1, COREBOOTCFG_SIZE
308 mul t0, t0, t1
309 PTR_LA t1, mips_cps_core_bootcfg
310 PTR_L t1, 0(t1)
[all …]
H A Docteon_switch.S26 mfc0 t1, CP0_STATUS
27 LONG_S t1, THREAD_STATUS(a0)
41 li t1, -32768 /* Base address of CVMSEG */
46 LONG_L t8, 0(t1) /* Load from CVMSEG */
48 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
49 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
77 set_saved_sp t0, t1, t2
79 mfc0 t1, CP0_STATUS /* Do we really need this? */
81 and t1, a3
85 or a2, t1
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S102 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
104 or t1, t1, t2
105 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
107 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
109 and t1, t1, t2
110 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
115 li t1, 0x01
116 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
122 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
123 andi t1, t1, 0x02
[all …]
/openbmc/linux/arch/riscv/lib/
H A Dstrlen.S23 mv t1, a0
25 lbu t0, 0(t1)
27 addi t1, t1, 1
30 sub a0, t1, a0
72 REG_L t1, 0(t0)
79 SHIFT t1, t1, t2
82 orc.b t1, t1
85 not t1, t1
91 CZ t1, t1
97 srli a0, t1, 3
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dmxu_translate.c720 TCGv t0, t1; in gen_mxu_s8ldd() local
724 t1 = tcg_temp_new(); in gen_mxu_s8ldd()
740 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
742 tcg_gen_deposit_tl(t0, t0, t1, 0, 8); in gen_mxu_s8ldd()
746 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
748 tcg_gen_deposit_tl(t0, t0, t1, 8, 8); in gen_mxu_s8ldd()
752 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
754 tcg_gen_deposit_tl(t0, t0, t1, 16, 8); in gen_mxu_s8ldd()
758 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); in gen_mxu_s8ldd()
760 tcg_gen_deposit_tl(t0, t0, t1, 24, 8); in gen_mxu_s8ldd()
[all …]
H A Dloong_translate.c31 TCGv t0, t1; in gen_lext_DIV_G() local
40 t1 = tcg_temp_new(); in gen_lext_DIV_G()
46 gen_load_gpr(t1, rt); in gen_lext_DIV_G()
50 tcg_gen_ext32s_tl(t1, t1); in gen_lext_DIV_G()
52 tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1); in gen_lext_DIV_G()
58 tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); in gen_lext_DIV_G()
63 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); in gen_lext_DIV_G()
85 TCGv t0, t1; in gen_lext_DIVU_G() local
94 t1 = tcg_temp_new(); in gen_lext_DIVU_G()
99 gen_load_gpr(t1, rt); in gen_lext_DIVU_G()
[all …]
/openbmc/pldm/platform-mc/test/
H A Dterminus_test.cpp10 auto t1 = pldm::platform_mc::Terminus(1, 1 << PLDM_BASE); in TEST() local
14 EXPECT_EQ(true, t1.doesSupportType(PLDM_BASE)); in TEST()
15 EXPECT_EQ(false, t1.doesSupportType(PLDM_PLATFORM)); in TEST()
23 auto t1 = pldm::platform_mc::Terminus(tid, 1 << PLDM_BASE); in TEST() local
25 EXPECT_EQ(tid, t1.getTid()); in TEST()
30 auto t1 = in TEST() local
90 t1.pdrs.emplace_back(pdr1); in TEST()
91 t1.pdrs.emplace_back(pdr2); in TEST()
92 t1.parseTerminusPDRs(); in TEST()
94 auto sensorAuxNames = t1.getSensorAuxiliaryNames(0); in TEST()
[all …]
/openbmc/linux/arch/powerpc/crypto/
H A Dghashp10-ppc.pl57 my ($zero,$t0,$t1,$t2,$xC2,$H,$Hh,$Hl,$lemask)=map("v$_",(4..12));
88 vsldoi $t1,$zero,$t0,1 # ...1
91 vor $xC2,$xC2,$t1 # 0xc2....01
92 vspltb $t1,$H,0 # most significant byte
94 vsrab $t1,$t1,$t2 # broadcast carry bit
95 vand $t1,$t1,$xC2
96 vxor $H,$H,$t1 # twisted H
130 vsldoi $t1,$zero,$t0,1 # ...1
133 vor $xC2,$xC2,$t1 # 0xc2....01
134 vspltb $t1,$H,0 # most significant byte
[all …]
/openbmc/linux/include/crypto/
H A Daria.h343 static inline void aria_sbox_layer1_with_pre_diff(u32 *t0, u32 *t1, u32 *t2, in aria_sbox_layer1_with_pre_diff() argument
350 *t1 = s1[get_u8(*t1, 0)] ^ in aria_sbox_layer1_with_pre_diff()
351 s2[get_u8(*t1, 1)] ^ in aria_sbox_layer1_with_pre_diff()
352 x1[get_u8(*t1, 2)] ^ in aria_sbox_layer1_with_pre_diff()
353 x2[get_u8(*t1, 3)]; in aria_sbox_layer1_with_pre_diff()
365 static inline void aria_sbox_layer2_with_pre_diff(u32 *t0, u32 *t1, u32 *t2, in aria_sbox_layer2_with_pre_diff() argument
372 *t1 = x1[get_u8(*t1, 0)] ^ in aria_sbox_layer2_with_pre_diff()
373 x2[get_u8(*t1, 1)] ^ in aria_sbox_layer2_with_pre_diff()
374 s1[get_u8(*t1, 2)] ^ in aria_sbox_layer2_with_pre_diff()
375 s2[get_u8(*t1, 3)]; in aria_sbox_layer2_with_pre_diff()
[all …]
/openbmc/linux/arch/csky/abiv2/
H A Dstrcmp.S13 andi t1, a0, 0x3
14 bnez t1, 5f
19 ldw t1, (a1, 0)
21 cmpne t0, t1
29 ldw t1, (a1, 4)
30 cmpne t0, t1
36 ldw t1, (a1, 8)
37 cmpne t0, t1
43 ldw t1, (a1, 12)
44 cmpne t0, t1
[all …]
/openbmc/u-boot/arch/riscv/cpu/
H A Dstart.S57 li t1, CONFIG_SYS_INIT_SP_ADDR
58 and sp, t1, t0 /* force 16 byte alignment */
103 mv t1, s4 /* t1 <- scratch for copy_loop */
111 SREG t5, 0(t1)
112 addi t1, t1, REGBYTES
119 la t1, __rel_dyn_start
121 beq t1, t2, clear_bss
122 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
128 bne t1, t2, 7f
131 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
[all …]
/openbmc/linux/arch/alpha/lib/
H A Dstxcpy.S49 mskqh t1, a1, t3 # e0 :
50 ornot t1, t2, t2 # .. e1 :
53 or t0, t3, t1 # e0 :
61 stq_u t1, 0(a0) # e0 :
63 ldq_u t1, 0(a1) # e0 :
65 cmpbge zero, t1, t8 # e0 (stall)
85 zapnot t1, t6, t1 # e0 : clear src bytes >= null
88 or t0, t1, t1 # e1 :
90 1: stq_u t1, 0(a0) # e0 :
109 ldq_u t1, 0(a1) # e0 : load first src word
[all …]
H A Dev6-stxcpy.S60 mskqh t1, a1, t3 # U :
61 ornot t1, t2, t2 # E : (stall)
65 or t0, t3, t1 # E : (stall)
74 stq_u t1, 0(a0) # L :
79 ldq_u t1, 0(a1) # L : Latency=3
81 cmpbge zero, t1, t8 # E : (3 cycle stall)
100 zapnot t1, t6, t1 # U : clear src bytes >= null (stall)
104 or t0, t1, t1 # E : (stall)
108 1: stq_u t1, 0(a0) # L :
129 ldq_u t1, 0(a1) # L : load first src word
[all …]
/openbmc/sdbusplus/test/vtable/
H A Dvtable.cpp34 constexpr bool operator==(const sd_bus_vtable& t1, const sd_bus_vtable& t2) in operator ==() argument
36 if (t1.type != t2.type || t1.flags != t2.flags) in operator ==()
41 switch (t1.type) in operator ==()
44 return t1.x.start.element_size == t2.x.start.element_size && in operator ==()
45 t1.x.start.features == t2.x.start.features; in operator ==()
54 constexpr uint8_t allZeors[sizeof(t1.x)] = {0}; in operator ==()
55 return memcmp(&t1.x, allZeors, sizeof(t1.x)) == 0 && in operator ==()
59 return strcmp(t1.x.method.member, t2.x.method.member) == 0 && in operator ==()
60 strcmp(t1.x.method.signature, t2.x.method.signature) == 0 && in operator ==()
61 strcmp(t1.x.method.result, t2.x.method.result) == 0 && in operator ==()
[all …]
/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dlowlevel_init.S71 li t1, DELAY_USEC(1000000)
77 subu t1, t1, 1
78 bgtz t1, 1b
88 lw t1, 0(t0)
90 and t1, t1, t2
91 ori t1, t1, 0xc
92 sw t1, 0(t0)
121 li t1, 0x1
123 sub t0, t0, t1
209 lw t1, 0x10(s0)
[all …]
/openbmc/u-boot/arch/mips/lib/
H A Dcache_init.S147 lw t1, GCR_L2_CONFIG(t0)
148 bgez t1, l2_probe_done
150 ext R_L2_LINE, t1, \
156 ext t2, t1, GCR_L2_CONFIG_ASSOC_SHIFT, GCR_L2_CONFIG_ASSOC_BITS
160 ext t2, t1, GCR_L2_CONFIG_SETSZ_SHIFT, GCR_L2_CONFIG_SETSZ_BITS
166 or t1, t1, GCR_L2_CONFIG_BYPASS
167 sw t1, GCR_L2_CONFIG(t0)
195 li t1, 2
196 sllv R_L2_LINE, t1, R_L2_LINE
198 srl t1, t0, MIPS_CONF2_SA_SHF
[all …]
/openbmc/linux/lib/crypto/mpi/
H A Dmpi-inv.c33 MPI u, v, u1, u2 = NULL, u3, v1, v2 = NULL, v3, t1, t2 = NULL, t3; in mpi_invm() local
63 t1 = mpi_alloc_set_ui(0); in mpi_invm()
72 t1 = mpi_alloc_set_ui(1); in mpi_invm()
81 if (mpi_test_bit(t1, 0) || mpi_test_bit(t2, 0)) { in mpi_invm()
83 mpi_add(t1, t1, v); in mpi_invm()
86 mpi_rshift(t1, t1, 1); in mpi_invm()
90 if (mpi_test_bit(t1, 0)) in mpi_invm()
91 mpi_add(t1, t1, v); in mpi_invm()
92 mpi_rshift(t1, t1, 1); in mpi_invm()
100 mpi_set(u1, t1); in mpi_invm()
[all …]
/openbmc/linux/drivers/crypto/vmx/
H A Dghashp8-ppc.pl57 my ($zero,$t0,$t1,$t2,$xC2,$H,$Hh,$Hl,$lemask)=map("v$_",(4..12));
86 vsldoi $t1,$zero,$t0,1 # ...1
89 vor $xC2,$xC2,$t1 # 0xc2....01
90 vspltb $t1,$H,0 # most significant byte
92 vsrab $t1,$t1,$t2 # broadcast carry bit
93 vand $t1,$t1,$xC2
94 vxor $H,$H,$t1 # twisted H
139 vsldoi $t1,$zero,$Xm,8
141 vxor $Xh,$Xh,$t1
146 vsldoi $t1,$Xl,$Xl,8 # 2nd phase
[all …]
/openbmc/linux/drivers/soc/bcm/brcmstb/pm/
H A Ds2-mips.S52 addiu t1, s3, -1
53 not t1
56 and t0, t1
59 and t2, t1
68 2: move t1, s4
69 cache 0x1c, 0(t1)
70 addu t1, s3
89 li t1, ~(ST0_IM | ST0_IE)
90 and t0, t1
121 lw t1, TIMER_TIMER1_STAT(s2)
[all …]

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