Lines Matching refs:t1
82 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
83 ori t1, t1, 0x0800
84 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
86 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
88 and t1, t1, t2
89 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
101 andi t1, t5, 0x10
102 bnez t1, 2b
105 li t1, 0x02110E
106 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
111 li t1, 0x03
112 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
117 li t1, 0x00
118 sw t1, AR933X_RTC_REG_RESET(t0)
122 li t1, 0x01
123 sw t1, AR933X_RTC_REG_RESET(t0)
129 lw t1, AR933X_RTC_REG_STATUS(t0)
130 andi t1, t1, 0x02
131 beqz t1, 1b
136 andi t1, t5, 0x01 # t5 BOOT_STRAP
137 bnez t1, 1f
139 li t1, 0x19e82f01
143 li t1, 0x18e82f01
145 sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
148 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
150 and t1, t1, t2
152 or t1, t1, t2
153 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
158 li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
159 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
163 andi t1, t5, 0x01 # t5 BOOT_STRAP
164 bnez t1, 1f
166 li t1, 0x0352
170 li t1, 0x0550
172 sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
177 andi t1, t5, 0x01 # t5 BOOT_STRAP
178 bnez t1, 1f
180 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
184 li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
186 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
189 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
191 and t1, t1, t2
192 bnez t1, 1b
196 li t1, 0x1003E8
197 sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
201 andi t1, t5, 0x01 # t5 BOOT_STRAP
202 bnez t1, 1f
204 li t1, PLL_CPU_CONFIG_VAL_25M
208 li t1, PLL_CPU_CONFIG_VAL_40M
210 sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
215 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
217 and t1, t1, t2
218 bnez t1, 1b
234 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
236 and t1, t1, t2
237 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
248 or t1, t1, t2
249 sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
254 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
255 andi t1, t1, 0x8
256 beqz t1, 1b
259 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
261 and t1, t1, t2
262 srl t1, t1, 3
264 bgt t1, t2, 2b
272 li t1, PLL_CLK_CONTROL_VAL
273 sw t1, AR933X_PLL_CLK_CTRL_REG(t0)