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Searched refs:smu_dpm_clks (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c513 smu_dpm_clks->mc_address.high_part); in dcn31_get_dpm_table_from_smu()
515 smu_dpm_clks->mc_address.low_part); in dcn31_get_dpm_table_from_smu()
709 &smu_dpm_clks.mc_address.quad_part); in dcn31_clk_mgr_construct()
711 if (smu_dpm_clks.dpm_clks == NULL) { in dcn31_clk_mgr_construct()
712 smu_dpm_clks.dpm_clks = &dummy_clocks; in dcn31_clk_mgr_construct()
713 smu_dpm_clks.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
716 ASSERT(smu_dpm_clks.dpm_clks); in dcn31_clk_mgr_construct()
760 smu_dpm_clks.dpm_clks->MinGfxClk, in dcn31_clk_mgr_construct()
791 smu_dpm_clks.dpm_clks); in dcn31_clk_mgr_construct()
795 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn31_clk_mgr_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c473 smu_dpm_clks->mc_address.high_part); in dcn315_get_dpm_table_from_smu()
475 smu_dpm_clks->mc_address.low_part); in dcn315_get_dpm_table_from_smu()
640 &smu_dpm_clks.mc_address.quad_part); in dcn315_clk_mgr_construct()
642 if (smu_dpm_clks.dpm_clks == NULL) { in dcn315_clk_mgr_construct()
643 smu_dpm_clks.dpm_clks = &dummy_clocks; in dcn315_clk_mgr_construct()
644 smu_dpm_clks.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
647 ASSERT(smu_dpm_clks.dpm_clks); in dcn315_clk_mgr_construct()
687 smu_dpm_clks.dpm_clks->MinGfxClk, in dcn315_clk_mgr_construct()
719 smu_dpm_clks.dpm_clks); in dcn315_clk_mgr_construct()
723 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn315_clk_mgr_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c528 smu_dpm_clks->mc_address.high_part); in dcn314_get_dpm_table_from_smu()
530 smu_dpm_clks->mc_address.low_part); in dcn314_get_dpm_table_from_smu()
753 &smu_dpm_clks.mc_address.quad_part); in dcn314_clk_mgr_construct()
755 if (smu_dpm_clks.dpm_clks == NULL) { in dcn314_clk_mgr_construct()
756 smu_dpm_clks.dpm_clks = &dummy_clocks; in dcn314_clk_mgr_construct()
757 smu_dpm_clks.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()
760 ASSERT(smu_dpm_clks.dpm_clks); in dcn314_clk_mgr_construct()
802 smu_dpm_clks.dpm_clks->MinGfxClk, in dcn314_clk_mgr_construct()
834 smu_dpm_clks.dpm_clks); in dcn314_clk_mgr_construct()
838 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn314_clk_mgr_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c639 struct smu_dpm_clks *smu_dpm_clks) in vg_get_dpm_table_from_smu() argument
652 smu_dpm_clks->mc_address.high_part); in vg_get_dpm_table_from_smu()
654 smu_dpm_clks->mc_address.low_part); in vg_get_dpm_table_from_smu()
664 struct smu_dpm_clks smu_dpm_clks = { 0 }; in vg_clk_mgr_construct() local
696 &smu_dpm_clks.mc_address.quad_part); in vg_clk_mgr_construct()
698 if (smu_dpm_clks.dpm_clks == NULL) { in vg_clk_mgr_construct()
699 smu_dpm_clks.dpm_clks = &dummy_clocks; in vg_clk_mgr_construct()
703 ASSERT(smu_dpm_clks.dpm_clks); in vg_clk_mgr_construct()
735 smu_dpm_clks.dpm_clks); in vg_clk_mgr_construct()
738 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in vg_clk_mgr_construct()
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H A Ddcn301_smu.h124 struct smu_dpm_clks { struct
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c422 struct dcn316_smu_dpm_clks *smu_dpm_clks) in dcn316_get_dpm_table_from_smu() argument
435 smu_dpm_clks->mc_address.high_part); in dcn316_get_dpm_table_from_smu()
437 smu_dpm_clks->mc_address.low_part); in dcn316_get_dpm_table_from_smu()
610 &smu_dpm_clks.mc_address.quad_part); in dcn316_clk_mgr_construct()
612 if (smu_dpm_clks.dpm_clks == NULL) { in dcn316_clk_mgr_construct()
613 smu_dpm_clks.dpm_clks = &dummy_clocks; in dcn316_clk_mgr_construct()
614 smu_dpm_clks.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
617 ASSERT(smu_dpm_clks.dpm_clks); in dcn316_clk_mgr_construct()
658 smu_dpm_clks.dpm_clks); in dcn316_clk_mgr_construct()
662 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) in dcn316_clk_mgr_construct()
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