460 		struct dcn315_smu_dpm_clks *smu_dpm_clks)  in dcn315_get_dpm_table_from_smu()  argument
462 	DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;  in dcn315_get_dpm_table_from_smu()
467 	if (!table || smu_dpm_clks->mc_address.quad_part == 0)  in dcn315_get_dpm_table_from_smu()
473 			smu_dpm_clks->mc_address.high_part);  in dcn315_get_dpm_table_from_smu()
475 			smu_dpm_clks->mc_address.low_part);  in dcn315_get_dpm_table_from_smu()
608 	struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };  in dcn315_clk_mgr_construct()  local
636 	smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(  in dcn315_clk_mgr_construct()
640 				&smu_dpm_clks.mc_address.quad_part);  in dcn315_clk_mgr_construct()
642 	if (smu_dpm_clks.dpm_clks == NULL) {  in dcn315_clk_mgr_construct()
643 		smu_dpm_clks.dpm_clks = &dummy_clocks;  in dcn315_clk_mgr_construct()
644 		smu_dpm_clks.mc_address.quad_part = 0;  in dcn315_clk_mgr_construct()
647 	ASSERT(smu_dpm_clks.dpm_clks);  in dcn315_clk_mgr_construct()
674 		dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);  in dcn315_clk_mgr_construct()
682 				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,  in dcn315_clk_mgr_construct()
683 				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,  in dcn315_clk_mgr_construct()
684 				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,  in dcn315_clk_mgr_construct()
685 				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,  in dcn315_clk_mgr_construct()
686 				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,  in dcn315_clk_mgr_construct()
687 				   smu_dpm_clks.dpm_clks->MinGfxClk,  in dcn315_clk_mgr_construct()
688 				   smu_dpm_clks.dpm_clks->MaxGfxClk);  in dcn315_clk_mgr_construct()
689 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {  in dcn315_clk_mgr_construct()
692 					   smu_dpm_clks.dpm_clks->DcfClocks[i]);  in dcn315_clk_mgr_construct()
694 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {  in dcn315_clk_mgr_construct()
696 					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);  in dcn315_clk_mgr_construct()
698 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {  in dcn315_clk_mgr_construct()
700 					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);  in dcn315_clk_mgr_construct()
704 					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);  in dcn315_clk_mgr_construct()
710 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,  in dcn315_clk_mgr_construct()
711 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,  in dcn315_clk_mgr_construct()
712 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);  in dcn315_clk_mgr_construct()
719 					smu_dpm_clks.dpm_clks);  in dcn315_clk_mgr_construct()
723 	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)  in dcn315_clk_mgr_construct()
725 				smu_dpm_clks.dpm_clks);  in dcn315_clk_mgr_construct()