515 		struct dcn314_smu_dpm_clks *smu_dpm_clks)  in dcn314_get_dpm_table_from_smu()  argument
517 	DpmClocks314_t *table = smu_dpm_clks->dpm_clks;  in dcn314_get_dpm_table_from_smu()
522 	if (!table || smu_dpm_clks->mc_address.quad_part == 0)  in dcn314_get_dpm_table_from_smu()
528 			smu_dpm_clks->mc_address.high_part);  in dcn314_get_dpm_table_from_smu()
530 			smu_dpm_clks->mc_address.low_part);  in dcn314_get_dpm_table_from_smu()
721 	struct dcn314_smu_dpm_clks smu_dpm_clks = { 0 };  in dcn314_clk_mgr_construct()  local
749 	smu_dpm_clks.dpm_clks = (DpmClocks314_t *)dm_helpers_allocate_gpu_mem(  in dcn314_clk_mgr_construct()
753 				&smu_dpm_clks.mc_address.quad_part);  in dcn314_clk_mgr_construct()
755 	if (smu_dpm_clks.dpm_clks == NULL) {  in dcn314_clk_mgr_construct()
756 		smu_dpm_clks.dpm_clks = &dummy_clocks;  in dcn314_clk_mgr_construct()
757 		smu_dpm_clks.mc_address.quad_part = 0;  in dcn314_clk_mgr_construct()
760 	ASSERT(smu_dpm_clks.dpm_clks);  in dcn314_clk_mgr_construct()
789 		dcn314_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);  in dcn314_clk_mgr_construct()
797 				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,  in dcn314_clk_mgr_construct()
798 				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,  in dcn314_clk_mgr_construct()
799 				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,  in dcn314_clk_mgr_construct()
800 				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,  in dcn314_clk_mgr_construct()
801 				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,  in dcn314_clk_mgr_construct()
802 				   smu_dpm_clks.dpm_clks->MinGfxClk,  in dcn314_clk_mgr_construct()
803 				   smu_dpm_clks.dpm_clks->MaxGfxClk);  in dcn314_clk_mgr_construct()
804 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {  in dcn314_clk_mgr_construct()
807 					   smu_dpm_clks.dpm_clks->DcfClocks[i]);  in dcn314_clk_mgr_construct()
809 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {  in dcn314_clk_mgr_construct()
811 					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);  in dcn314_clk_mgr_construct()
813 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {  in dcn314_clk_mgr_construct()
815 					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);  in dcn314_clk_mgr_construct()
819 					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);  in dcn314_clk_mgr_construct()
825 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,  in dcn314_clk_mgr_construct()
826 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,  in dcn314_clk_mgr_construct()
827 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);  in dcn314_clk_mgr_construct()
834 					smu_dpm_clks.dpm_clks);  in dcn314_clk_mgr_construct()
838 	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)  in dcn314_clk_mgr_construct()
840 				smu_dpm_clks.dpm_clks);  in dcn314_clk_mgr_construct()