500 		struct dcn31_smu_dpm_clks *smu_dpm_clks)  in dcn31_get_dpm_table_from_smu()  argument
502 	DpmClocks_t *table = smu_dpm_clks->dpm_clks;  in dcn31_get_dpm_table_from_smu()
507 	if (!table || smu_dpm_clks->mc_address.quad_part == 0)  in dcn31_get_dpm_table_from_smu()
513 			smu_dpm_clks->mc_address.high_part);  in dcn31_get_dpm_table_from_smu()
515 			smu_dpm_clks->mc_address.low_part);  in dcn31_get_dpm_table_from_smu()
677 	struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };  in dcn31_clk_mgr_construct()  local
705 	smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(  in dcn31_clk_mgr_construct()
709 				&smu_dpm_clks.mc_address.quad_part);  in dcn31_clk_mgr_construct()
711 	if (smu_dpm_clks.dpm_clks == NULL) {  in dcn31_clk_mgr_construct()
712 		smu_dpm_clks.dpm_clks = &dummy_clocks;  in dcn31_clk_mgr_construct()
713 		smu_dpm_clks.mc_address.quad_part = 0;  in dcn31_clk_mgr_construct()
716 	ASSERT(smu_dpm_clks.dpm_clks);  in dcn31_clk_mgr_construct()
746 		dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);  in dcn31_clk_mgr_construct()
755 				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,  in dcn31_clk_mgr_construct()
756 				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,  in dcn31_clk_mgr_construct()
757 				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,  in dcn31_clk_mgr_construct()
758 				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,  in dcn31_clk_mgr_construct()
759 				   smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,  in dcn31_clk_mgr_construct()
760 				   smu_dpm_clks.dpm_clks->MinGfxClk,  in dcn31_clk_mgr_construct()
761 				   smu_dpm_clks.dpm_clks->MaxGfxClk);  in dcn31_clk_mgr_construct()
762 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {  in dcn31_clk_mgr_construct()
765 					   smu_dpm_clks.dpm_clks->DcfClocks[i]);  in dcn31_clk_mgr_construct()
767 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {  in dcn31_clk_mgr_construct()
769 					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);  in dcn31_clk_mgr_construct()
771 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {  in dcn31_clk_mgr_construct()
773 					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);  in dcn31_clk_mgr_construct()
777 					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);  in dcn31_clk_mgr_construct()
783 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,  in dcn31_clk_mgr_construct()
784 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,  in dcn31_clk_mgr_construct()
785 					   i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);  in dcn31_clk_mgr_construct()
791 					smu_dpm_clks.dpm_clks);  in dcn31_clk_mgr_construct()
795 	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)  in dcn31_clk_mgr_construct()
797 				smu_dpm_clks.dpm_clks);  in dcn31_clk_mgr_construct()