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Searched refs:sdelay (Results 1 – 25 of 36) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c95 sdelay(0x100000); in dmc_init()
140 sdelay(0x100000); in dmc_init()
144 sdelay(0x100000); in dmc_init()
148 sdelay(0x100000); in dmc_init()
151 sdelay(0x100000); in dmc_init()
155 sdelay(0x100000); in dmc_init()
159 sdelay(0x100000); in dmc_init()
162 sdelay(0x100000); in dmc_init()
H A Ddmc_common.c56 sdelay(100); in dmc_config_zq()
65 sdelay(100); in dmc_config_zq()
116 sdelay(0x10000); in dmc_config_mrs()
122 sdelay(0x10000); in dmc_config_mrs()
130 sdelay(10000); in dmc_config_mrs()
149 sdelay(0x10000); in dmc_config_prech()
H A Dclock_init_exynos4.c46 sdelay(0x10000); in system_clock_init()
60 sdelay(0x10000); in system_clock_init()
93 sdelay(0x30000); in system_clock_init()
H A Dcommon_setup.h47 void sdelay(unsigned long);
H A Ddmc_init_ddr3.c191 sdelay(100); in ddr3_mem_ctrl_init()
646 sdelay(10); in ddr3_mem_ctrl_init()
656 sdelay(10); in ddr3_mem_ctrl_init()
752 sdelay(100); in ddr3_mem_ctrl_init()
767 sdelay(100); in ddr3_mem_ctrl_init()
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dclock.c45 sdelay(450); in wait_for_completion()
57 sdelay(340); in bypass_main_pll()
98 sdelay(210000); in configure_main_pll()
113 sdelay(21000); in configure_main_pll()
152 sdelay(21000); /* Wait for a minimum of 7 us*/ in configure_main_pll()
154 sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ in configure_main_pll()
185 sdelay(21000); in configure_secondary_pll()
193 sdelay(105000); in configure_secondary_pll()
215 sdelay(210000); in init_pll()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun9i.c105 sdelay(2000); in clock_set_pll1()
126 sdelay(2000); in clock_set_pll2()
144 sdelay(2000); in clock_set_pll6()
158 sdelay(2000); in clock_set_pll12()
170 sdelay(2000); in clock_set_pll4()
H A Dclock_sun4i.c31 sdelay(200); in clock_init_safe()
159 sdelay(20); in clock_set_pll1()
170 sdelay(200); in clock_set_pll1()
178 sdelay(20); in clock_set_pll1()
H A Ddram_sun9i.c277 sdelay(2000); in mctl_sys_init()
287 sdelay(1000); in mctl_sys_init()
295 sdelay(10000); in mctl_sys_init()
303 sdelay(2000); in mctl_sys_init()
331 sdelay(1000); in mctl_sys_init()
754 sdelay(10000); /* XXX necessary? */ in mctl_channel_init()
760 sdelay(1000); in mctl_channel_init()
803 sdelay(100000); in mctl_channel_init()
H A Dclock_sun8i_a83t.c32 sdelay(50); in clock_init_safe()
34 sdelay(100); in clock_init_safe()
H A Dp2wi.c38 sdelay(0x100); in p2wi_init()
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dspl_id_nand.c35 sdelay(2000); in identify_nand_chip()
42 sdelay(100); in identify_nand_chip()
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dmem-common.c67 sdelay(1000); in enable_gpmc_cs_config()
78 sdelay(2000); in enable_gpmc_cs_config()
148 sdelay(1000); in set_gpmc_cs0()
H A Dvc.c124 sdelay(100); in omap_vc_bypass_send_value()
/openbmc/u-boot/drivers/adc/
H A Dadc-uclass.c23 #define sdelay(x) udelay(x) macro
25 extern void sdelay(unsigned long loops);
161 sdelay(5); in adc_channel_data()
188 sdelay(5); in adc_channels_data()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dsys_proto.h13 void sdelay(unsigned long);
/openbmc/u-boot/arch/arm/mach-k3/include/mach/
H A Dsys_proto.h10 void sdelay(unsigned long loops);
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero.c137 sdelay(1000); in enable_gpmc_net_config()
155 sdelay(2000); in enable_gpmc_net_config()
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dsyslib.c20 void sdelay(unsigned long loops) in sdelay() function
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcpu.c27 void sdelay(unsigned long loops) in sdelay() function
/openbmc/u-boot/arch/arm/include/asm/arch-am33xx/
H A Dsys_proto.h26 void sdelay(unsigned long);
/openbmc/u-boot/arch/arm/include/asm/arch-omap4/
H A Dsys_proto.h48 void sdelay(unsigned long);
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dsys_proto.h68 void sdelay(unsigned long);
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Dsys_proto.h53 void sdelay(unsigned long);
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.c183 sdelay(10); /* Delay at least 20 clock cycles */ \
189 sdelay(10); /* Delay at least 20 clock cycles */ \
299 sdelay(5); /* Delay at least 10 clock cycles */ in __phy_builtin_init_routine()
305 sdelay(16); /* Delay at least 32 clock cycles */ in __phy_builtin_init_routine()

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