| /openbmc/u-boot/drivers/clk/ |
| H A D | clk-hsdk-cgu.c | 369 static ulong pll_get(struct clk *sclk) in pll_get() argument
374 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in pll_get()
401 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate) in hsdk_pll_round_rate() argument
405 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in hsdk_pll_round_rate()
477 static ulong pll_set(struct clk *sclk, ulong rate) in pll_set() argument
481 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in pll_set()
484 best_rate = hsdk_pll_round_rate(sclk, rate); in pll_set()
498 static int idiv_off(struct clk *sclk) in idiv_off() argument
500 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in idiv_off()
507 static ulong idiv_get(struct clk *sclk) in idiv_get() argument
[all …]
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 367 unsigned long sclk = 0; in exynos5_get_periph_rate() local
437 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
440 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()
443 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
460 return (sclk / (div + 1)) / (sub_div + 1); in exynos5_get_periph_rate()
466 unsigned long sclk = 0; in exynos542x_get_periph_rate() local
528 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()
531 sclk = exynos542x_get_pll_clk(SPLL); in exynos542x_get_periph_rate()
534 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()
537 sclk = exynos542x_get_pll_clk(RPLL); in exynos542x_get_periph_rate()
[all …]
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| /openbmc/u-boot/board/freescale/common/ |
| H A D | ngpixis.c | 142 PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); in pixis_dump_regs()
169 PIXIS_WRITE(sclk[0], sclk0); in pixis_sysclk_set()
170 PIXIS_WRITE(sclk[1], sclk1); in pixis_sysclk_set()
171 PIXIS_WRITE(sclk[2], sclk2); in pixis_sysclk_set()
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| H A D | ics307_clk.c | 134 in_8(&fpga_reg->sclk[0]), in get_board_sys_clk()
135 in_8(&fpga_reg->sclk[1]), in get_board_sys_clk()
136 in_8(&fpga_reg->sclk[2])); in get_board_sys_clk()
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| H A D | pixis.h | 33 u8 sclk[3]; member
96 u8 sclk[3]; member
128 u8 sclk[3]; member
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| H A D | qixis.c | 184 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), in qixis_dump_regs()
185 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); in qixis_dump_regs()
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| H A D | ngpixis.h | 38 u8 sclk[3]; member
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| H A D | qixis.h | 46 u8 sclk[3]; /* Clock Configuration Registers,0x34 */ member
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | exynos_dw_mmc.c | 60 unsigned long sclk; in exynos_dwmci_get_clk() local
71 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_get_clk()
77 return sclk / clk_div / (host->div + 1); in exynos_dwmci_get_clk()
102 unsigned long freq, sclk; in exynos_dwmci_core_init() local
110 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_core_init()
111 div = DIV_ROUND_UP(sclk, freq); in exynos_dwmci_core_init()
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| H A D | mtk-sd.c | 254 u32 sclk; /* actual calculated bus clock */ member
669 if (host->sclk == 0) { in msdc_set_timeout()
672 clk_ns = 1000000000UL / host->sclk; in msdc_set_timeout()
718 u32 sclk; in msdc_set_mclk() local
742 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
746 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
758 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
764 sclk = host->src_clk_freq; in msdc_set_mclk()
769 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
773 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
[all …]
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| H A D | ftsdc010_mci.h | 17 uint32_t sclk; /* FTSDC010 source clock in Hz */ member
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| H A D | dw_mmc.c | 375 unsigned long sclk; local
385 sclk = host->get_mmc_clk(host, freq);
387 sclk = host->bus_hz;
393 if (sclk == freq)
396 div = DIV_ROUND_UP(sclk, 2 * freq);
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| H A D | ftsdc010_mci.c | 140 if (rate >= chip->sclk / (2 * (div + 1))) in ftsdc010_clkset()
143 chip->rate = chip->sclk / (2 * (div + 1)); in ftsdc010_clkset()
418 chip->sclk = priv->minmax[1]; in ftsdc010_mmc_ofdata_to_platdata()
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| /openbmc/u-boot/drivers/spi/ |
| H A D | soft_spi.c | 24 struct gpio_desc sclk; member
43 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
64 dm_gpio_set_value(&plat->sclk, 0); in soft_spi_cs_activate()
223 gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, in soft_spi_probe()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | meson-axg.dtsi | 30 clock-names = "mclk", "sclk", "lrclk";
41 clock-names = "mclk", "sclk", "lrclk";
52 clock-names = "mclk", "sclk", "lrclk";
1103 clock-names = "pclk", "sclk", "sclk_sel",
1117 clock-names = "pclk", "sclk", "sclk_sel",
1131 clock-names = "pclk", "sclk", "sclk_sel",
1145 clock-names = "pclk", "sclk", "sclk_sel",
1170 clock-names = "pclk", "sclk", "sclk_sel",
1184 clock-names = "pclk", "sclk", "sclk_sel",
1198 clock-names = "pclk", "sclk", "sclk_sel",
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| H A D | stih407-pinctrl.dtsi | 1138 sclk = <&pio33 6 ALT1 OUT>;
1150 sclk = <&pio33 6 ALT1 OUT>;
1161 sclk = <&pio32 6 ALT1 IN>;
1174 sclk = <&pio32 6 ALT1 IN>;
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| H A D | rk3328.dtsi | 856 i2s1_sclk: i2s1-sclk {
916 i2s2m0_sclk: i2s2m0-sclk {
958 i2s2m1_sclk: i2s2m1-sclk {
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| /openbmc/u-boot/doc/device-tree-bindings/clock/ |
| H A D | nvidia,tegra20-car.txt | 138 107 sclk
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| /openbmc/u-boot/doc/device-tree-bindings/video/ |
| H A D | exynos-fb.txt | 56 samsung,sclk-div: parent_clock/source_clock ratio
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