/openbmc/linux/arch/x86/pci/ |
H A D | ce4100.c | 66 static void reg_write(struct sim_dev_reg *reg, u32 value) in reg_write() function 105 DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write) 113 DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write) 118 DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write) 120 DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write) 121 DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write) 139 DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write) 140 DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write) 141 DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write) 142 DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write) [all …]
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/openbmc/u-boot/board/micronas/vct/ |
H A D | ebi_onenand.c | 25 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16)); in ebi_nand_write_word() 26 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_nand_write_word() 36 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_onenand() 38 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand() 39 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_onenand() 41 reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002); in ebi_init_onenand() 53 reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000); in ebi_init_onenand() 66 reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1); in ebi_init_onenand() 67 reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2); in ebi_init_onenand() 68 reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3); in ebi_init_onenand() [all …]
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H A D | ebi_smc911x.c | 16 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x00003020); in ebi_init_smc911x() 17 reg_write(EBI_DEV1_CONFIG2(EBI_BASE), 0x0000004F); in ebi_init_smc911x() 19 reg_write(EBI_DEV1_TIM1_RD1(EBI_BASE), 0x00501100); in ebi_init_smc911x() 20 reg_write(EBI_DEV1_TIM1_RD2(EBI_BASE), 0x0FF02111); in ebi_init_smc911x() 22 reg_write(EBI_DEV1_TIM_EXT(EBI_BASE), 0xFFF00000); in ebi_init_smc911x() 23 reg_write(EBI_DEV1_EXT_ACC(EBI_BASE), 0x0FFFFFFF); in ebi_init_smc911x() 25 reg_write(EBI_DEV1_TIM1_WR1(EBI_BASE), 0x05001100); in ebi_init_smc911x() 54 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); in smc911x_reg_write() 55 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in smc911x_reg_write() 65 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), data); in pkt_data_push() [all …]
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H A D | ebi_nor_flash.c | 14 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), EXT_DEVICE_CHANNEL_2 | addr); in ebi_read() 28 reg_write(EBI_IO_ACCS_DATA(EBI_BASE), val); in ebi_write_u16() 29 reg_write(EBI_CPU_IO_ACCS(EBI_BASE), in ebi_write_u16() 64 reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000); in ebi_init_nor_flash() 66 reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x400002); in ebi_init_nor_flash() 67 reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50); in ebi_init_nor_flash() 69 reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x409113); in ebi_init_nor_flash() 70 reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0xFF01000); in ebi_init_nor_flash() 71 reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x04003113); in ebi_init_nor_flash() 72 reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC12011); in ebi_init_nor_flash() [all …]
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H A D | top.c | 72 reg_write(FWSRAM_TOP_SCL_CFG(FWSRAM_BASE), reg.reg); in top_write_pin() 75 reg_write(FWSRAM_TOP_SDA_CFG(FWSRAM_BASE), reg.reg); in top_write_pin() 78 reg_write(FWSRAM_TOP_TDO_CFG(FWSRAM_BASE), reg.reg); in top_write_pin() 81 reg_write(FWSRAM_TOP_GPIO2_0_CFG(FWSRAM_BASE), reg.reg); in top_write_pin() 90 reg_write(FWSRAM_BASE + FWSRAM_TOP_GPIO2_1_CFG_OFFS + in top_write_pin() 94 reg_write(TOP_BASE + (pin * 4), reg.reg); in top_write_pin() 132 reg_write(TOP_BASE + (pin * 4), reg.reg); in top_set_pin()
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/openbmc/linux/drivers/firewire/ |
H A D | init_ohci1394_dma.c | 114 reg_write(ohci, OHCI1394_BusOptions, bus_options); in init_ohci1394_initialize() 117 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); in init_ohci1394_initialize() 120 reg_write(ohci, OHCI1394_HCControlSet, in init_ohci1394_initialize() 124 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); in init_ohci1394_initialize() 127 reg_write(ohci, OHCI1394_LinkControlSet, in init_ohci1394_initialize() 143 reg_write(ohci, OHCI1394_ATRetries, in init_ohci1394_initialize() 149 reg_write(ohci, OHCI1394_HCControlClear, in init_ohci1394_initialize() 185 reg_write(ohci, OHCI1394_IntEventClear, in init_ohci1394_wait_for_busresets() 199 reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000); in init_ohci1394_enable_physical_dma() 215 reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff); in init_ohci1394_reset_and_init_dma() [all …]
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
H A D | high_speed_env_lib.c | 643 reg_write(SOC_CTRL_REG, tmp); in serdes_phy_config() 1073 reg_write(PEX_PHY_ACCESS_REG in serdes_phy_config() 1103 reg_write(SATA_BASE_REG in serdes_phy_config() 1112 reg_write(SATA_BASE_REG in serdes_phy_config() 1144 reg_write(MV_ETH_REGS_BASE in serdes_phy_config() 1153 reg_write(MV_ETH_REGS_BASE in serdes_phy_config() 1167 reg_write in serdes_phy_config() 1174 reg_write in serdes_phy_config() 1201 reg_write(SOC_CTRL_REG, tmp); in serdes_phy_config() 1334 reg_write in serdes_phy_config() [all …]
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/openbmc/u-boot/board/Synology/ds414/ |
H A D | ds414.c | 133 reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); in board_early_init_f() 134 reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); in board_early_init_f() 135 reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); in board_early_init_f() 138 reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); in board_early_init_f() 139 reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); in board_early_init_f() 140 reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); in board_early_init_f() 143 reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); in board_early_init_f() 144 reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); in board_early_init_f() 145 reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); in board_early_init_f() 148 reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); in board_early_init_f() [all …]
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/openbmc/linux/drivers/media/i2c/ |
H A D | rj54n1cb0c.c | 481 ret = reg_write(client, rv->reg, rv->val); in reg_write_multiple() 515 ret = reg_write(client, reg_xy, in rj54n1_set_rect() 785 ret = reg_write(client, RJ54N1_PEAK_H, in rj54n1_sensor_scale() 838 ret = reg_write(client, RJ54N1_RATIO_TG, in rj54n1_set_clock() 841 ret = reg_write(client, RJ54N1_RATIO_T, in rj54n1_set_clock() 844 ret = reg_write(client, RJ54N1_RATIO_R, in rj54n1_set_clock() 857 ret = reg_write(client, RJ54N1_RATIO_OP, in rj54n1_set_clock() 860 ret = reg_write(client, RJ54N1_RATIO_O, in rj54n1_set_clock() 877 ret = reg_write(client, RJ54N1_PLL_EN, 1); in rj54n1_set_clock() 884 ret = reg_write(client, RJ54N1_CLK_RST, 1); in rj54n1_set_clock() [all …]
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/openbmc/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_write_leveling.c | 78 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw() 501 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_hw_reg_dimm() 672 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_sw() 686 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw() 806 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw() 844 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw() 896 reg_write(REG_DUNIT_CTRL_LOW_ADDR, in ddr3_write_leveling_sw_reg_dimm() 921 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm() 994 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm() 1038 reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_write_leveling_sw_reg_dimm() [all …]
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H A D | ddr3_init.c | 165 reg_write(0x8c04, 0x40000000); in ddr3_restore_and_set_final_windows() 205 reg_write(0x8c04, 0); in ddr3_save_and_set_training_windows() 222 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0); in ddr3_save_and_set_training_windows() 257 reg_write(win_remap_reg + in ddr3_save_and_set_training_windows() 475 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main() 532 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0); in ddr3_init_main() 560 reg_write(DLB_EVICTION_CONTROL_REG, 0x0); in ddr3_init_main() 645 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main() 655 reg_write(REG_BOOTROM_ROUTINE_ADDR, in ddr3_init_main() 791 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init() [all …]
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H A D | xor.c | 41 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init() 45 reg_write(XOR_BASE_ADDR_REG(0, dram_info->num_cs), base); in mv_sys_xor_init() 47 reg_write(XOR_SIZE_MASK_REG(0, dram_info->num_cs), 0x03FF0000); in mv_sys_xor_init() 71 reg_write(XOR_BASE_ADDR_REG(0, cs_count), base); in mv_sys_xor_init() 74 reg_write(XOR_SIZE_MASK_REG(0, cs_count), 0x0FFF0000); in mv_sys_xor_init() 88 reg_write(XOR_WINDOW_CTRL_REG(0, 0), xor_regs_ctrl_backup); in mv_sys_xor_finish() 90 reg_write(XOR_BASE_ADDR_REG(0, ui), xor_regs_base_backup[ui]); in mv_sys_xor_finish() 92 reg_write(XOR_SIZE_MASK_REG(0, ui), xor_regs_mask_backup[ui]); in mv_sys_xor_finish() 94 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish() 186 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init() [all …]
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H A D | ddr3_spd.c | 776 reg_write(REG_SDRAM_CONFIG_ADDR, reg); 952 reg_write(REG_DDR_CONT_HIGH_ADDR, reg); 959 reg_write(0x142C, reg); 1064 reg_write(REG_DDR3_MR0_CS_ADDR + 1077 reg_write(REG_DDR3_MR1_CS_ADDR + 1115 reg_write(REG_DDR3_MR2_CS_ADDR + 1124 reg_write(REG_DDR3_MR3_CS_ADDR + 1136 reg_write(REG_ODT_TIME_LOW_ADDR, reg); 1142 reg_write(REG_ODT_TIME_HIGH_ADDR, reg); 1171 reg_write(REG_ZQC_CONF_ADDR, reg); [all …]
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H A D | ddr3_hw_training.c | 109 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training() 541 reg_write(REG_SDRAM_TIMING_HIGH_ADDR, reg); in ddr3_set_performance_params() 629 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns() 646 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_load_patterns() 650 reg_write(REG_DRAM_TRAINING_1_ADDR, reg); in ddr3_load_patterns() 654 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, 0); in ddr3_load_patterns() 659 reg_write(REG_DRAM_TRAINING_PATTERN_BASE_ADDR, in ddr3_load_patterns() 674 reg_write(REG_DRAM_TRAINING_ADDR, reg); in ddr3_load_patterns() 935 reg_write(REG_DRAM_TRAINING_2_ADDR, reg); in ddr3_training_suspend_resume() 1080 reg_write(REG_DUNIT_ODT_CTRL_ADDR, reg); in ddr3_odt_activate() [all …]
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/openbmc/linux/drivers/media/tuners/ |
H A D | qm1d1c0042.c | 107 return reg_write(state, 0x03, state->regs[0x03]); in qm1d1c0042_set_srch_mode() 117 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup() 205 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params() 230 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params() 269 ret = reg_write(state, 0x0c, val); in qm1d1c0042_set_params() 274 ret = reg_write(state, 0x0c, val); in qm1d1c0042_set_params() 287 ret = reg_write(state, 0x08, 0x09); in qm1d1c0042_set_params() 325 reg_write(state, 0x01, 0x0c); in qm1d1c0042_init() 326 reg_write(state, 0x01, 0x0c); in qm1d1c0042_init() 361 ret = reg_write(state, i, state->regs[i]); in qm1d1c0042_init() [all …]
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/openbmc/linux/drivers/media/usb/gspca/ |
H A D | spca505.c | 533 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function 651 ret = reg_write(gspca_dev, 0x06, 0x16, 0x0a); in sd_start() 654 reg_write(gspca_dev, 0x05, 0xc2, 0x12); in sd_start() 659 reg_write(gspca_dev, 0x02, 0x00, 0x00); in sd_start() 666 return reg_write(gspca_dev, SPCA50X_REG_USB, in sd_start() 674 reg_write(gspca_dev, 0x02, 0x00, 0x00); in sd_stopN() 684 reg_write(gspca_dev, 0x03, 0x03, 0x20); in sd_stop0() 685 reg_write(gspca_dev, 0x03, 0x01, 0x00); in sd_stop0() 686 reg_write(gspca_dev, 0x03, 0x00, 0x01); in sd_stop0() 687 reg_write(gspca_dev, 0x05, 0x10, 0x01); in sd_stop0() [all …]
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H A D | spca508.c | 1278 ret = reg_write(gspca_dev, 0x8802, reg >> 8); in ssi_w() 1290 ret = reg_write(gspca_dev, 0x8800, val); in ssi_w() 1325 ret = reg_write(gspca_dev, (*data)[1], in write_vector() 1393 reg_write(gspca_dev, 0x8500, mode); in sd_start() 1397 reg_write(gspca_dev, 0x8700, 0x28); /* clock */ in sd_start() 1405 reg_write(gspca_dev, 0x8112, 0x10 | 0x20); in sd_start() 1412 reg_write(gspca_dev, 0x8112, 0x20); in sd_stopN() 1439 reg_write(gspca_dev, 0x8651, brightness); in setbrightness() 1440 reg_write(gspca_dev, 0x8652, brightness); in setbrightness() 1441 reg_write(gspca_dev, 0x8653, brightness); in setbrightness() [all …]
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H A D | spca501.c | 1745 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function 1769 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector() 1783 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x12, val); in setbrightness() 1788 reg_write(gspca_dev, 0x00, 0x00, (val >> 8) & 0xff); in setcontrast() 1789 reg_write(gspca_dev, 0x00, 0x01, val & 0xff); in setcontrast() 1794 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x0c, val); in setcolors() 1799 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x11, val); in setblue_balance() 1804 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x13, val); in setred_balance() 1880 reg_write(gspca_dev, SPCA50X_REG_USB, 0x6, 0x94); in sd_start() 1893 reg_write(gspca_dev, SPCA501_REG_CTLRL, 0x01, 0x02); in sd_start() [all …]
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/openbmc/u-boot/drivers/ddr/marvell/a38x/ |
H A D | xor.c | 46 reg_write(XOR_WINDOW_CTRL_REG(0, 0), reg); in mv_sys_xor_init() 81 reg_write(XOR_BASE_ADDR_REG(0, ui), (u32)base); in mv_sys_xor_init() 85 reg_write(XOR_SIZE_MASK_REG(0, ui), (u32)size_mask); in mv_sys_xor_init() 98 reg_write(XOR_WINDOW_CTRL_REG(0, 0), ui_xor_regs_ctrl_backup); in mv_sys_xor_finish() 100 reg_write(XOR_BASE_ADDR_REG(0, ui), in mv_sys_xor_finish() 103 reg_write(XOR_SIZE_MASK_REG(0, ui), in mv_sys_xor_finish() 106 reg_write(XOR_ADDR_OVRD_REG(0, 0), 0); in mv_sys_xor_finish() 188 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init() 200 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init() 207 reg_write(XOR_INIT_VAL_LOW_REG(XOR_UNIT(chan)), init_val_low); in mv_xor_mem_init() [all …]
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/openbmc/linux/drivers/media/platform/st/stm32/dma2d/ |
H A D | dma2d-hw.c | 24 static inline void reg_write(void __iomem *base, u32 reg, u32 val) in reg_write() function 32 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); in reg_update_bits() 49 reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f); in dma2d_clear_int() 58 reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height); in dma2d_config_common() 75 reg_write(d->regs, DMA2D_OMAR_REG, o_addr); in dma2d_config_out() 77 reg_write(d->regs, DMA2D_OCOLR_REG, in dma2d_config_out() 90 reg_write(d->regs, DMA2D_FGMAR_REG, f_addr); in dma2d_config_fg() 105 reg_write(d->regs, DMA2D_FGCOLR_REG, in dma2d_config_fg() 114 reg_write(d->regs, DMA2D_BGMAR_REG, b_addr); in dma2d_config_bg() 129 reg_write(d->regs, DMA2D_BGCOLR_REG, in dma2d_config_bg()
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/openbmc/linux/drivers/base/regmap/ |
H A D | regmap-mmio.c | 25 void (*reg_write)(struct regmap_mmio_context *ctx, member 162 ctx->reg_write(ctx, reg, val); in regmap_mmio_write() 399 .reg_write = regmap_mmio_write, 451 ctx->reg_write = regmap_mmio_iowrite8; in regmap_mmio_gen_context() 457 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context() 469 ctx->reg_write = regmap_mmio_write16le; in regmap_mmio_gen_context() 481 ctx->reg_write = regmap_mmio_write32le; in regmap_mmio_gen_context() 498 ctx->reg_write = regmap_mmio_iowrite8; in regmap_mmio_gen_context() 501 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context() 510 ctx->reg_write = regmap_mmio_write16be; in regmap_mmio_gen_context() [all …]
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/openbmc/linux/drivers/net/dsa/ |
H A D | mv88e6060.c | 63 ret = reg_write(priv, REG_PORT(i), PORT_CONTROL, in mv88e6060_switch_reset() 73 ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, in mv88e6060_switch_reset() 105 ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL, in mv88e6060_setup_global() 112 return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, in mv88e6060_setup_global() 129 ret = reg_write(priv, addr, PORT_CONTROL, in mv88e6060_setup_port() 143 ret = reg_write(priv, addr, PORT_VLAN_MAP, in mv88e6060_setup_port() 156 return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p)); in mv88e6060_setup_port() 174 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val); in mv88e6060_setup_addr() 178 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23, in mv88e6060_setup_addr() 183 return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45, in mv88e6060_setup_addr() [all …]
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/openbmc/linux/drivers/gpu/drm/i2c/ |
H A D | tda998x_drv.c | 695 reg_write(priv, reg, old_val | val); in reg_set() 714 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset() 1025 reg_write(priv, REG_AUDIO_DIV, adiv); in tda998x_configure_audio() 1131 reg_write(priv, REG_ENA_AP, 0); in tda998x_audio_shutdown() 1230 reg_write(priv, REG_DDC_ADDR, 0xa0); in read_edid_block() 1237 reg_write(priv, REG_EDID_CTRL, 0x1); in read_edid_block() 1240 reg_write(priv, REG_EDID_CTRL, 0x0); in read_edid_block() 1407 reg_write(priv, REG_ENA_VP_0, 0xff); in tda998x_bridge_enable() 1565 reg_write(priv, REG_SERIALIZER, 0); in tda998x_bridge_mode_set() 1650 reg_write(priv, REG_TBG_CNTRL_0, 0); in tda998x_bridge_mode_set() [all …]
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/openbmc/linux/drivers/media/pci/tw686x/ |
H A D | tw686x-core.c | 108 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en); in tw686x_disable_channel() 109 reg_write(dev, DMA_CMD, dma_cmd); in tw686x_disable_channel() 134 reg_write(dev, DMA_CMD, dev->pending_dma_cmd); in tw686x_dma_delay() 162 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask); in tw686x_reset_channels() 300 reg_write(dev, SYS_SOFT_RST, 0x0f); in tw686x_probe() 303 reg_write(dev, SRST[0], 0x3f); in tw686x_probe() 305 reg_write(dev, SRST[1], 0x3f); in tw686x_probe() 308 reg_write(dev, DMA_CMD, 0); in tw686x_probe() 309 reg_write(dev, DMA_CHANNEL_ENABLE, 0); in tw686x_probe() 312 reg_write(dev, DMA_CONFIG, 0xffffff04); in tw686x_probe() [all …]
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/openbmc/u-boot/drivers/spi/ |
H A D | mxc_spi.c | 35 #define reg_write(a, v) writel(v, a) macro 146 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc() 148 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc() 202 reg_write(®s->ctrl, reg_ctrl); in spi_cfg_mxc() 204 reg_write(®s->cfg, reg_config); in spi_cfg_mxc() 211 reg_write(®s->intr, 0); in spi_cfg_mxc() 236 reg_write(®s->cfg, mxcs->cfg_reg); in spi_xchg_single() 257 reg_write(®s->txdata, data); in spi_xchg_single() 278 reg_write(®s->txdata, data); in spi_xchg_single() 381 reg_write(®s->rxdata, 1); in mxc_spi_claim_bus_internal() [all …]
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