1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2ae691e57SStefan Roese /*
3ae691e57SStefan Roese * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
4ae691e57SStefan Roese *
5ae691e57SStefan Roese * Copyright (C) 2006 Micronas GmbH
6ae691e57SStefan Roese */
7ae691e57SStefan Roese
8ae691e57SStefan Roese #include <common.h>
9ae691e57SStefan Roese #include <command.h>
10736fead8SBen Warren #include <netdev.h>
11ae691e57SStefan Roese #include <asm/mipsregs.h>
12ae691e57SStefan Roese #include "vct.h"
13ae691e57SStefan Roese
14ae691e57SStefan Roese #if defined(CONFIG_VCT_PREMIUM)
15ae691e57SStefan Roese #define BOARD_NAME "PremiumD"
16ae691e57SStefan Roese #elif defined(CONFIG_VCT_PLATINUM)
17ae691e57SStefan Roese #define BOARD_NAME "PlatinumD"
18ae691e57SStefan Roese #elif defined(CONFIG_VCT_PLATINUMAVC)
19ae691e57SStefan Roese #define BOARD_NAME "PlatinumAVC"
20ae691e57SStefan Roese #else
21ae691e57SStefan Roese #error "vct: No board variant defined!"
22ae691e57SStefan Roese #endif
23ae691e57SStefan Roese
24ae691e57SStefan Roese #if defined(CONFIG_VCT_ONENAND)
25ae691e57SStefan Roese #define BOARD_NAME_ADD " OneNAND"
26ae691e57SStefan Roese #else
27ae691e57SStefan Roese #define BOARD_NAME_ADD " NOR"
28ae691e57SStefan Roese #endif
29ae691e57SStefan Roese
30088454cdSSimon Glass DECLARE_GLOBAL_DATA_PTR;
31088454cdSSimon Glass
board_early_init_f(void)32ae691e57SStefan Roese int board_early_init_f(void)
33ae691e57SStefan Roese {
34ae691e57SStefan Roese /*
35ae691e57SStefan Roese * First initialize the PIN mulitplexing
36ae691e57SStefan Roese */
37ae691e57SStefan Roese vct_pin_mux_initialize();
38ae691e57SStefan Roese
39ae691e57SStefan Roese /*
40ae691e57SStefan Roese * Init the EBI very early so that FLASH can be accessed
41ae691e57SStefan Roese */
42ae691e57SStefan Roese ebi_initialize();
43ae691e57SStefan Roese
44ae691e57SStefan Roese return 0;
45ae691e57SStefan Roese }
46ae691e57SStefan Roese
_machine_restart(void)47ae691e57SStefan Roese void _machine_restart(void)
48ae691e57SStefan Roese {
49ae691e57SStefan Roese reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
50ae691e57SStefan Roese reg_write(WDT_TORR(WDT_BASE), 0x00);
51ae691e57SStefan Roese reg_write(WDT_CR(WDT_BASE), 0x1D);
52ae691e57SStefan Roese
53ae691e57SStefan Roese /*
54ae691e57SStefan Roese * Now wait for the watchdog to trigger the reset
55ae691e57SStefan Roese */
56ae691e57SStefan Roese udelay(1000000);
57ae691e57SStefan Roese }
58ae691e57SStefan Roese
59ae691e57SStefan Roese /*
60ae691e57SStefan Roese * SDRAM is already configured by the bootstrap code, only return the
61ae691e57SStefan Roese * auto-detected size here
62ae691e57SStefan Roese */
dram_init(void)63f1683aa7SSimon Glass int dram_init(void)
64ae691e57SStefan Roese {
65088454cdSSimon Glass gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
66ae691e57SStefan Roese CONFIG_SYS_MBYTES_SDRAM << 20);
67088454cdSSimon Glass
68088454cdSSimon Glass return 0;
69ae691e57SStefan Roese }
70ae691e57SStefan Roese
checkboard(void)71ae691e57SStefan Roese int checkboard(void)
72ae691e57SStefan Roese {
73f0c0b3a9SWolfgang Denk char buf[64];
7400caae6dSSimon Glass int i = env_get_f("serial#", buf, sizeof(buf));
75ae691e57SStefan Roese u32 config0 = read_c0_prid();
76ae691e57SStefan Roese
77ae691e57SStefan Roese if ((config0 & 0xff0000) == PRID_COMP_LEGACY
78ae691e57SStefan Roese && (config0 & 0xff00) == PRID_IMP_LX4280) {
79ae691e57SStefan Roese puts("Board: MDED \n");
80ae691e57SStefan Roese printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
81ae691e57SStefan Roese (config0 >> 8) & 0xFF, config0 & 0xFF);
82ae691e57SStefan Roese } else if ((config0 & 0xff0000) == PRID_COMP_MIPS
83ae691e57SStefan Roese && (config0 & 0xff00) == PRID_IMP_VGC) {
84ae691e57SStefan Roese u32 jedec_id = *((u32 *) 0xBEBC71A0);
85ae691e57SStefan Roese if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
86ae691e57SStefan Roese puts("Board: VGCA \n");
87ae691e57SStefan Roese } else if ((((jedec_id) >> 12) & 0xFF) == 0x48
88ae691e57SStefan Roese || (((jedec_id) >> 12) & 0xFF) == 0x49) {
89ae691e57SStefan Roese puts("Board: VGCB \n");
90ae691e57SStefan Roese }
91ae691e57SStefan Roese printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
92ae691e57SStefan Roese (config0 >> 8) & 0xFF, config0 & 0xFF);
93ae691e57SStefan Roese } else if (config0 == 0x19378) {
94ae691e57SStefan Roese printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
95ae691e57SStefan Roese (config0 >> 8) & 0xFF, config0 & 0xFF);
96ae691e57SStefan Roese } else {
97ae691e57SStefan Roese printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
98ae691e57SStefan Roese config0);
99ae691e57SStefan Roese }
100ae691e57SStefan Roese
101ae691e57SStefan Roese printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
102f0c0b3a9SWolfgang Denk if (i > 0) {
103ae691e57SStefan Roese puts(", serial# ");
104f0c0b3a9SWolfgang Denk puts(buf);
105ae691e57SStefan Roese }
106ae691e57SStefan Roese putc('\n');
107ae691e57SStefan Roese
108ae691e57SStefan Roese return 0;
109ae691e57SStefan Roese }
110736fead8SBen Warren
board_eth_init(bd_t * bis)111736fead8SBen Warren int board_eth_init(bd_t *bis)
112736fead8SBen Warren {
113736fead8SBen Warren int rc = 0;
114736fead8SBen Warren #ifdef CONFIG_SMC911X
115736fead8SBen Warren rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
116736fead8SBen Warren #endif
117736fead8SBen Warren return rc;
118736fead8SBen Warren }
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