Home
last modified time | relevance | path

Searched refs:reg_addr (Results 1 – 25 of 242) sorted by relevance

12345678910

/openbmc/linux/drivers/input/touchscreen/
H A Dedt-ft5x06.c146 struct edt_reg_addr reg_addr; member
590 struct edt_reg_addr *reg_addr = &tsdata->reg_addr; in edt_ft5x06_restore_reg_parameters() local
593 regmap_write(regmap, reg_addr->reg_threshold, tsdata->threshold); in edt_ft5x06_restore_reg_parameters()
594 regmap_write(regmap, reg_addr->reg_gain, tsdata->gain); in edt_ft5x06_restore_reg_parameters()
595 if (reg_addr->reg_offset != NO_REGISTER) in edt_ft5x06_restore_reg_parameters()
596 regmap_write(regmap, reg_addr->reg_offset, tsdata->offset); in edt_ft5x06_restore_reg_parameters()
597 if (reg_addr->reg_offset_x != NO_REGISTER) in edt_ft5x06_restore_reg_parameters()
598 regmap_write(regmap, reg_addr->reg_offset_x, tsdata->offset_x); in edt_ft5x06_restore_reg_parameters()
599 if (reg_addr->reg_offset_y != NO_REGISTER) in edt_ft5x06_restore_reg_parameters()
600 regmap_write(regmap, reg_addr->reg_offset_y, tsdata->offset_y); in edt_ft5x06_restore_reg_parameters()
[all …]
H A Diqs7211.c479 u8 reg_addr[IQS7211_NUM_REG_GRPS][ARRAY_SIZE(iqs7211_devs)]; member
491 .reg_addr = {
512 .reg_addr = {
533 .reg_addr = {
554 .reg_addr = {
573 .reg_addr = {
585 .reg_addr = {
598 .reg_addr = {
617 .reg_addr[IQS7211_REG_GRP_ALP] = {
627 .reg_addr[IQS7211_REG_GRP_BTN] = {
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/css_2401_system/host/
H A Disys_irq_private.h73 unsigned int reg_addr; in isys_irqc_reg_store() local
78 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_store()
80 "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); in isys_irqc_reg_store()
82 ia_css_device_store_uint32(reg_addr, value); in isys_irqc_reg_store()
89 unsigned int reg_addr; in isys_irqc_reg_load() local
95 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_load()
96 value = ia_css_device_load_uint32(reg_addr); in isys_irqc_reg_load()
98 "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); in isys_irqc_reg_load()
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c49 u32 reg_addr = 0; in ddr3_tip_pbs() local
72 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
75 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs()
186 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
192 reg_addr, 0x1f)); in ddr3_tip_pbs()
193 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
199 reg_addr, 0x1f)); in ddr3_tip_pbs()
246 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
254 DDR_PHY_DATA, reg_addr, in ddr3_tip_pbs()
256 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
[all …]
H A Dddr3_training_ip_flow.h53 u32 reg_addr; member
68 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
73 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
78 u32 reg_addr, u32 data_value, u32 reg_mask);
80 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
84 enum hws_ddr_phy e_phy_type, u32 reg_addr,
90 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
92 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
115 int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
116 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
[all …]
H A Dddr3_training_hw_algo.c164 u32 reg_addr = 0xa8; in ddr3_tip_vref() local
203 DDR_PHY_DATA, reg_addr, &val)); in ddr3_tip_vref()
207 pup, DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
377 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
385 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
492 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
500 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
535 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
543 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
565 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
[all …]
/openbmc/linux/arch/riscv/kvm/
H A Dvcpu_vector.c97 void **reg_addr) in kvm_riscv_vcpu_vreg_addr() argument
107 *reg_addr = &cntx->vector.vstart; in kvm_riscv_vcpu_vreg_addr()
110 *reg_addr = &cntx->vector.vl; in kvm_riscv_vcpu_vreg_addr()
113 *reg_addr = &cntx->vector.vtype; in kvm_riscv_vcpu_vreg_addr()
116 *reg_addr = &cntx->vector.vcsr; in kvm_riscv_vcpu_vreg_addr()
125 *reg_addr = cntx->vector.datap + in kvm_riscv_vcpu_vreg_addr()
144 void *reg_addr; in kvm_riscv_vcpu_get_reg_vector() local
150 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, &reg_addr); in kvm_riscv_vcpu_get_reg_vector()
154 if (copy_to_user(uaddr, reg_addr, reg_size)) in kvm_riscv_vcpu_get_reg_vector()
170 void *reg_addr; in kvm_riscv_vcpu_set_reg_vector() local
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Dinput_formatter_private.h27 const hrt_address reg_addr, in input_formatter_reg_store() argument
32 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_store()
33 ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value); in input_formatter_reg_store()
39 const unsigned int reg_addr) in input_formatter_reg_load() argument
43 assert((reg_addr % sizeof(hrt_data)) == 0); in input_formatter_reg_load()
44 return ia_css_device_load_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr); in input_formatter_reg_load()
H A Dgp_device_private.h27 const unsigned int reg_addr, in gp_device_reg_store() argument
32 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_store()
33 ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value); in gp_device_reg_store()
39 const hrt_address reg_addr) in gp_device_reg_load() argument
43 assert((reg_addr % sizeof(hrt_data)) == 0); in gp_device_reg_load()
44 return ia_css_device_load_uint32(GP_DEVICE_BASE[ID] + reg_addr); in gp_device_reg_load()
/openbmc/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_mbx.c41 u64 reg_addr; in pf2vf_read_mbox() local
43 reg_addr = NPS_PKT_MBOX_VF_PF_PFDATAX(ring); in pf2vf_read_mbox()
44 return nitrox_read_csr(ndev, reg_addr); in pf2vf_read_mbox()
50 u64 reg_addr; in pf2vf_write_mbox() local
52 reg_addr = NPS_PKT_MBOX_PF_VF_PFDATAX(ring); in pf2vf_write_mbox()
53 nitrox_write_csr(ndev, reg_addr, value); in pf2vf_write_mbox()
127 u64 value, reg_addr; in nitrox_pf2vf_mbox_handler() local
132 reg_addr = NPS_PKT_MBOX_INT_LO; in nitrox_pf2vf_mbox_handler()
133 value = nitrox_read_csr(ndev, reg_addr); in nitrox_pf2vf_mbox_handler()
151 nitrox_write_csr(ndev, reg_addr, BIT_ULL(i)); in nitrox_pf2vf_mbox_handler()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
48 reg_addr = unit_base_reg + unit_offset * serdes_num; in write_op_execute()
51 printf("Write: 0x%x: 0x%x (mask 0x%x) - ", reg_addr, data, mask); in write_op_execute()
54 reg_data = reg_read(reg_addr); in write_op_execute()
60 reg_write(reg_addr, reg_data); in write_op_execute()
87 u32 reg_addr, reg_data; in poll_op_execute() local
105 reg_addr = unit_base_reg + unit_offset * serdes_num; in poll_op_execute()
109 printf("Poll: 0x%x: 0x%x (mask 0x%x)\n", reg_addr, data, mask); in poll_op_execute()
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
/openbmc/linux/drivers/infiniband/hw/qib/
H A Dqib_diag.c342 const u64 __iomem *reg_addr; in qib_read_umem64() local
347 reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); in qib_read_umem64()
348 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { in qib_read_umem64()
354 reg_end = reg_addr + (count / sizeof(u64)); in qib_read_umem64()
357 while (reg_addr < reg_end) { in qib_read_umem64()
358 u64 data = readq(reg_addr); in qib_read_umem64()
364 reg_addr++; in qib_read_umem64()
386 u64 __iomem *reg_addr; in qib_write_umem64() local
391 reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); in qib_write_umem64()
392 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { in qib_write_umem64()
[all …]
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.h28 unsigned int reg_addr,
31 unsigned int reg_addr,
34 unsigned int reg_addr,
38 unsigned int reg_addr,
43 unsigned int reg_addr);
46 unsigned int reg_addr, unsigned int *data);
49 unsigned int reg_addr, unsigned int count,
H A Dexynos_dp_lowlevel.c474 unsigned int reg_addr, in exynos_dp_write_byte_to_dpcd() argument
484 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_write_byte_to_dpcd()
486 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_write_byte_to_dpcd()
488 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_write_byte_to_dpcd()
514 unsigned int reg_addr, in exynos_dp_read_byte_from_dpcd() argument
525 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_read_byte_from_dpcd()
527 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_read_byte_from_dpcd()
529 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_read_byte_from_dpcd()
553 unsigned int reg_addr, in exynos_dp_write_bytes_to_dpcd() argument
579 reg = AUX_ADDR_7_0(reg_addr + start_offset); in exynos_dp_write_bytes_to_dpcd()
[all …]
/openbmc/u-boot/drivers/video/bridge/
H A Danx6345.c23 unsigned char reg_addr, unsigned char value) in anx6345_write() argument
31 buf[0] = reg_addr; in anx6345_write()
38 __func__, reg_addr, value, ret); in anx6345_write()
46 unsigned char reg_addr, unsigned char *value) in anx6345_read() argument
54 addr = reg_addr; in anx6345_read()
64 __func__, (int)reg_addr, value, ret); in anx6345_read()
72 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_write_r0() argument
77 return anx6345_write(dev, chip->chip_addr, reg_addr, value); in anx6345_write_r0()
80 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_read_r0() argument
85 return anx6345_read(dev, chip->chip_addr, reg_addr, value); in anx6345_read_r0()
[all …]
/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c17 int reg_addr) in pfe_write_addr() argument
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
51 int reg_addr) in pfe_phy_read() argument
61 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << in pfe_phy_read()
64 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_read()
100 phy_addr, reg_addr, val); in pfe_phy_read()
106 int reg_addr, u16 data) in pfe_phy_write() argument
116 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << in pfe_phy_write()
119 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_write()
151 reg_addr, data); in pfe_phy_write()
/openbmc/linux/drivers/reset/
H A Dreset-meson.c39 void __iomem *reg_addr = data->reg_base + (bank << 2); in meson_reset_reset() local
41 writel(BIT(offset), reg_addr); in meson_reset_reset()
53 void __iomem *reg_addr; in meson_reset_level() local
57 reg_addr = data->reg_base + data->param->level_offset + (bank << 2); in meson_reset_level()
61 reg = readl(reg_addr); in meson_reset_level()
63 writel(reg & ~BIT(offset), reg_addr); in meson_reset_level()
65 writel(reg | BIT(offset), reg_addr); in meson_reset_level()
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.c69 unsigned int reg_addr; in mtk_pmx_gpio_set_direction() local
73 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; in mtk_pmx_gpio_set_direction()
77 pctl->devdata->spec_dir_set(&reg_addr, offset); in mtk_pmx_gpio_set_direction()
81 reg_addr = CLR_ADDR(reg_addr, pctl); in mtk_pmx_gpio_set_direction()
83 reg_addr = SET_ADDR(reg_addr, pctl); in mtk_pmx_gpio_set_direction()
85 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); in mtk_pmx_gpio_set_direction()
91 unsigned int reg_addr; in mtk_gpio_set() local
95 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; in mtk_gpio_set()
99 reg_addr = SET_ADDR(reg_addr, pctl); in mtk_gpio_set()
101 reg_addr = CLR_ADDR(reg_addr, pctl); in mtk_gpio_set()
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h46 struct reg_addr { struct
67 static const struct reg_addr page_read_regs_e2[] = { argument
76 static const struct reg_addr page_read_regs_e3[] = {
80 static const struct reg_addr reg_addrs[] = {
1901 static const struct reg_addr idle_reg_addrs[] = {
/openbmc/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_misc.c306 u32 reg_addr; in hns_dsaf_xge_srst_by_port() local
315 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG; in hns_dsaf_xge_srst_by_port()
317 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG; in hns_dsaf_xge_srst_by_port()
319 dsaf_write_sub(dsaf_dev, reg_addr, reg_val); in hns_dsaf_xge_srst_by_port()
343 u32 reg_addr; in hns_dsaf_srst_chns() local
346 reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG; in hns_dsaf_srst_chns()
348 reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG; in hns_dsaf_srst_chns()
350 dsaf_write_sub(dsaf_dev, reg_addr, msk); in hns_dsaf_srst_chns()
461 u32 reg_addr; in hns_ppe_srst_by_port() local
466 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG; in hns_ppe_srst_by_port()
[all …]
/openbmc/linux/drivers/soc/litex/
H A Dlitex_soc_ctrl.c41 static int litex_check_csr_access(void __iomem *reg_addr) in litex_check_csr_access() argument
45 reg = litex_read32(reg_addr + SCRATCH_REG_OFF); in litex_check_csr_access()
53 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_TEST_VALUE); in litex_check_csr_access()
54 reg = litex_read32(reg_addr + SCRATCH_REG_OFF); in litex_check_csr_access()
63 litex_write32(reg_addr + SCRATCH_REG_OFF, SCRATCH_REG_VALUE); in litex_check_csr_access()
/openbmc/linux/arch/microblaze/kernel/
H A Dptrace.c105 microblaze_reg_t *reg_addr = reg_save_addr(addr, child); in arch_ptrace() local
107 val = *reg_addr; in arch_ptrace()
110 *reg_addr = data; in arch_ptrace()
117 u32 paddr = virt_to_phys((u32)reg_addr); in arch_ptrace()
119 *reg_addr = data; in arch_ptrace()
/openbmc/linux/sound/arm/
H A Dpxa2xx-ac97-lib.c49 u32 __iomem *reg_addr; in pxa2xx_ac97_read() local
58 reg_addr = ac97_reg_base + in pxa2xx_ac97_read()
61 reg_addr = ac97_reg_base + in pxa2xx_ac97_read()
63 reg_addr += (reg >> 1); in pxa2xx_ac97_read()
68 val = (readl(reg_addr) & 0xffff); in pxa2xx_ac97_read()
82 val = (readl(reg_addr) & 0xffff); in pxa2xx_ac97_read()
93 u32 __iomem *reg_addr; in pxa2xx_ac97_write() local
100 reg_addr = ac97_reg_base + in pxa2xx_ac97_write()
103 reg_addr = ac97_reg_base + in pxa2xx_ac97_write()
105 reg_addr += (reg >> 1); in pxa2xx_ac97_write()
[all …]
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-i2c.c82 cx_write(bus->reg_addr, msg->addr << 25); in i2c_sendbytes()
106 cx_write(bus->reg_addr, addr); in i2c_sendbytes()
132 cx_write(bus->reg_addr, addr); in i2c_sendbytes()
173 cx_write(bus->reg_addr, msg->addr << 25); in i2c_readbytes()
198 cx_write(bus->reg_addr, msg->addr << 25); in i2c_readbytes()
344 int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value) in cx25821_i2c_read() argument
365 addr[0] = (reg_addr >> 8); in cx25821_i2c_read()
366 addr[1] = (reg_addr & 0xff); in cx25821_i2c_read()
378 int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value) in cx25821_i2c_write() argument
393 buf[0] = reg_addr >> 8; in cx25821_i2c_write()
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb4vf/
H A Dadapter.h430 static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr) in t4_read_reg() argument
432 return readl(adapter->regs + reg_addr); in t4_read_reg()
443 static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val) in t4_write_reg() argument
445 writel(val, adapter->regs + reg_addr); in t4_write_reg()
468 static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr) in t4_read_reg64() argument
470 return readq(adapter->regs + reg_addr); in t4_read_reg64()
481 static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr, in t4_write_reg64() argument
484 writeq(val, adapter->regs + reg_addr); in t4_write_reg64()

12345678910