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Searched refs:reg_addr (Results 1 – 25 of 51) sorted by relevance

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/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_ip_flow.h53 u32 reg_addr; member
68 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
73 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
78 u32 reg_addr, u32 data_value, u32 reg_mask);
80 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
84 enum hws_ddr_phy e_phy_type, u32 reg_addr,
90 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
92 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
115 int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
116 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
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H A Dddr3_training_pbs.c49 u32 reg_addr = 0; in ddr3_tip_pbs() local
72 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
75 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs()
186 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
192 reg_addr, 0x1f)); in ddr3_tip_pbs()
193 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
199 reg_addr, 0x1f)); in ddr3_tip_pbs()
246 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
254 DDR_PHY_DATA, reg_addr, in ddr3_tip_pbs()
256 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
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H A Dddr3_training_ip_prv_if.h42 u32 reg_addr, u32 data, u32 mask);
45 u32 reg_addr, u32 *data, u32 mask);
49 enum hws_ddr_phy phy_type, u32 reg_addr, u32 data);
52 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data);
102 u32 reg_addr, u32 *data);
105 u32 reg_addr, u32 data,
H A Dddr3_training_hw_algo.c164 u32 reg_addr = 0xa8; in ddr3_tip_vref() local
203 DDR_PHY_DATA, reg_addr, &val)); in ddr3_tip_vref()
207 pup, DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
377 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
385 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
492 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
500 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
535 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
543 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
565 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
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H A Dddr3_debug.c113 u32 if_id, reg_addr, data_value, bus_id; in ddr3_tip_reg_dump() local
119 for (reg_addr = 0x1400; reg_addr < 0x19f0; reg_addr += 4) { in ddr3_tip_reg_dump()
120 printf("0x%x ", reg_addr); in ddr3_tip_reg_dump()
125 if_id, reg_addr, read_data, in ddr3_tip_reg_dump()
133 for (reg_addr = 0; reg_addr <= 0xff; reg_addr++) { in ddr3_tip_reg_dump()
134 printf("0x%x ", reg_addr); in ddr3_tip_reg_dump()
144 DDR_PHY_DATA, reg_addr, in ddr3_tip_reg_dump()
155 DDR_PHY_CONTROL, reg_addr, in ddr3_tip_reg_dump()
673 u32 reg_addr, u32 mask) in ddr3_tip_read_adll_value() argument
692 DDR_PHY_DATA, reg_addr, in ddr3_tip_read_adll_value()
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H A Dddr3_init.h152 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
153 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
159 int reg_addr, u32 mask);
161 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dseq_exec.c32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
48 reg_addr = unit_base_reg + unit_offset * serdes_num; in write_op_execute()
51 printf("Write: 0x%x: 0x%x (mask 0x%x) - ", reg_addr, data, mask); in write_op_execute()
54 reg_data = reg_read(reg_addr); in write_op_execute()
60 reg_write(reg_addr, reg_data); in write_op_execute()
87 u32 reg_addr, reg_data; in poll_op_execute() local
105 reg_addr = unit_base_reg + unit_offset * serdes_num; in poll_op_execute()
109 printf("Poll: 0x%x: 0x%x (mask 0x%x)\n", reg_addr, data, mask); in poll_op_execute()
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.h28 unsigned int reg_addr,
31 unsigned int reg_addr,
34 unsigned int reg_addr,
38 unsigned int reg_addr,
43 unsigned int reg_addr);
46 unsigned int reg_addr, unsigned int *data);
49 unsigned int reg_addr, unsigned int count,
H A Dexynos_dp_lowlevel.c474 unsigned int reg_addr, in exynos_dp_write_byte_to_dpcd() argument
484 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_write_byte_to_dpcd()
486 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_write_byte_to_dpcd()
488 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_write_byte_to_dpcd()
514 unsigned int reg_addr, in exynos_dp_read_byte_from_dpcd() argument
525 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_read_byte_from_dpcd()
527 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_read_byte_from_dpcd()
529 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_read_byte_from_dpcd()
553 unsigned int reg_addr, in exynos_dp_write_bytes_to_dpcd() argument
579 reg = AUX_ADDR_7_0(reg_addr + start_offset); in exynos_dp_write_bytes_to_dpcd()
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/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c17 int reg_addr) in pfe_write_addr() argument
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
51 int reg_addr) in pfe_phy_read() argument
61 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << in pfe_phy_read()
64 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_read()
100 phy_addr, reg_addr, val); in pfe_phy_read()
106 int reg_addr, u16 data) in pfe_phy_write() argument
116 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << in pfe_phy_write()
119 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_write()
151 reg_addr, data); in pfe_phy_write()
/openbmc/u-boot/drivers/video/bridge/
H A Danx6345.c23 unsigned char reg_addr, unsigned char value) in anx6345_write() argument
31 buf[0] = reg_addr; in anx6345_write()
38 __func__, reg_addr, value, ret); in anx6345_write()
46 unsigned char reg_addr, unsigned char *value) in anx6345_read() argument
54 addr = reg_addr; in anx6345_read()
64 __func__, (int)reg_addr, value, ret); in anx6345_read()
72 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_write_r0() argument
77 return anx6345_write(dev, chip->chip_addr, reg_addr, value); in anx6345_write_r0()
80 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_read_r0() argument
85 return anx6345_read(dev, chip->chip_addr, reg_addr, value); in anx6345_read_r0()
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H A Dps862x.c36 unsigned char reg_addr, unsigned char value) in ps8622_write() argument
45 buf[0] = reg_addr; in ps8622_write()
52 __func__, reg_addr, value, ret); in ps8622_write()
/openbmc/u-boot/drivers/net/
H A Daspeed_mdio.c59 int reg_addr) in aspeed_mdio_read() argument
68 FTGMAC100_PHYCR_NEW_REGAD(reg_addr); in aspeed_mdio_read()
116 int reg_addr, u16 value) in aspeed_mdio_write() argument
131 | FTGMAC100_PHYCR_REGAD(reg_addr) in aspeed_mdio_write()
156 FTGMAC100_PHYCR_NEW_REGAD(reg_addr); in aspeed_mdio_write()
H A Daspeed_mdio.h12 int reg_addr);
14 int reg_addr, u16 value);
H A Dftgmac100.c101 int reg_addr) in ftgmac100_mdio_read() argument
111 FTGMAC100_PHYCR_REGAD(reg_addr) | in ftgmac100_mdio_read()
120 bus->name, phy_addr, reg_addr); in ftgmac100_mdio_read()
130 int reg_addr, u16 value) in ftgmac100_mdio_write() argument
140 FTGMAC100_PHYCR_REGAD(reg_addr) | in ftgmac100_mdio_write()
152 bus->name, phy_addr, reg_addr); in ftgmac100_mdio_write()
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dvc.c94 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) in omap_vc_bypass_send_value() argument
104 reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; in omap_vc_bypass_send_value()
109 reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | in omap_vc_bypass_send_value()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Drsb.c144 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) in rsb_write() argument
150 writel(reg_addr, &rsb->addr); in rsb_write()
157 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) in rsb_read() argument
164 writel(reg_addr, &rsb->addr); in rsb_read()
/openbmc/u-boot/drivers/net/phy/
H A Dcortina.c128 char reg_addr[0x50] = {0}; in cs4340_upload_firmware() local
209 memcpy(reg_addr, line_temp, i); in cs4340_upload_firmware()
211 strim(reg_addr); in cs4340_upload_firmware()
213 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; in cs4340_upload_firmware()
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
/openbmc/u-boot/cmd/
H A Dpci.c103 u32 reg_addr; in pci_bar_show() local
119 reg_addr = PCI_BASE_ADDRESS_0; in pci_bar_show()
121 dm_pci_read_config32(dev, reg_addr, &base_low); in pci_bar_show()
122 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
123 dm_pci_read_config32(dev, reg_addr, &size_low); in pci_bar_show()
124 dm_pci_write_config32(dev, reg_addr, base_low); in pci_bar_show()
125 reg_addr += 4; in pci_bar_show()
137 dm_pci_read_config32(dev, reg_addr, &base_high); in pci_bar_show()
138 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
139 dm_pci_read_config32(dev, reg_addr, &size_high); in pci_bar_show()
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Drsb.h51 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
52 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c789 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()
791 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
794 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()
815 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2, in ddr3_get_static_mc_value() argument
820 reg = reg_read(reg_addr); in ddr3_get_static_mc_value()
888 while (ddr_mode->regs[j].reg_addr != 0) { in ddr3_static_mc_init()
889 reg_write(ddr_mode->regs[j].reg_addr, in ddr3_static_mc_init()
891 if (ddr_mode->regs[j].reg_addr == in ddr3_static_mc_init()
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-cfu.c218 uint8_t packet_type, row_addr, reg_addr; in cfu_stream_write() local
222 reg_addr = extract32(wfifo[0], 8, 6); in cfu_stream_write()
228 .reg_addr = CFRAME_FDRI, in cfu_stream_write()
240 reg_addr == CFRAME_FDRI) { in cfu_stream_write()
256 .reg_addr = reg_addr, in cfu_stream_write()
283 XlnxCfiPacket pkt = { .reg_addr = CFRAME_SFR, in cfu_sfr_write()
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dfsl_icid.h19 phys_addr_t reg_addr; member
38 .reg_addr = addr, \
/openbmc/qemu/hw/net/
H A Dsungem.c756 uint8_t reg_addr, uint16_t val) in sungem_mii_write() argument
758 trace_sungem_mii_write(phy_addr, reg_addr, val); in sungem_mii_write()
764 uint8_t reg_addr) in __sungem_mii_read() argument
772 switch (reg_addr) { in __sungem_mii_read()
796 uint8_t reg_addr) in sungem_mii_read() argument
800 val = __sungem_mii_read(s, phy_addr, reg_addr); in sungem_mii_read()
802 trace_sungem_mii_read(phy_addr, reg_addr, val); in sungem_mii_read()
809 uint8_t phy_addr, reg_addr, op; in sungem_mii_op() local
817 reg_addr = (val & MIF_FRAME_REGAD) >> 18; in sungem_mii_op()
821 sungem_mii_write(s, phy_addr, reg_addr, val & MIF_FRAME_DATA); in sungem_mii_op()
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/openbmc/qemu/include/hw/misc/
H A Dxlnx-cfi-if.h36 uint8_t reg_addr; member

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