1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Marvell International Ltd. and its affiliates 4 */ 5 6 #ifndef _DDR3_INIT_H 7 #define _DDR3_INIT_H 8 9 #include "ddr_ml_wrapper.h" 10 #include "mv_ddr_plat.h" 11 12 #include "seq_exec.h" 13 #include "ddr3_logging_def.h" 14 #include "ddr3_training_hw_algo.h" 15 #include "ddr3_training_ip.h" 16 #include "ddr3_training_ip_centralization.h" 17 #include "ddr3_training_ip_engine.h" 18 #include "ddr3_training_ip_flow.h" 19 #include "ddr3_training_ip_pbs.h" 20 #include "ddr3_training_ip_prv_if.h" 21 #include "ddr3_training_leveling.h" 22 #include "xor.h" 23 24 /* For checking function return values */ 25 #define CHECK_STATUS(orig_func) \ 26 { \ 27 int status; \ 28 status = orig_func; \ 29 if (MV_OK != status) \ 30 return status; \ 31 } 32 33 #define SUB_VERSION 0 34 35 enum log_level { 36 MV_LOG_LEVEL_0, 37 MV_LOG_LEVEL_1, 38 MV_LOG_LEVEL_2, 39 MV_LOG_LEVEL_3 40 }; 41 42 /* TODO: consider to move to misl phy driver */ 43 #define MISL_PHY_DRV_P_OFFS 0x7 44 #define MISL_PHY_DRV_N_OFFS 0x0 45 #define MISL_PHY_ODT_P_OFFS 0x6 46 #define MISL_PHY_ODT_N_OFFS 0x0 47 48 /* Globals */ 49 extern u8 debug_training, debug_calibration, debug_ddr4_centralization, 50 debug_tap_tuning, debug_dm_tuning; 51 extern u8 is_reg_dump; 52 extern u8 generic_init_controller; 53 /* list of allowed frequency listed in order of enum mv_ddr_freq */ 54 extern u32 is_pll_old; 55 extern struct pattern_info pattern_table[]; 56 extern u8 debug_centralization, debug_training_ip, debug_training_bist, 57 debug_pbs, debug_training_static, debug_leveling; 58 extern struct hws_tip_config_func_db config_func_info[]; 59 extern u8 twr_mask_table[]; 60 extern u8 cl_mask_table[]; 61 extern u8 cwl_mask_table[]; 62 extern u32 speed_bin_table_t_rc[]; 63 extern u32 speed_bin_table_t_rcd_t_rp[]; 64 65 extern u32 vref_init_val; 66 extern u32 g_zpri_data; 67 extern u32 g_znri_data; 68 extern u32 g_zpri_ctrl; 69 extern u32 g_znri_ctrl; 70 extern u32 g_zpodt_data; 71 extern u32 g_znodt_data; 72 extern u32 g_zpodt_ctrl; 73 extern u32 g_znodt_ctrl; 74 extern u32 g_dic; 75 extern u32 g_odt_config; 76 extern u32 g_rtt_nom; 77 extern u32 g_rtt_wr; 78 extern u32 g_rtt_park; 79 80 extern u8 debug_training_access; 81 extern u32 first_active_if; 82 extern u32 delay_enable, ck_delay, ca_delay; 83 extern u32 mask_tune_func; 84 extern u32 rl_version; 85 extern int rl_mid_freq_wa; 86 extern u8 calibration_update_control; /* 2 external only, 1 is internal only */ 87 extern enum mv_ddr_freq medium_freq; 88 89 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]; 90 extern enum mv_ddr_freq low_freq; 91 extern enum auto_tune_stage training_stage; 92 extern u32 is_pll_before_init; 93 extern u32 is_adll_calib_before_init; 94 extern u32 is_dfs_in_init; 95 extern int wl_debug_delay; 96 extern u32 silicon_delay[MAX_DEVICE_NUM]; 97 extern u32 start_pattern, end_pattern; 98 extern u32 phy_reg0_val; 99 extern u32 phy_reg1_val; 100 extern u32 phy_reg2_val; 101 extern u32 phy_reg3_val; 102 extern enum hws_pattern sweep_pattern; 103 extern enum hws_pattern pbs_pattern; 104 extern u32 g_znri_data; 105 extern u32 g_zpri_data; 106 extern u32 g_znri_ctrl; 107 extern u32 g_zpri_ctrl; 108 extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start, 109 n_finger_end, p_finger_step, n_finger_step; 110 extern u32 mode_2t; 111 extern u32 xsb_validate_type; 112 extern u32 xsb_validation_base_address; 113 extern u32 odt_additional; 114 extern u32 debug_mode; 115 extern u32 debug_dunit; 116 extern u32 clamp_tbl[]; 117 extern u32 freq_mask[MAX_DEVICE_NUM][MV_DDR_FREQ_LAST]; 118 119 extern u32 maxt_poll_tries; 120 extern u32 is_bist_reset_bit; 121 122 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM]; 123 extern u32 effective_cs; 124 extern int ddr3_tip_centr_skip_min_win_check; 125 extern u32 *dq_map_table; 126 127 extern u8 debug_training_hw_alg; 128 129 extern u32 start_xsb_offset; 130 extern u32 odt_config; 131 132 extern u16 mask_results_dq_reg_map[]; 133 134 extern u32 target_freq; 135 extern u32 dfs_low_freq; 136 137 extern u32 nominal_avs; 138 extern u32 extension_avs; 139 140 141 /* Prototypes */ 142 int ddr3_init(void); 143 int ddr3_tip_enable_init_sequence(u32 dev_num); 144 145 int ddr3_hws_hw_training(enum hws_algo_type algo_mode); 146 int mv_ddr_early_init(void); 147 int mv_ddr_early_init2(void); 148 int ddr3_silicon_post_init(void); 149 int ddr3_post_run_alg(void); 150 void ddr3_new_tip_ecc_scrub(void); 151 152 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data); 153 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask); 154 int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq); 155 156 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]); 157 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]); 158 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 159 int reg_addr, u32 mask); 160 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 161 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr); 162 int ddr3_tip_restore_dunit_regs(u32 dev_num); 163 void print_topology(struct mv_ddr_topology_map *tm); 164 165 u32 mv_board_id_get(void); 166 167 int ddr3_load_topology_map(void); 168 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level); 169 void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block); 170 int ddr3_tip_tune_training_params(u32 dev_num, 171 struct tune_train_params *params); 172 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps); 173 void ddr3_fast_path_static_cs_size_config(u32 cs_ena); 174 u32 mv_board_id_index_get(u32 board_id); 175 void ddr3_set_log_level(u32 n_log_level); 176 177 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr); 178 179 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode); 180 int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode); 181 void mv_ddr_mc_config(void); 182 int mv_ddr_mc_init(void); 183 void mv_ddr_set_calib_controller(void); 184 /* TODO: consider to move to misl phy driver */ 185 unsigned int mv_ddr_misl_phy_drv_data_p_get(void); 186 unsigned int mv_ddr_misl_phy_drv_data_n_get(void); 187 unsigned int mv_ddr_misl_phy_drv_ctrl_p_get(void); 188 unsigned int mv_ddr_misl_phy_drv_ctrl_n_get(void); 189 unsigned int mv_ddr_misl_phy_odt_p_get(void); 190 unsigned int mv_ddr_misl_phy_odt_n_get(void); 191 192 #endif /* _DDR3_INIT_H */ 193