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Searched refs:ref_ctrl (Results 1 – 25 of 32) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dsdram_elpida.c37 .ref_ctrl = 0x0000030c,
51 .ref_ctrl = 0x000005cd,
65 .ref_ctrl = 0x00000618,
79 .ref_ctrl = 0x00000618,
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dddr.c126 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram_emif4d5()
127 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram_emif4d5()
171 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
184 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
185 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram()
187 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); in config_sdram()
188 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); in config_sdram()
H A Dchilisom.c86 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dsdram.c37 .ref_ctrl = 0x0000081A,
56 .ref_ctrl = 0x0000081A,
75 .ref_ctrl = 0x0000040D,
95 .ref_ctrl = 0x00001035,
119 .ref_ctrl = 0x00001035,
/openbmc/u-boot/board/ti/ti814x/
H A Devm.c47 .ref_ctrl = 0x10000c30,
56 .ref_ctrl = 0x10000c30,
/openbmc/u-boot/board/ti/am43xx/
H A Dboard.c155 .ref_ctrl = 0x0000040D,
191 .ref_ctrl = 0x00000C30,
217 .ref_ctrl = 0x00000C30,
240 .ref_ctrl = 0x00000C30,
263 .ref_ctrl = 0x00000c30,
289 .ref_ctrl = 0x00000c30,
/openbmc/u-boot/board/siemens/draco/
H A Dboard.c103 PRINTARGS(ref_ctrl); in print_ddr3_timings()
224 draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; in board_init_ddr()
H A Dboard.h44 unsigned int ref_ctrl; /* 0x0000093B */ member
/openbmc/u-boot/board/ti/dra7xx/
H A Devm.c66 .ref_ctrl = 0x000040F1,
91 .ref_ctrl = 0x000040F1,
116 .ref_ctrl = 0x0000514C,
141 .ref_ctrl = 0x0000514D,
166 .ref_ctrl = 0x000040F1,
191 .ref_ctrl = 0x000040F1,
216 .ref_ctrl = 0x0000514C,
241 .ref_ctrl = 0x0000514C,
/openbmc/u-boot/board/ti/am335x/
H A Dboard.c109 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
118 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
200 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
211 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
222 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
234 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
/openbmc/u-boot/board/compulab/cl-som-am57x/
H A Dspl.c33 .ref_ctrl = 0x000040f1,
101 .ref_ctrl = 0x000040f1,
/openbmc/u-boot/board/phytec/pcm051/
H A Dboard.c81 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
124 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
/openbmc/u-boot/board/gumstix/pepper/
H A Dboard.c57 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
91 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
/openbmc/u-boot/board/isee/igep003x/
H A Dboard.c106 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
116 .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
/openbmc/u-boot/board/compulab/cm_t54/
H A Dspl.c21 .ref_ctrl = 0x00001040,
/openbmc/u-boot/arch/arm/mach-omap2/
H A Demif-common.c169 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); in emif_update_timings()
410 writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, in dra7_ddr3_init()
427 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); in dra7_ddr3_init()
465 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); in omap5_ddr3_init()
670 u32 ref_ctrl = 0, val = 0, freq_khz; in get_sdram_ref_ctrl() local
677 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; in get_sdram_ref_ctrl()
679 return ref_ctrl; in get_sdram_ref_ctrl()
969 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); in emif_calculate_regs()
995 print_timing_reg(regs->ref_ctrl); in emif_calculate_regs()
/openbmc/u-boot/board/compulab/cm_t43/
H A Dspl.c35 .ref_ctrl = 0x00000C30,
/openbmc/u-boot/board/compulab/cm_t335/
H A Dspl.c50 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
/openbmc/u-boot/board/ti/ti816x/
H A Devm.c93 .ref_ctrl = EMIF_SDREF,
/openbmc/u-boot/board/BuR/brppt1/
H A Dboard.c59 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
/openbmc/u-boot/board/ti/am57xx/
H A Dboard.c112 .ref_ctrl = 0x000040F1,
176 .ref_ctrl = 0x000040F1,
239 .ref_ctrl = 0x0000514d,
264 .ref_ctrl = 0x0000514d,
/openbmc/linux/drivers/memory/
H A Demif.c502 u32 tim1, tim3, ref_ctrl, type; in setup_temperature_sensitive_regs() local
510 ref_ctrl = regs->ref_ctrl_shdw; in setup_temperature_sensitive_regs()
518 ref_ctrl = regs->ref_ctrl_shdw_derated; in setup_temperature_sensitive_regs()
522 ref_ctrl = regs->ref_ctrl_shdw_derated; in setup_temperature_sensitive_regs()
528 writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW); in setup_temperature_sensitive_regs()
/openbmc/u-boot/board/silica/pengwyn/
H A Dboard.c45 .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
/openbmc/u-boot/board/eets/pdu001/
H A Dboard.c177 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
/openbmc/u-boot/board/BuR/brxre1/
H A Dboard.c91 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,

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