183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
274cc8b09SKipisz, Steven /*
374cc8b09SKipisz, Steven * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
474cc8b09SKipisz, Steven *
574cc8b09SKipisz, Steven * Author: Felipe Balbi <balbi@ti.com>
674cc8b09SKipisz, Steven *
774cc8b09SKipisz, Steven * Based on board/ti/dra7xx/evm.c
874cc8b09SKipisz, Steven */
974cc8b09SKipisz, Steven
1074cc8b09SKipisz, Steven #include <common.h>
1174cc8b09SKipisz, Steven #include <palmas.h>
1274cc8b09SKipisz, Steven #include <sata.h>
1374cc8b09SKipisz, Steven #include <usb.h>
1474cc8b09SKipisz, Steven #include <asm/omap_common.h>
1517c29873SAndreas Dannenberg #include <asm/omap_sec_common.h>
1674cc8b09SKipisz, Steven #include <asm/emif.h>
1774cc8b09SKipisz, Steven #include <asm/gpio.h>
1874cc8b09SKipisz, Steven #include <asm/arch/gpio.h>
1974cc8b09SKipisz, Steven #include <asm/arch/clock.h>
2074cc8b09SKipisz, Steven #include <asm/arch/dra7xx_iodelay.h>
2174cc8b09SKipisz, Steven #include <asm/arch/sys_proto.h>
2274cc8b09SKipisz, Steven #include <asm/arch/mmc_host_def.h>
2374cc8b09SKipisz, Steven #include <asm/arch/sata.h>
2474cc8b09SKipisz, Steven #include <asm/arch/gpio.h>
2574cc8b09SKipisz, Steven #include <asm/arch/omap.h>
2674cc8b09SKipisz, Steven #include <environment.h>
2774cc8b09SKipisz, Steven #include <usb.h>
2874cc8b09SKipisz, Steven #include <linux/usb/gadget.h>
2974cc8b09SKipisz, Steven #include <dwc3-uboot.h>
3074cc8b09SKipisz, Steven #include <dwc3-omap-uboot.h>
3174cc8b09SKipisz, Steven #include <ti-usb-phy-uboot.h>
32c413baa9SKishon Vijay Abraham I #include <mmc.h>
3374cc8b09SKipisz, Steven
34212f96f6SKipisz, Steven #include "../common/board_detect.h"
3574cc8b09SKipisz, Steven #include "mux_data.h"
3674cc8b09SKipisz, Steven
37212f96f6SKipisz, Steven #define board_is_x15() board_ti_is("BBRDX15_")
38f7f9f6beSLokesh Vutla #define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
3970879224SLokesh Vutla !strncmp("B.10", board_ti_get_rev(), 3))
40f70a4272SLokesh Vutla #define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
41f70a4272SLokesh Vutla !strncmp("C.00", board_ti_get_rev(), 3))
42212f96f6SKipisz, Steven #define board_is_am572x_evm() board_ti_is("AM572PM_")
43bf43ce6cSNishanth Menon #define board_is_am572x_evm_reva3() \
44bf43ce6cSNishanth Menon (board_ti_is("AM572PM_") && \
4570879224SLokesh Vutla !strncmp("A.30", board_ti_get_rev(), 3))
469646b95fSLokesh Vutla #define board_is_am574x_idk() board_ti_is("AM574IDK")
47c020d355SSteve Kipisz #define board_is_am572x_idk() board_ti_is("AM572IDK")
484d8397c6SSteve Kipisz #define board_is_am571x_idk() board_ti_is("AM571IDK")
49212f96f6SKipisz, Steven
5074cc8b09SKipisz, Steven #ifdef CONFIG_DRIVER_TI_CPSW
5174cc8b09SKipisz, Steven #include <cpsw.h>
5274cc8b09SKipisz, Steven #endif
5374cc8b09SKipisz, Steven
5474cc8b09SKipisz, Steven DECLARE_GLOBAL_DATA_PTR;
5574cc8b09SKipisz, Steven
5637611052SRoger Quadros #define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
5774cc8b09SKipisz, Steven /* GPIO 7_11 */
5874cc8b09SKipisz, Steven #define GPIO_DDR_VTT_EN 203
5974cc8b09SKipisz, Steven
60fcb18524SNishanth Menon /* Touch screen controller to identify the LCD */
61fcb18524SNishanth Menon #define OSD_TS_FT_BUS_ADDRESS 0
62fcb18524SNishanth Menon #define OSD_TS_FT_CHIP_ADDRESS 0x38
63fcb18524SNishanth Menon #define OSD_TS_FT_REG_ID 0xA3
64fcb18524SNishanth Menon /*
65fcb18524SNishanth Menon * Touchscreen IDs for various OSD panels
66fcb18524SNishanth Menon * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
67fcb18524SNishanth Menon */
68fcb18524SNishanth Menon /* Used on newer osd101t2587 Panels */
69fcb18524SNishanth Menon #define OSD_TS_FT_ID_5x46 0x54
70fcb18524SNishanth Menon /* Used on older osd101t2045 Panels */
71fcb18524SNishanth Menon #define OSD_TS_FT_ID_5606 0x08
72fcb18524SNishanth Menon
73212f96f6SKipisz, Steven #define SYSINFO_BOARD_NAME_MAX_LEN 45
74212f96f6SKipisz, Steven
75385d3632SKeerthy #define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
76385d3632SKeerthy #define TPS65903X_PAD2_POWERHOLD_MASK 0x20
77385d3632SKeerthy
7874cc8b09SKipisz, Steven const struct omap_sysinfo sysinfo = {
79212f96f6SKipisz, Steven "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
8074cc8b09SKipisz, Steven };
8174cc8b09SKipisz, Steven
8274cc8b09SKipisz, Steven static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
8374cc8b09SKipisz, Steven .dmm_lisa_map_3 = 0x80740300,
8474cc8b09SKipisz, Steven .is_ma_present = 0x1
8574cc8b09SKipisz, Steven };
8674cc8b09SKipisz, Steven
874d8397c6SSteve Kipisz static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
884d8397c6SSteve Kipisz .dmm_lisa_map_3 = 0x80640100,
894d8397c6SSteve Kipisz .is_ma_present = 0x1
904d8397c6SSteve Kipisz };
914d8397c6SSteve Kipisz
927b16de85SLokesh Vutla static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
937b16de85SLokesh Vutla .dmm_lisa_map_2 = 0xc0600200,
947b16de85SLokesh Vutla .dmm_lisa_map_3 = 0x80600100,
957b16de85SLokesh Vutla .is_ma_present = 0x1
967b16de85SLokesh Vutla };
977b16de85SLokesh Vutla
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)9874cc8b09SKipisz, Steven void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
9974cc8b09SKipisz, Steven {
1004d8397c6SSteve Kipisz if (board_is_am571x_idk())
1014d8397c6SSteve Kipisz *dmm_lisa_regs = &am571x_idk_lisa_regs;
1027b16de85SLokesh Vutla else if (board_is_am574x_idk())
1037b16de85SLokesh Vutla *dmm_lisa_regs = &am574x_idk_lisa_regs;
1044d8397c6SSteve Kipisz else
10574cc8b09SKipisz, Steven *dmm_lisa_regs = &beagle_x15_lisa_regs;
10674cc8b09SKipisz, Steven }
10774cc8b09SKipisz, Steven
10874cc8b09SKipisz, Steven static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
10974cc8b09SKipisz, Steven .sdram_config_init = 0x61851b32,
11074cc8b09SKipisz, Steven .sdram_config = 0x61851b32,
11111e2b043SLokesh Vutla .sdram_config2 = 0x08000000,
11274cc8b09SKipisz, Steven .ref_ctrl = 0x000040F1,
11374cc8b09SKipisz, Steven .ref_ctrl_final = 0x00001035,
11411e2b043SLokesh Vutla .sdram_tim1 = 0xcccf36ab,
11511e2b043SLokesh Vutla .sdram_tim2 = 0x308f7fda,
11611e2b043SLokesh Vutla .sdram_tim3 = 0x409f88a8,
11774cc8b09SKipisz, Steven .read_idle_ctrl = 0x00050000,
11811e2b043SLokesh Vutla .zq_config = 0x5007190b,
11974cc8b09SKipisz, Steven .temp_alert_config = 0x00000000,
12074cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1_init = 0x0024400b,
12174cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1 = 0x0e24400b,
12274cc8b09SKipisz, Steven .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
12311e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
12411e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
12511e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
12611e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
12774cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_win = 0x00000000,
12874cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
12974cc8b09SKipisz, Steven .emif_rd_wr_lvl_ctl = 0x00000000,
13074cc8b09SKipisz, Steven .emif_rd_wr_exec_thresh = 0x00000305
13174cc8b09SKipisz, Steven };
13274cc8b09SKipisz, Steven
13374cc8b09SKipisz, Steven /* Ext phy ctrl regs 1-35 */
13474cc8b09SKipisz, Steven static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
13574cc8b09SKipisz, Steven 0x10040100,
13611e2b043SLokesh Vutla 0x00910091,
13711e2b043SLokesh Vutla 0x00950095,
13811e2b043SLokesh Vutla 0x009B009B,
13911e2b043SLokesh Vutla 0x009E009E,
14011e2b043SLokesh Vutla 0x00980098,
14174cc8b09SKipisz, Steven 0x00340034,
14274cc8b09SKipisz, Steven 0x00350035,
14311e2b043SLokesh Vutla 0x00340034,
14411e2b043SLokesh Vutla 0x00310031,
14511e2b043SLokesh Vutla 0x00340034,
14611e2b043SLokesh Vutla 0x007F007F,
14711e2b043SLokesh Vutla 0x007F007F,
14811e2b043SLokesh Vutla 0x007F007F,
14911e2b043SLokesh Vutla 0x007F007F,
15011e2b043SLokesh Vutla 0x007F007F,
15111e2b043SLokesh Vutla 0x00480048,
15211e2b043SLokesh Vutla 0x004A004A,
15311e2b043SLokesh Vutla 0x00520052,
15411e2b043SLokesh Vutla 0x00550055,
15511e2b043SLokesh Vutla 0x00500050,
15674cc8b09SKipisz, Steven 0x00000000,
15774cc8b09SKipisz, Steven 0x00600020,
15874cc8b09SKipisz, Steven 0x40011080,
15974cc8b09SKipisz, Steven 0x08102040,
16011e2b043SLokesh Vutla 0x0,
16111e2b043SLokesh Vutla 0x0,
16211e2b043SLokesh Vutla 0x0,
16311e2b043SLokesh Vutla 0x0,
16411e2b043SLokesh Vutla 0x0,
16574cc8b09SKipisz, Steven 0x0,
16674cc8b09SKipisz, Steven 0x0,
16774cc8b09SKipisz, Steven 0x0,
16874cc8b09SKipisz, Steven 0x0,
16974cc8b09SKipisz, Steven 0x0
17074cc8b09SKipisz, Steven };
17174cc8b09SKipisz, Steven
17274cc8b09SKipisz, Steven static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
17374cc8b09SKipisz, Steven .sdram_config_init = 0x61851b32,
17474cc8b09SKipisz, Steven .sdram_config = 0x61851b32,
17511e2b043SLokesh Vutla .sdram_config2 = 0x08000000,
17674cc8b09SKipisz, Steven .ref_ctrl = 0x000040F1,
17774cc8b09SKipisz, Steven .ref_ctrl_final = 0x00001035,
1785f405e7fSSchuyler Patton .sdram_tim1 = 0xcccf36b3,
17911e2b043SLokesh Vutla .sdram_tim2 = 0x308f7fda,
1805f405e7fSSchuyler Patton .sdram_tim3 = 0x407f88a8,
18174cc8b09SKipisz, Steven .read_idle_ctrl = 0x00050000,
18211e2b043SLokesh Vutla .zq_config = 0x5007190b,
18374cc8b09SKipisz, Steven .temp_alert_config = 0x00000000,
18474cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1_init = 0x0024400b,
18574cc8b09SKipisz, Steven .emif_ddr_phy_ctlr_1 = 0x0e24400b,
18674cc8b09SKipisz, Steven .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
18711e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
18811e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
18911e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
19011e2b043SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
19174cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_win = 0x00000000,
19274cc8b09SKipisz, Steven .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
19374cc8b09SKipisz, Steven .emif_rd_wr_lvl_ctl = 0x00000000,
19474cc8b09SKipisz, Steven .emif_rd_wr_exec_thresh = 0x00000305
19574cc8b09SKipisz, Steven };
19674cc8b09SKipisz, Steven
19774cc8b09SKipisz, Steven static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
19874cc8b09SKipisz, Steven 0x10040100,
19911e2b043SLokesh Vutla 0x00910091,
20011e2b043SLokesh Vutla 0x00950095,
20111e2b043SLokesh Vutla 0x009B009B,
20211e2b043SLokesh Vutla 0x009E009E,
20311e2b043SLokesh Vutla 0x00980098,
20411e2b043SLokesh Vutla 0x00340034,
20574cc8b09SKipisz, Steven 0x00350035,
20611e2b043SLokesh Vutla 0x00340034,
20711e2b043SLokesh Vutla 0x00310031,
20811e2b043SLokesh Vutla 0x00340034,
20911e2b043SLokesh Vutla 0x007F007F,
21011e2b043SLokesh Vutla 0x007F007F,
21111e2b043SLokesh Vutla 0x007F007F,
21211e2b043SLokesh Vutla 0x007F007F,
21311e2b043SLokesh Vutla 0x007F007F,
21411e2b043SLokesh Vutla 0x00480048,
21511e2b043SLokesh Vutla 0x004A004A,
21611e2b043SLokesh Vutla 0x00520052,
21711e2b043SLokesh Vutla 0x00550055,
21811e2b043SLokesh Vutla 0x00500050,
21974cc8b09SKipisz, Steven 0x00000000,
22074cc8b09SKipisz, Steven 0x00600020,
22174cc8b09SKipisz, Steven 0x40011080,
22274cc8b09SKipisz, Steven 0x08102040,
22311e2b043SLokesh Vutla 0x0,
22411e2b043SLokesh Vutla 0x0,
22511e2b043SLokesh Vutla 0x0,
22611e2b043SLokesh Vutla 0x0,
22711e2b043SLokesh Vutla 0x0,
22874cc8b09SKipisz, Steven 0x0,
22974cc8b09SKipisz, Steven 0x0,
23074cc8b09SKipisz, Steven 0x0,
23174cc8b09SKipisz, Steven 0x0,
23274cc8b09SKipisz, Steven 0x0
23374cc8b09SKipisz, Steven };
23474cc8b09SKipisz, Steven
235209742faSSteve Kipisz static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
236209742faSSteve Kipisz .sdram_config_init = 0x61863332,
237209742faSSteve Kipisz .sdram_config = 0x61863332,
238209742faSSteve Kipisz .sdram_config2 = 0x08000000,
239209742faSSteve Kipisz .ref_ctrl = 0x0000514d,
240209742faSSteve Kipisz .ref_ctrl_final = 0x0000144a,
241209742faSSteve Kipisz .sdram_tim1 = 0xd333887c,
2427b16de85SLokesh Vutla .sdram_tim2 = 0x30b37fe3,
2437b16de85SLokesh Vutla .sdram_tim3 = 0x409f8ad8,
244209742faSSteve Kipisz .read_idle_ctrl = 0x00050000,
245209742faSSteve Kipisz .zq_config = 0x5007190b,
246209742faSSteve Kipisz .temp_alert_config = 0x00000000,
247209742faSSteve Kipisz .emif_ddr_phy_ctlr_1_init = 0x0024400f,
248209742faSSteve Kipisz .emif_ddr_phy_ctlr_1 = 0x0e24400f,
249209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
250209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
251209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
252209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
253209742faSSteve Kipisz .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
254209742faSSteve Kipisz .emif_rd_wr_lvl_rmp_win = 0x00000000,
255209742faSSteve Kipisz .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
256209742faSSteve Kipisz .emif_rd_wr_lvl_ctl = 0x00000000,
257209742faSSteve Kipisz .emif_rd_wr_exec_thresh = 0x00000305
258209742faSSteve Kipisz };
259209742faSSteve Kipisz
2607b16de85SLokesh Vutla static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
2617b16de85SLokesh Vutla .sdram_config_init = 0x61863332,
2627b16de85SLokesh Vutla .sdram_config = 0x61863332,
2637b16de85SLokesh Vutla .sdram_config2 = 0x08000000,
2647b16de85SLokesh Vutla .ref_ctrl = 0x0000514d,
2657b16de85SLokesh Vutla .ref_ctrl_final = 0x0000144a,
2667b16de85SLokesh Vutla .sdram_tim1 = 0xd333887c,
2677b16de85SLokesh Vutla .sdram_tim2 = 0x30b37fe3,
2687b16de85SLokesh Vutla .sdram_tim3 = 0x409f8ad8,
2697b16de85SLokesh Vutla .read_idle_ctrl = 0x00050000,
2707b16de85SLokesh Vutla .zq_config = 0x5007190b,
2717b16de85SLokesh Vutla .temp_alert_config = 0x00000000,
2727b16de85SLokesh Vutla .emif_ddr_phy_ctlr_1_init = 0x0024400f,
2737b16de85SLokesh Vutla .emif_ddr_phy_ctlr_1 = 0x0e24400f,
2747b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
2757b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
2767b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
2777b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
2787b16de85SLokesh Vutla .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
2797b16de85SLokesh Vutla .emif_rd_wr_lvl_rmp_win = 0x00000000,
2807b16de85SLokesh Vutla .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
2817b16de85SLokesh Vutla .emif_rd_wr_lvl_ctl = 0x00000000,
2827b16de85SLokesh Vutla .emif_rd_wr_exec_thresh = 0x00000305,
2837b16de85SLokesh Vutla .emif_ecc_ctrl_reg = 0xD0000001,
2847b16de85SLokesh Vutla .emif_ecc_address_range_1 = 0x3FFF0000,
2857b16de85SLokesh Vutla .emif_ecc_address_range_2 = 0x00000000
2867b16de85SLokesh Vutla };
2877b16de85SLokesh Vutla
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)28874cc8b09SKipisz, Steven void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
28974cc8b09SKipisz, Steven {
29074cc8b09SKipisz, Steven switch (emif_nr) {
29174cc8b09SKipisz, Steven case 1:
292209742faSSteve Kipisz if (board_is_am571x_idk())
293209742faSSteve Kipisz *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
2947b16de85SLokesh Vutla else if (board_is_am574x_idk())
2957b16de85SLokesh Vutla *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
296209742faSSteve Kipisz else
29774cc8b09SKipisz, Steven *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
29874cc8b09SKipisz, Steven break;
29974cc8b09SKipisz, Steven case 2:
3007b16de85SLokesh Vutla if (board_is_am574x_idk())
3017b16de85SLokesh Vutla *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
3027b16de85SLokesh Vutla else
30374cc8b09SKipisz, Steven *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
30474cc8b09SKipisz, Steven break;
30574cc8b09SKipisz, Steven }
30674cc8b09SKipisz, Steven }
30774cc8b09SKipisz, Steven
emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,const u32 ** regs,u32 * size)30874cc8b09SKipisz, Steven void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
30974cc8b09SKipisz, Steven {
31074cc8b09SKipisz, Steven switch (emif_nr) {
31174cc8b09SKipisz, Steven case 1:
31274cc8b09SKipisz, Steven *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
31374cc8b09SKipisz, Steven *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
31474cc8b09SKipisz, Steven break;
31574cc8b09SKipisz, Steven case 2:
31674cc8b09SKipisz, Steven *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
31774cc8b09SKipisz, Steven *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
31874cc8b09SKipisz, Steven break;
31974cc8b09SKipisz, Steven }
32074cc8b09SKipisz, Steven }
32174cc8b09SKipisz, Steven
32274cc8b09SKipisz, Steven struct vcores_data beagle_x15_volts = {
323beb71279SLokesh Vutla .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
324beb71279SLokesh Vutla .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
32574cc8b09SKipisz, Steven .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
32674cc8b09SKipisz, Steven .mpu.addr = TPS659038_REG_ADDR_SMPS12,
32774cc8b09SKipisz, Steven .mpu.pmic = &tps659038,
3283708e78cSNishanth Menon .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
32974cc8b09SKipisz, Steven
330beb71279SLokesh Vutla .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
331beb71279SLokesh Vutla .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
332beb71279SLokesh Vutla .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
333beb71279SLokesh Vutla .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
334beb71279SLokesh Vutla .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
335beb71279SLokesh Vutla .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
33674cc8b09SKipisz, Steven .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
33774cc8b09SKipisz, Steven .eve.addr = TPS659038_REG_ADDR_SMPS45,
33874cc8b09SKipisz, Steven .eve.pmic = &tps659038,
339e52e334eSNishanth Menon .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
34074cc8b09SKipisz, Steven
341beb71279SLokesh Vutla .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
342beb71279SLokesh Vutla .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
343beb71279SLokesh Vutla .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
344beb71279SLokesh Vutla .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
345beb71279SLokesh Vutla .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
346beb71279SLokesh Vutla .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
34774cc8b09SKipisz, Steven .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
34874cc8b09SKipisz, Steven .gpu.addr = TPS659038_REG_ADDR_SMPS45,
34974cc8b09SKipisz, Steven .gpu.pmic = &tps659038,
350e52e334eSNishanth Menon .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
35174cc8b09SKipisz, Steven
352beb71279SLokesh Vutla .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
353beb71279SLokesh Vutla .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
35474cc8b09SKipisz, Steven .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
35574cc8b09SKipisz, Steven .core.addr = TPS659038_REG_ADDR_SMPS6,
35674cc8b09SKipisz, Steven .core.pmic = &tps659038,
35774cc8b09SKipisz, Steven
358beb71279SLokesh Vutla .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
359beb71279SLokesh Vutla .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
360beb71279SLokesh Vutla .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
361beb71279SLokesh Vutla .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
362beb71279SLokesh Vutla .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
363beb71279SLokesh Vutla .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
36474cc8b09SKipisz, Steven .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
36574cc8b09SKipisz, Steven .iva.addr = TPS659038_REG_ADDR_SMPS45,
36674cc8b09SKipisz, Steven .iva.pmic = &tps659038,
367e52e334eSNishanth Menon .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
36874cc8b09SKipisz, Steven };
36974cc8b09SKipisz, Steven
370d60198daSKeerthy struct vcores_data am572x_idk_volts = {
371beb71279SLokesh Vutla .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
372beb71279SLokesh Vutla .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
373d60198daSKeerthy .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374d60198daSKeerthy .mpu.addr = TPS659038_REG_ADDR_SMPS12,
375d60198daSKeerthy .mpu.pmic = &tps659038,
376d60198daSKeerthy .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
377d60198daSKeerthy
378beb71279SLokesh Vutla .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
379beb71279SLokesh Vutla .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
380beb71279SLokesh Vutla .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
381beb71279SLokesh Vutla .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
382beb71279SLokesh Vutla .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
383beb71279SLokesh Vutla .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
384d60198daSKeerthy .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385d60198daSKeerthy .eve.addr = TPS659038_REG_ADDR_SMPS45,
386d60198daSKeerthy .eve.pmic = &tps659038,
387d60198daSKeerthy .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
388d60198daSKeerthy
389beb71279SLokesh Vutla .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
390beb71279SLokesh Vutla .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
391beb71279SLokesh Vutla .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
392beb71279SLokesh Vutla .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
393beb71279SLokesh Vutla .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
394beb71279SLokesh Vutla .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
395d60198daSKeerthy .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
396d60198daSKeerthy .gpu.addr = TPS659038_REG_ADDR_SMPS6,
397d60198daSKeerthy .gpu.pmic = &tps659038,
398d60198daSKeerthy .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
399d60198daSKeerthy
400beb71279SLokesh Vutla .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
401beb71279SLokesh Vutla .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
402d60198daSKeerthy .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
403d60198daSKeerthy .core.addr = TPS659038_REG_ADDR_SMPS7,
404d60198daSKeerthy .core.pmic = &tps659038,
405d60198daSKeerthy
406beb71279SLokesh Vutla .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
407beb71279SLokesh Vutla .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
408beb71279SLokesh Vutla .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
409beb71279SLokesh Vutla .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
410beb71279SLokesh Vutla .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
411beb71279SLokesh Vutla .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
412d60198daSKeerthy .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
413d60198daSKeerthy .iva.addr = TPS659038_REG_ADDR_SMPS8,
414d60198daSKeerthy .iva.pmic = &tps659038,
415d60198daSKeerthy .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
416d60198daSKeerthy };
417d60198daSKeerthy
418b12550ebSKeerthy struct vcores_data am571x_idk_volts = {
419b12550ebSKeerthy .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
420b12550ebSKeerthy .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
421b12550ebSKeerthy .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422b12550ebSKeerthy .mpu.addr = TPS659038_REG_ADDR_SMPS12,
423b12550ebSKeerthy .mpu.pmic = &tps659038,
424b12550ebSKeerthy .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
425b12550ebSKeerthy
426b12550ebSKeerthy .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
427b12550ebSKeerthy .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
428b12550ebSKeerthy .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
429b12550ebSKeerthy .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
430b12550ebSKeerthy .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
431b12550ebSKeerthy .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
432b12550ebSKeerthy .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433b12550ebSKeerthy .eve.addr = TPS659038_REG_ADDR_SMPS45,
434b12550ebSKeerthy .eve.pmic = &tps659038,
435b12550ebSKeerthy .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
436b12550ebSKeerthy
437b12550ebSKeerthy .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
438b12550ebSKeerthy .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
439b12550ebSKeerthy .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
440b12550ebSKeerthy .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
441b12550ebSKeerthy .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
442b12550ebSKeerthy .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
443b12550ebSKeerthy .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444b12550ebSKeerthy .gpu.addr = TPS659038_REG_ADDR_SMPS6,
445b12550ebSKeerthy .gpu.pmic = &tps659038,
446b12550ebSKeerthy .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
447b12550ebSKeerthy
448b12550ebSKeerthy .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
449b12550ebSKeerthy .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
450b12550ebSKeerthy .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451b12550ebSKeerthy .core.addr = TPS659038_REG_ADDR_SMPS7,
452b12550ebSKeerthy .core.pmic = &tps659038,
453b12550ebSKeerthy
454b12550ebSKeerthy .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
455b12550ebSKeerthy .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
456b12550ebSKeerthy .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
457b12550ebSKeerthy .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
458b12550ebSKeerthy .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
459b12550ebSKeerthy .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
460b12550ebSKeerthy .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
461b12550ebSKeerthy .iva.addr = TPS659038_REG_ADDR_SMPS45,
462b12550ebSKeerthy .iva.pmic = &tps659038,
463b12550ebSKeerthy .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
464b12550ebSKeerthy };
465b12550ebSKeerthy
get_voltrail_opp(int rail_offset)466beb71279SLokesh Vutla int get_voltrail_opp(int rail_offset)
467beb71279SLokesh Vutla {
468beb71279SLokesh Vutla int opp;
469beb71279SLokesh Vutla
470beb71279SLokesh Vutla switch (rail_offset) {
471beb71279SLokesh Vutla case VOLT_MPU:
472beb71279SLokesh Vutla opp = DRA7_MPU_OPP;
473beb71279SLokesh Vutla break;
474beb71279SLokesh Vutla case VOLT_CORE:
475beb71279SLokesh Vutla opp = DRA7_CORE_OPP;
476beb71279SLokesh Vutla break;
477beb71279SLokesh Vutla case VOLT_GPU:
478beb71279SLokesh Vutla opp = DRA7_GPU_OPP;
479beb71279SLokesh Vutla break;
480beb71279SLokesh Vutla case VOLT_EVE:
481beb71279SLokesh Vutla opp = DRA7_DSPEVE_OPP;
482beb71279SLokesh Vutla break;
483beb71279SLokesh Vutla case VOLT_IVA:
484beb71279SLokesh Vutla opp = DRA7_IVA_OPP;
485beb71279SLokesh Vutla break;
486beb71279SLokesh Vutla default:
487beb71279SLokesh Vutla opp = OPP_NOM;
488beb71279SLokesh Vutla }
489beb71279SLokesh Vutla
490beb71279SLokesh Vutla return opp;
491beb71279SLokesh Vutla }
492beb71279SLokesh Vutla
493beb71279SLokesh Vutla
494212f96f6SKipisz, Steven #ifdef CONFIG_SPL_BUILD
495212f96f6SKipisz, Steven /* No env to setup for SPL */
setup_board_eeprom_env(void)496212f96f6SKipisz, Steven static inline void setup_board_eeprom_env(void) { }
497212f96f6SKipisz, Steven
498212f96f6SKipisz, Steven /* Override function to read eeprom information */
do_board_detect(void)499212f96f6SKipisz, Steven void do_board_detect(void)
500212f96f6SKipisz, Steven {
501212f96f6SKipisz, Steven int rc;
502212f96f6SKipisz, Steven
503212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
504212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS);
505212f96f6SKipisz, Steven if (rc)
506212f96f6SKipisz, Steven printf("ti_i2c_eeprom_init failed %d\n", rc);
507212f96f6SKipisz, Steven }
508212f96f6SKipisz, Steven
509212f96f6SKipisz, Steven #else /* CONFIG_SPL_BUILD */
510212f96f6SKipisz, Steven
511212f96f6SKipisz, Steven /* Override function to read eeprom information: actual i2c read done by SPL*/
do_board_detect(void)512212f96f6SKipisz, Steven void do_board_detect(void)
513212f96f6SKipisz, Steven {
514212f96f6SKipisz, Steven char *bname = NULL;
515212f96f6SKipisz, Steven int rc;
516212f96f6SKipisz, Steven
517212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
518212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS);
519212f96f6SKipisz, Steven if (rc)
520212f96f6SKipisz, Steven printf("ti_i2c_eeprom_init failed %d\n", rc);
521212f96f6SKipisz, Steven
522212f96f6SKipisz, Steven if (board_is_x15())
523212f96f6SKipisz, Steven bname = "BeagleBoard X15";
524212f96f6SKipisz, Steven else if (board_is_am572x_evm())
525212f96f6SKipisz, Steven bname = "AM572x EVM";
5269646b95fSLokesh Vutla else if (board_is_am574x_idk())
5279646b95fSLokesh Vutla bname = "AM574x IDK";
528c020d355SSteve Kipisz else if (board_is_am572x_idk())
529c020d355SSteve Kipisz bname = "AM572x IDK";
5304d8397c6SSteve Kipisz else if (board_is_am571x_idk())
5314d8397c6SSteve Kipisz bname = "AM571x IDK";
532212f96f6SKipisz, Steven
533212f96f6SKipisz, Steven if (bname)
534212f96f6SKipisz, Steven snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
535212f96f6SKipisz, Steven "Board: %s REV %s\n", bname, board_ti_get_rev());
536212f96f6SKipisz, Steven }
537212f96f6SKipisz, Steven
setup_board_eeprom_env(void)538212f96f6SKipisz, Steven static void setup_board_eeprom_env(void)
539212f96f6SKipisz, Steven {
540212f96f6SKipisz, Steven char *name = "beagle_x15";
541212f96f6SKipisz, Steven int rc;
542212f96f6SKipisz, Steven
543212f96f6SKipisz, Steven rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
544212f96f6SKipisz, Steven CONFIG_EEPROM_CHIP_ADDRESS);
545212f96f6SKipisz, Steven if (rc)
546212f96f6SKipisz, Steven goto invalid_eeprom;
547212f96f6SKipisz, Steven
548bf43ce6cSNishanth Menon if (board_is_x15()) {
549f7f9f6beSLokesh Vutla if (board_is_x15_revb1())
550f7f9f6beSLokesh Vutla name = "beagle_x15_revb1";
551f70a4272SLokesh Vutla else if (board_is_x15_revc())
552f70a4272SLokesh Vutla name = "beagle_x15_revc";
553f7f9f6beSLokesh Vutla else
554c9891660SNishanth Menon name = "beagle_x15";
555bf43ce6cSNishanth Menon } else if (board_is_am572x_evm()) {
556bf43ce6cSNishanth Menon if (board_is_am572x_evm_reva3())
557bf43ce6cSNishanth Menon name = "am57xx_evm_reva3";
558212f96f6SKipisz, Steven else
559bf43ce6cSNishanth Menon name = "am57xx_evm";
5609646b95fSLokesh Vutla } else if (board_is_am574x_idk()) {
5619646b95fSLokesh Vutla name = "am574x_idk";
562bf43ce6cSNishanth Menon } else if (board_is_am572x_idk()) {
563bf43ce6cSNishanth Menon name = "am572x_idk";
5644d8397c6SSteve Kipisz } else if (board_is_am571x_idk()) {
5654d8397c6SSteve Kipisz name = "am571x_idk";
566bf43ce6cSNishanth Menon } else {
567212f96f6SKipisz, Steven printf("Unidentified board claims %s in eeprom header\n",
568212f96f6SKipisz, Steven board_ti_get_name());
569bf43ce6cSNishanth Menon }
570212f96f6SKipisz, Steven
571212f96f6SKipisz, Steven invalid_eeprom:
572212f96f6SKipisz, Steven set_board_info_env(name);
573212f96f6SKipisz, Steven }
574212f96f6SKipisz, Steven
575212f96f6SKipisz, Steven #endif /* CONFIG_SPL_BUILD */
576212f96f6SKipisz, Steven
vcores_init(void)577d60198daSKeerthy void vcores_init(void)
578d60198daSKeerthy {
57910f430f3SLokesh Vutla if (board_is_am572x_idk() || board_is_am574x_idk())
580d60198daSKeerthy *omap_vcores = &am572x_idk_volts;
581b12550ebSKeerthy else if (board_is_am571x_idk())
582b12550ebSKeerthy *omap_vcores = &am571x_idk_volts;
583d60198daSKeerthy else
584d60198daSKeerthy *omap_vcores = &beagle_x15_volts;
585d60198daSKeerthy }
586d60198daSKeerthy
hw_data_init(void)58774cc8b09SKipisz, Steven void hw_data_init(void)
58874cc8b09SKipisz, Steven {
58974cc8b09SKipisz, Steven *prcm = &dra7xx_prcm;
590209742faSSteve Kipisz if (is_dra72x())
591209742faSSteve Kipisz *dplls_data = &dra72x_dplls;
59210f430f3SLokesh Vutla else if (is_dra76x())
59310f430f3SLokesh Vutla *dplls_data = &dra76x_dplls;
594209742faSSteve Kipisz else
59574cc8b09SKipisz, Steven *dplls_data = &dra7xx_dplls;
59674cc8b09SKipisz, Steven *ctrl = &dra7xx_ctrl;
59774cc8b09SKipisz, Steven }
59874cc8b09SKipisz, Steven
am571x_idk_needs_lcd(void)59937611052SRoger Quadros bool am571x_idk_needs_lcd(void)
60037611052SRoger Quadros {
60137611052SRoger Quadros bool needs_lcd;
60237611052SRoger Quadros
60337611052SRoger Quadros gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
60437611052SRoger Quadros if (gpio_get_value(GPIO_ETH_LCD))
60537611052SRoger Quadros needs_lcd = false;
60637611052SRoger Quadros else
60737611052SRoger Quadros needs_lcd = true;
60837611052SRoger Quadros
60937611052SRoger Quadros gpio_free(GPIO_ETH_LCD);
61037611052SRoger Quadros
61137611052SRoger Quadros return needs_lcd;
61237611052SRoger Quadros }
61337611052SRoger Quadros
board_init(void)61474cc8b09SKipisz, Steven int board_init(void)
61574cc8b09SKipisz, Steven {
61674cc8b09SKipisz, Steven gpmc_init();
61774cc8b09SKipisz, Steven gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
61874cc8b09SKipisz, Steven
61974cc8b09SKipisz, Steven return 0;
62074cc8b09SKipisz, Steven }
62174cc8b09SKipisz, Steven
am57x_idk_lcd_detect(void)622fcb18524SNishanth Menon void am57x_idk_lcd_detect(void)
623fcb18524SNishanth Menon {
624fcb18524SNishanth Menon int r = -ENODEV;
625fcb18524SNishanth Menon char *idk_lcd = "no";
6267eb1f607SJean-Jacques Hiblot struct udevice *dev;
627fcb18524SNishanth Menon
628fcb18524SNishanth Menon /* Only valid for IDKs */
629fcb18524SNishanth Menon if (board_is_x15() || board_is_am572x_evm())
630fcb18524SNishanth Menon return;
631fcb18524SNishanth Menon
632fcb18524SNishanth Menon /* Only AM571x IDK has gpio control detect.. so check that */
633fcb18524SNishanth Menon if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
634fcb18524SNishanth Menon goto out;
635fcb18524SNishanth Menon
6361514244cSJean-Jacques Hiblot r = i2c_get_chip_for_busnum(OSD_TS_FT_BUS_ADDRESS,
6371514244cSJean-Jacques Hiblot OSD_TS_FT_CHIP_ADDRESS, 1, &dev);
638fcb18524SNishanth Menon if (r) {
6391514244cSJean-Jacques Hiblot printf("%s: Failed to get I2C device %d/%d (ret %d)\n",
6401514244cSJean-Jacques Hiblot __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
6411514244cSJean-Jacques Hiblot r);
642fcb18524SNishanth Menon /* AM572x IDK has no explicit settings for optional LCD kit */
6431514244cSJean-Jacques Hiblot if (board_is_am571x_idk())
644fcb18524SNishanth Menon printf("%s: Touch screen detect failed: %d!\n",
645fcb18524SNishanth Menon __func__, r);
646fcb18524SNishanth Menon goto out;
647fcb18524SNishanth Menon }
648fcb18524SNishanth Menon
649fcb18524SNishanth Menon /* Read FT ID */
6501514244cSJean-Jacques Hiblot r = dm_i2c_reg_read(dev, OSD_TS_FT_REG_ID);
6511514244cSJean-Jacques Hiblot if (r < 0) {
652fcb18524SNishanth Menon printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
653fcb18524SNishanth Menon __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
654fcb18524SNishanth Menon OSD_TS_FT_REG_ID, r);
655fcb18524SNishanth Menon goto out;
656fcb18524SNishanth Menon }
657fcb18524SNishanth Menon
6587eb1f607SJean-Jacques Hiblot switch (r) {
659fcb18524SNishanth Menon case OSD_TS_FT_ID_5606:
660fcb18524SNishanth Menon idk_lcd = "osd101t2045";
661fcb18524SNishanth Menon break;
662fcb18524SNishanth Menon case OSD_TS_FT_ID_5x46:
663fcb18524SNishanth Menon idk_lcd = "osd101t2587";
664fcb18524SNishanth Menon break;
665fcb18524SNishanth Menon default:
666fcb18524SNishanth Menon printf("%s: Unidentifed Touch screen ID 0x%02x\n",
6677eb1f607SJean-Jacques Hiblot __func__, r);
668fcb18524SNishanth Menon /* we will let default be "no lcd" */
669fcb18524SNishanth Menon }
670fcb18524SNishanth Menon out:
671382bee57SSimon Glass env_set("idk_lcd", idk_lcd);
672fcb18524SNishanth Menon return;
673fcb18524SNishanth Menon }
674fcb18524SNishanth Menon
675c3cd5fc8SVignesh R #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
device_okay(const char * path)676c3cd5fc8SVignesh R static int device_okay(const char *path)
677c3cd5fc8SVignesh R {
678c3cd5fc8SVignesh R int node;
679c3cd5fc8SVignesh R
680c3cd5fc8SVignesh R node = fdt_path_offset(gd->fdt_blob, path);
681c3cd5fc8SVignesh R if (node < 0)
682c3cd5fc8SVignesh R return 0;
683c3cd5fc8SVignesh R
684c3cd5fc8SVignesh R return fdtdec_get_is_enabled(gd->fdt_blob, node);
685c3cd5fc8SVignesh R }
686c3cd5fc8SVignesh R #endif
687c3cd5fc8SVignesh R
board_late_init(void)68874cc8b09SKipisz, Steven int board_late_init(void)
68974cc8b09SKipisz, Steven {
690212f96f6SKipisz, Steven setup_board_eeprom_env();
691385d3632SKeerthy u8 val;
692212f96f6SKipisz, Steven
69374cc8b09SKipisz, Steven /*
69474cc8b09SKipisz, Steven * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
69574cc8b09SKipisz, Steven * This is the POWERHOLD-in-Low behavior.
69674cc8b09SKipisz, Steven */
69774cc8b09SKipisz, Steven palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
69882cca5a6SLokesh Vutla
69982cca5a6SLokesh Vutla /*
70082cca5a6SLokesh Vutla * Default FIT boot on HS devices. Non FIT images are not allowed
70182cca5a6SLokesh Vutla * on HS devices.
70282cca5a6SLokesh Vutla */
70382cca5a6SLokesh Vutla if (get_device_type() == HS_DEVICE)
704382bee57SSimon Glass env_set("boot_fit", "1");
70582cca5a6SLokesh Vutla
706385d3632SKeerthy /*
707385d3632SKeerthy * Set the GPIO7 Pad to POWERHOLD. This has higher priority
708385d3632SKeerthy * over DEV_CTRL.DEV_ON bit. This can be reset in case of
709385d3632SKeerthy * PMIC Power off. So to be on the safer side set it back
710385d3632SKeerthy * to POWERHOLD mode irrespective of the current state.
711385d3632SKeerthy */
712385d3632SKeerthy palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
713385d3632SKeerthy &val);
714385d3632SKeerthy val = val | TPS65903X_PAD2_POWERHOLD_MASK;
715385d3632SKeerthy palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
716385d3632SKeerthy val);
717385d3632SKeerthy
7187a2af751SSemen Protsenko omap_die_id_serial();
7198bd29623SSemen Protsenko omap_set_fastboot_vars();
7207a2af751SSemen Protsenko
721fcb18524SNishanth Menon am57x_idk_lcd_detect();
72237611052SRoger Quadros
72337611052SRoger Quadros #if !defined(CONFIG_SPL_BUILD)
72437611052SRoger Quadros board_ti_set_ethaddr(2);
72537611052SRoger Quadros #endif
72637611052SRoger Quadros
727c3cd5fc8SVignesh R #if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
728c3cd5fc8SVignesh R if (device_okay("/ocp/omap_dwc3_1@48880000"))
729c3cd5fc8SVignesh R enable_usb_clocks(0);
730c3cd5fc8SVignesh R if (device_okay("/ocp/omap_dwc3_2@488c0000"))
731c3cd5fc8SVignesh R enable_usb_clocks(1);
732c3cd5fc8SVignesh R #endif
73374cc8b09SKipisz, Steven return 0;
73474cc8b09SKipisz, Steven }
73574cc8b09SKipisz, Steven
set_muxconf_regs(void)7363ef56e61SPaul Kocialkowski void set_muxconf_regs(void)
73774cc8b09SKipisz, Steven {
73874cc8b09SKipisz, Steven do_set_mux32((*ctrl)->control_padconf_core_base,
73974cc8b09SKipisz, Steven early_padconf, ARRAY_SIZE(early_padconf));
74074cc8b09SKipisz, Steven }
74174cc8b09SKipisz, Steven
74274cc8b09SKipisz, Steven #ifdef CONFIG_IODELAY_RECALIBRATION
recalibrate_iodelay(void)74374cc8b09SKipisz, Steven void recalibrate_iodelay(void)
74474cc8b09SKipisz, Steven {
745c020d355SSteve Kipisz const struct pad_conf_entry *pconf;
7462d7e9e9dSLokesh Vutla const struct iodelay_cfg_entry *iod, *delta_iod;
7472d7e9e9dSLokesh Vutla int pconf_sz, iod_sz, delta_iod_sz = 0;
74889a38953SNishanth Menon int ret;
749c020d355SSteve Kipisz
750443b0df3SLokesh Vutla if (board_is_am572x_idk()) {
751c020d355SSteve Kipisz pconf = core_padconf_array_essential_am572x_idk;
752c020d355SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
753c020d355SSteve Kipisz iod = iodelay_cfg_array_am572x_idk;
754c020d355SSteve Kipisz iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
755443b0df3SLokesh Vutla } else if (board_is_am574x_idk()) {
756443b0df3SLokesh Vutla pconf = core_padconf_array_essential_am574x_idk;
757443b0df3SLokesh Vutla pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
758443b0df3SLokesh Vutla iod = iodelay_cfg_array_am574x_idk;
759443b0df3SLokesh Vutla iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
7604d8397c6SSteve Kipisz } else if (board_is_am571x_idk()) {
7614d8397c6SSteve Kipisz pconf = core_padconf_array_essential_am571x_idk;
7624d8397c6SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
7634d8397c6SSteve Kipisz iod = iodelay_cfg_array_am571x_idk;
7644d8397c6SSteve Kipisz iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
765c020d355SSteve Kipisz } else {
766c020d355SSteve Kipisz /* Common for X15/GPEVM */
767c020d355SSteve Kipisz pconf = core_padconf_array_essential_x15;
768c020d355SSteve Kipisz pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
76989a38953SNishanth Menon /* There never was an SR1.0 X15.. So.. */
77089a38953SNishanth Menon if (omap_revision() == DRA752_ES1_1) {
77189a38953SNishanth Menon iod = iodelay_cfg_array_x15_sr1_1;
77289a38953SNishanth Menon iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
77389a38953SNishanth Menon } else {
77489a38953SNishanth Menon /* Since full production should switch to SR2.0 */
77589a38953SNishanth Menon iod = iodelay_cfg_array_x15_sr2_0;
77689a38953SNishanth Menon iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
77789a38953SNishanth Menon }
778c020d355SSteve Kipisz }
779c020d355SSteve Kipisz
78089a38953SNishanth Menon /* Setup I/O isolation */
78189a38953SNishanth Menon ret = __recalibrate_iodelay_start();
78289a38953SNishanth Menon if (ret)
78389a38953SNishanth Menon goto err;
78489a38953SNishanth Menon
78589a38953SNishanth Menon /* Do the muxing here */
78689a38953SNishanth Menon do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
78789a38953SNishanth Menon
78889a38953SNishanth Menon /* Now do the weird minor deltas that should be safe */
78989a38953SNishanth Menon if (board_is_x15() || board_is_am572x_evm()) {
790f70a4272SLokesh Vutla if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
791f70a4272SLokesh Vutla board_is_x15_revc()) {
79289a38953SNishanth Menon pconf = core_padconf_array_delta_x15_sr2_0;
79389a38953SNishanth Menon pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
79489a38953SNishanth Menon } else {
79589a38953SNishanth Menon pconf = core_padconf_array_delta_x15_sr1_1;
79689a38953SNishanth Menon pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
79789a38953SNishanth Menon }
79889a38953SNishanth Menon do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
79989a38953SNishanth Menon }
80089a38953SNishanth Menon
80137611052SRoger Quadros if (board_is_am571x_idk()) {
80237611052SRoger Quadros if (am571x_idk_needs_lcd()) {
80337611052SRoger Quadros pconf = core_padconf_array_vout_am571x_idk;
80437611052SRoger Quadros pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
8052d7e9e9dSLokesh Vutla delta_iod = iodelay_cfg_array_am571x_idk_4port;
8062d7e9e9dSLokesh Vutla delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
8072d7e9e9dSLokesh Vutla
80837611052SRoger Quadros } else {
80937611052SRoger Quadros pconf = core_padconf_array_icss1eth_am571x_idk;
81037611052SRoger Quadros pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
81137611052SRoger Quadros }
81237611052SRoger Quadros do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
81337611052SRoger Quadros }
81437611052SRoger Quadros
81589a38953SNishanth Menon /* Setup IOdelay configuration */
81689a38953SNishanth Menon ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
8172d7e9e9dSLokesh Vutla if (delta_iod_sz)
8182d7e9e9dSLokesh Vutla ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
8192d7e9e9dSLokesh Vutla delta_iod_sz);
8202d7e9e9dSLokesh Vutla
82189a38953SNishanth Menon err:
82289a38953SNishanth Menon /* Closeup.. remove isolation */
82389a38953SNishanth Menon __recalibrate_iodelay_end(ret);
82474cc8b09SKipisz, Steven }
82574cc8b09SKipisz, Steven #endif
82674cc8b09SKipisz, Steven
8274aa2ba3aSMasahiro Yamada #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)82874cc8b09SKipisz, Steven int board_mmc_init(bd_t *bis)
82974cc8b09SKipisz, Steven {
83074cc8b09SKipisz, Steven omap_mmc_init(0, 0, 0, -1, -1);
83174cc8b09SKipisz, Steven omap_mmc_init(1, 0, 0, -1, -1);
83274cc8b09SKipisz, Steven return 0;
83374cc8b09SKipisz, Steven }
834c413baa9SKishon Vijay Abraham I
835c413baa9SKishon Vijay Abraham I static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
836c413baa9SKishon Vijay Abraham I .hw_rev = "rev11",
837c413baa9SKishon Vijay Abraham I .unsupported_caps = MMC_CAP(MMC_HS_200) |
838c413baa9SKishon Vijay Abraham I MMC_CAP(UHS_SDR104),
839c413baa9SKishon Vijay Abraham I .max_freq = 96000000,
840c413baa9SKishon Vijay Abraham I };
841c413baa9SKishon Vijay Abraham I
842c413baa9SKishon Vijay Abraham I static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
843c413baa9SKishon Vijay Abraham I .hw_rev = "rev11",
844c413baa9SKishon Vijay Abraham I .unsupported_caps = MMC_CAP(MMC_HS_200) |
845c413baa9SKishon Vijay Abraham I MMC_CAP(UHS_SDR104) |
846c413baa9SKishon Vijay Abraham I MMC_CAP(UHS_SDR50),
847c413baa9SKishon Vijay Abraham I .max_freq = 48000000,
848c413baa9SKishon Vijay Abraham I };
849c413baa9SKishon Vijay Abraham I
platform_fixups_mmc(uint32_t addr)850c413baa9SKishon Vijay Abraham I const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
851c413baa9SKishon Vijay Abraham I {
852c413baa9SKishon Vijay Abraham I switch (omap_revision()) {
853c413baa9SKishon Vijay Abraham I case DRA752_ES1_0:
854c413baa9SKishon Vijay Abraham I case DRA752_ES1_1:
855c413baa9SKishon Vijay Abraham I if (addr == OMAP_HSMMC1_BASE)
856c413baa9SKishon Vijay Abraham I return &am57x_es1_1_mmc1_fixups;
857c413baa9SKishon Vijay Abraham I else
858c413baa9SKishon Vijay Abraham I return &am57x_es1_1_mmc23_fixups;
859c413baa9SKishon Vijay Abraham I default:
860c413baa9SKishon Vijay Abraham I return NULL;
861c413baa9SKishon Vijay Abraham I }
862c413baa9SKishon Vijay Abraham I }
86374cc8b09SKipisz, Steven #endif
86474cc8b09SKipisz, Steven
86574cc8b09SKipisz, Steven #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
spl_start_uboot(void)86674cc8b09SKipisz, Steven int spl_start_uboot(void)
86774cc8b09SKipisz, Steven {
86874cc8b09SKipisz, Steven /* break into full u-boot on 'c' */
86974cc8b09SKipisz, Steven if (serial_tstc() && serial_getc() == 'c')
87074cc8b09SKipisz, Steven return 1;
87174cc8b09SKipisz, Steven
87274cc8b09SKipisz, Steven #ifdef CONFIG_SPL_ENV_SUPPORT
87374cc8b09SKipisz, Steven env_init();
874310fb14bSSimon Glass env_load();
875bfebc8c9SSimon Glass if (env_get_yesno("boot_os") != 1)
87674cc8b09SKipisz, Steven return 1;
87774cc8b09SKipisz, Steven #endif
87874cc8b09SKipisz, Steven
87974cc8b09SKipisz, Steven return 0;
88074cc8b09SKipisz, Steven }
88174cc8b09SKipisz, Steven #endif
88274cc8b09SKipisz, Steven
88374cc8b09SKipisz, Steven #ifdef CONFIG_DRIVER_TI_CPSW
88474cc8b09SKipisz, Steven
88574cc8b09SKipisz, Steven /* Delay value to add to calibrated value */
88674cc8b09SKipisz, Steven #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
88774cc8b09SKipisz, Steven #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
88874cc8b09SKipisz, Steven #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
88974cc8b09SKipisz, Steven #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
89074cc8b09SKipisz, Steven #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
89174cc8b09SKipisz, Steven #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
89274cc8b09SKipisz, Steven #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
89374cc8b09SKipisz, Steven #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
89474cc8b09SKipisz, Steven #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
89574cc8b09SKipisz, Steven #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
89674cc8b09SKipisz, Steven
cpsw_control(int enabled)89774cc8b09SKipisz, Steven static void cpsw_control(int enabled)
89874cc8b09SKipisz, Steven {
89974cc8b09SKipisz, Steven /* VTP can be added here */
90074cc8b09SKipisz, Steven }
90174cc8b09SKipisz, Steven
90274cc8b09SKipisz, Steven static struct cpsw_slave_data cpsw_slaves[] = {
90374cc8b09SKipisz, Steven {
90474cc8b09SKipisz, Steven .slave_reg_ofs = 0x208,
90574cc8b09SKipisz, Steven .sliver_reg_ofs = 0xd80,
90674cc8b09SKipisz, Steven .phy_addr = 1,
90774cc8b09SKipisz, Steven },
90874cc8b09SKipisz, Steven {
90974cc8b09SKipisz, Steven .slave_reg_ofs = 0x308,
91074cc8b09SKipisz, Steven .sliver_reg_ofs = 0xdc0,
91174cc8b09SKipisz, Steven .phy_addr = 2,
91274cc8b09SKipisz, Steven },
91374cc8b09SKipisz, Steven };
91474cc8b09SKipisz, Steven
91574cc8b09SKipisz, Steven static struct cpsw_platform_data cpsw_data = {
91674cc8b09SKipisz, Steven .mdio_base = CPSW_MDIO_BASE,
91774cc8b09SKipisz, Steven .cpsw_base = CPSW_BASE,
91874cc8b09SKipisz, Steven .mdio_div = 0xff,
91974cc8b09SKipisz, Steven .channels = 8,
92074cc8b09SKipisz, Steven .cpdma_reg_ofs = 0x800,
92174cc8b09SKipisz, Steven .slaves = 1,
92274cc8b09SKipisz, Steven .slave_data = cpsw_slaves,
92374cc8b09SKipisz, Steven .ale_reg_ofs = 0xd00,
92474cc8b09SKipisz, Steven .ale_entries = 1024,
92574cc8b09SKipisz, Steven .host_port_reg_ofs = 0x108,
92674cc8b09SKipisz, Steven .hw_stats_reg_ofs = 0x900,
92774cc8b09SKipisz, Steven .bd_ram_ofs = 0x2000,
92874cc8b09SKipisz, Steven .mac_control = (1 << 5),
92974cc8b09SKipisz, Steven .control = cpsw_control,
93074cc8b09SKipisz, Steven .host_port_num = 0,
93174cc8b09SKipisz, Steven .version = CPSW_CTRL_VERSION_2,
93274cc8b09SKipisz, Steven };
93374cc8b09SKipisz, Steven
mac_to_u64(u8 mac[6])93492667e89SRoger Quadros static u64 mac_to_u64(u8 mac[6])
93592667e89SRoger Quadros {
93692667e89SRoger Quadros int i;
93792667e89SRoger Quadros u64 addr = 0;
93892667e89SRoger Quadros
93992667e89SRoger Quadros for (i = 0; i < 6; i++) {
94092667e89SRoger Quadros addr <<= 8;
94192667e89SRoger Quadros addr |= mac[i];
94292667e89SRoger Quadros }
94392667e89SRoger Quadros
94492667e89SRoger Quadros return addr;
94592667e89SRoger Quadros }
94692667e89SRoger Quadros
u64_to_mac(u64 addr,u8 mac[6])94792667e89SRoger Quadros static void u64_to_mac(u64 addr, u8 mac[6])
94892667e89SRoger Quadros {
94992667e89SRoger Quadros mac[5] = addr;
95092667e89SRoger Quadros mac[4] = addr >> 8;
95192667e89SRoger Quadros mac[3] = addr >> 16;
95292667e89SRoger Quadros mac[2] = addr >> 24;
95392667e89SRoger Quadros mac[1] = addr >> 32;
95492667e89SRoger Quadros mac[0] = addr >> 40;
95592667e89SRoger Quadros }
95692667e89SRoger Quadros
board_eth_init(bd_t * bis)95774cc8b09SKipisz, Steven int board_eth_init(bd_t *bis)
95874cc8b09SKipisz, Steven {
95974cc8b09SKipisz, Steven int ret;
96074cc8b09SKipisz, Steven uint8_t mac_addr[6];
96174cc8b09SKipisz, Steven uint32_t mac_hi, mac_lo;
96274cc8b09SKipisz, Steven uint32_t ctrl_val;
96392667e89SRoger Quadros int i;
96492667e89SRoger Quadros u64 mac1, mac2;
96592667e89SRoger Quadros u8 mac_addr1[6], mac_addr2[6];
96692667e89SRoger Quadros int num_macs;
96774cc8b09SKipisz, Steven
96874cc8b09SKipisz, Steven /* try reading mac address from efuse */
96974cc8b09SKipisz, Steven mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
97074cc8b09SKipisz, Steven mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
97174cc8b09SKipisz, Steven mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
97274cc8b09SKipisz, Steven mac_addr[1] = (mac_hi & 0xFF00) >> 8;
97374cc8b09SKipisz, Steven mac_addr[2] = mac_hi & 0xFF;
97474cc8b09SKipisz, Steven mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
97574cc8b09SKipisz, Steven mac_addr[4] = (mac_lo & 0xFF00) >> 8;
97674cc8b09SKipisz, Steven mac_addr[5] = mac_lo & 0xFF;
97774cc8b09SKipisz, Steven
97800caae6dSSimon Glass if (!env_get("ethaddr")) {
97974cc8b09SKipisz, Steven printf("<ethaddr> not set. Validating first E-fuse MAC\n");
98074cc8b09SKipisz, Steven
98174cc8b09SKipisz, Steven if (is_valid_ethaddr(mac_addr))
982fd1e959eSSimon Glass eth_env_set_enetaddr("ethaddr", mac_addr);
98374cc8b09SKipisz, Steven }
98474cc8b09SKipisz, Steven
98574cc8b09SKipisz, Steven mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
98674cc8b09SKipisz, Steven mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
98774cc8b09SKipisz, Steven mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
98874cc8b09SKipisz, Steven mac_addr[1] = (mac_hi & 0xFF00) >> 8;
98974cc8b09SKipisz, Steven mac_addr[2] = mac_hi & 0xFF;
99074cc8b09SKipisz, Steven mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
99174cc8b09SKipisz, Steven mac_addr[4] = (mac_lo & 0xFF00) >> 8;
99274cc8b09SKipisz, Steven mac_addr[5] = mac_lo & 0xFF;
99374cc8b09SKipisz, Steven
99400caae6dSSimon Glass if (!env_get("eth1addr")) {
99574cc8b09SKipisz, Steven if (is_valid_ethaddr(mac_addr))
996fd1e959eSSimon Glass eth_env_set_enetaddr("eth1addr", mac_addr);
99774cc8b09SKipisz, Steven }
99874cc8b09SKipisz, Steven
99974cc8b09SKipisz, Steven ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
100074cc8b09SKipisz, Steven ctrl_val |= 0x22;
100174cc8b09SKipisz, Steven writel(ctrl_val, (*ctrl)->control_core_control_io1);
100274cc8b09SKipisz, Steven
10034d8397c6SSteve Kipisz /* The phy address for the AM57xx IDK are different than x15 */
100410f430f3SLokesh Vutla if (board_is_am572x_idk() || board_is_am571x_idk() ||
100510f430f3SLokesh Vutla board_is_am574x_idk()) {
1006c020d355SSteve Kipisz cpsw_data.slave_data[0].phy_addr = 0;
1007c020d355SSteve Kipisz cpsw_data.slave_data[1].phy_addr = 1;
1008c020d355SSteve Kipisz }
1009c020d355SSteve Kipisz
101074cc8b09SKipisz, Steven ret = cpsw_register(&cpsw_data);
101174cc8b09SKipisz, Steven if (ret < 0)
101274cc8b09SKipisz, Steven printf("Error %d registering CPSW switch\n", ret);
101374cc8b09SKipisz, Steven
101492667e89SRoger Quadros /*
101592667e89SRoger Quadros * Export any Ethernet MAC addresses from EEPROM.
101692667e89SRoger Quadros * On AM57xx the 2 MAC addresses define the address range
101792667e89SRoger Quadros */
101892667e89SRoger Quadros board_ti_get_eth_mac_addr(0, mac_addr1);
101992667e89SRoger Quadros board_ti_get_eth_mac_addr(1, mac_addr2);
102092667e89SRoger Quadros
102192667e89SRoger Quadros if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
102292667e89SRoger Quadros mac1 = mac_to_u64(mac_addr1);
102392667e89SRoger Quadros mac2 = mac_to_u64(mac_addr2);
102492667e89SRoger Quadros
102592667e89SRoger Quadros /* must contain an address range */
102692667e89SRoger Quadros num_macs = mac2 - mac1 + 1;
102792667e89SRoger Quadros /* <= 50 to protect against user programming error */
102892667e89SRoger Quadros if (num_macs > 0 && num_macs <= 50) {
102992667e89SRoger Quadros for (i = 0; i < num_macs; i++) {
103092667e89SRoger Quadros u64_to_mac(mac1 + i, mac_addr);
103192667e89SRoger Quadros if (is_valid_ethaddr(mac_addr)) {
1032fd1e959eSSimon Glass eth_env_set_enetaddr_by_index("eth",
103392667e89SRoger Quadros i + 2,
103492667e89SRoger Quadros mac_addr);
103592667e89SRoger Quadros }
103692667e89SRoger Quadros }
103792667e89SRoger Quadros }
103892667e89SRoger Quadros }
103992667e89SRoger Quadros
104074cc8b09SKipisz, Steven return ret;
104174cc8b09SKipisz, Steven }
104274cc8b09SKipisz, Steven #endif
104374cc8b09SKipisz, Steven
104474cc8b09SKipisz, Steven #ifdef CONFIG_BOARD_EARLY_INIT_F
104574cc8b09SKipisz, Steven /* VTT regulator enable */
vtt_regulator_enable(void)104674cc8b09SKipisz, Steven static inline void vtt_regulator_enable(void)
104774cc8b09SKipisz, Steven {
104874cc8b09SKipisz, Steven if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
104974cc8b09SKipisz, Steven return;
105074cc8b09SKipisz, Steven
105174cc8b09SKipisz, Steven gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
105274cc8b09SKipisz, Steven gpio_direction_output(GPIO_DDR_VTT_EN, 1);
105374cc8b09SKipisz, Steven }
105474cc8b09SKipisz, Steven
board_early_init_f(void)105574cc8b09SKipisz, Steven int board_early_init_f(void)
105674cc8b09SKipisz, Steven {
105774cc8b09SKipisz, Steven vtt_regulator_enable();
105874cc8b09SKipisz, Steven return 0;
105974cc8b09SKipisz, Steven }
106074cc8b09SKipisz, Steven #endif
106162a09f05SDaniel Allred
106262a09f05SDaniel Allred #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)106362a09f05SDaniel Allred int ft_board_setup(void *blob, bd_t *bd)
106462a09f05SDaniel Allred {
106562a09f05SDaniel Allred ft_cpu_setup(blob, bd);
106662a09f05SDaniel Allred
106762a09f05SDaniel Allred return 0;
106862a09f05SDaniel Allred }
106962a09f05SDaniel Allred #endif
10707a0ea589SLokesh Vutla
10717a0ea589SLokesh Vutla #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)10727a0ea589SLokesh Vutla int board_fit_config_name_match(const char *name)
10737a0ea589SLokesh Vutla {
1074f7f9f6beSLokesh Vutla if (board_is_x15()) {
1075f7f9f6beSLokesh Vutla if (board_is_x15_revb1()) {
1076f7f9f6beSLokesh Vutla if (!strcmp(name, "am57xx-beagle-x15-revb1"))
10777a0ea589SLokesh Vutla return 0;
10788b2551a4SLokesh Vutla } else if (board_is_x15_revc()) {
10798b2551a4SLokesh Vutla if (!strcmp(name, "am57xx-beagle-x15-revc"))
10808b2551a4SLokesh Vutla return 0;
1081f7f9f6beSLokesh Vutla } else if (!strcmp(name, "am57xx-beagle-x15")) {
10827a0ea589SLokesh Vutla return 0;
1083f7f9f6beSLokesh Vutla }
1084f7f9f6beSLokesh Vutla } else if (board_is_am572x_evm() &&
1085f7f9f6beSLokesh Vutla !strcmp(name, "am57xx-beagle-x15")) {
1086332dddc6SSchuyler Patton return 0;
1087f7f9f6beSLokesh Vutla } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
1088f7f9f6beSLokesh Vutla return 0;
1089b4185e4fSLokesh Vutla } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1090b4185e4fSLokesh Vutla return 0;
109145e7f7e7SSchuyler Patton } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
109245e7f7e7SSchuyler Patton return 0;
1093f7f9f6beSLokesh Vutla }
1094f7f9f6beSLokesh Vutla
10957a0ea589SLokesh Vutla return -1;
10967a0ea589SLokesh Vutla }
10977a0ea589SLokesh Vutla #endif
109817c29873SAndreas Dannenberg
109950580a0eSAndrew F. Davis #if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
fastboot_set_reboot_flag(void)110050580a0eSAndrew F. Davis int fastboot_set_reboot_flag(void)
110150580a0eSAndrew F. Davis {
110250580a0eSAndrew F. Davis printf("Setting reboot to fastboot flag ...\n");
110350580a0eSAndrew F. Davis env_set("dofastboot", "1");
110450580a0eSAndrew F. Davis env_save();
110550580a0eSAndrew F. Davis return 0;
110650580a0eSAndrew F. Davis }
110750580a0eSAndrew F. Davis #endif
110850580a0eSAndrew F. Davis
110917c29873SAndreas Dannenberg #ifdef CONFIG_TI_SECURE_DEVICE
board_fit_image_post_process(const void * fit,int node,void ** p_image,size_t * p_size)1110*b7d9107fSChia-Wei Wang void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size)
111117c29873SAndreas Dannenberg {
111217c29873SAndreas Dannenberg secure_boot_verify_image(p_image, p_size);
111317c29873SAndreas Dannenberg }
11141b597adaSAndrew F. Davis
board_tee_image_process(ulong tee_image,size_t tee_size)11151b597adaSAndrew F. Davis void board_tee_image_process(ulong tee_image, size_t tee_size)
11161b597adaSAndrew F. Davis {
11171b597adaSAndrew F. Davis secure_tee_install((u32)tee_image);
11181b597adaSAndrew F. Davis }
11191b597adaSAndrew F. Davis
11201b597adaSAndrew F. Davis U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
112117c29873SAndreas Dannenberg #endif
1122