1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2076446f1SDmitry Lifshitz /*
3076446f1SDmitry Lifshitz * SPL specific code for Compulab CM-T54 board
4076446f1SDmitry Lifshitz *
5076446f1SDmitry Lifshitz * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
6076446f1SDmitry Lifshitz *
7076446f1SDmitry Lifshitz * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
8076446f1SDmitry Lifshitz */
9076446f1SDmitry Lifshitz
10076446f1SDmitry Lifshitz #include <asm/emif.h>
11076446f1SDmitry Lifshitz
12076446f1SDmitry Lifshitz const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
13076446f1SDmitry Lifshitz #if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
14076446f1SDmitry Lifshitz .sdram_config_init = 0x618522B2,
15076446f1SDmitry Lifshitz .sdram_config = 0x618522B2,
16076446f1SDmitry Lifshitz #elif defined(CONFIG_DRAM_2G)
17076446f1SDmitry Lifshitz .sdram_config_init = 0x618522BA,
18076446f1SDmitry Lifshitz .sdram_config = 0x618522BA,
19076446f1SDmitry Lifshitz #endif
20076446f1SDmitry Lifshitz .sdram_config2 = 0x0,
21076446f1SDmitry Lifshitz .ref_ctrl = 0x00001040,
22076446f1SDmitry Lifshitz .sdram_tim1 = 0xEEEF36F3,
23076446f1SDmitry Lifshitz .sdram_tim2 = 0x348F7FDA,
24076446f1SDmitry Lifshitz .sdram_tim3 = 0x027F88A8,
25076446f1SDmitry Lifshitz .read_idle_ctrl = 0x00050000,
26076446f1SDmitry Lifshitz .zq_config = 0x1007190B,
27076446f1SDmitry Lifshitz .temp_alert_config = 0x00000000,
28076446f1SDmitry Lifshitz
29076446f1SDmitry Lifshitz .emif_ddr_phy_ctlr_1_init = 0x0030400B,
30076446f1SDmitry Lifshitz .emif_ddr_phy_ctlr_1 = 0x0034400B,
31076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
32076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
33076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
34076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
35076446f1SDmitry Lifshitz .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
36076446f1SDmitry Lifshitz .emif_rd_wr_lvl_rmp_win = 0x00000000,
37076446f1SDmitry Lifshitz .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
38076446f1SDmitry Lifshitz .emif_rd_wr_lvl_ctl = 0x00000000,
39076446f1SDmitry Lifshitz .emif_rd_wr_exec_thresh = 0x40000305,
40076446f1SDmitry Lifshitz };
41076446f1SDmitry Lifshitz
42076446f1SDmitry Lifshitz const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
43076446f1SDmitry Lifshitz .dmm_lisa_map_0 = 0x0,
44076446f1SDmitry Lifshitz .dmm_lisa_map_1 = 0x0,
45076446f1SDmitry Lifshitz
46076446f1SDmitry Lifshitz #ifdef CONFIG_DRAM_2G
47076446f1SDmitry Lifshitz .dmm_lisa_map_2 = 0x80740300,
48076446f1SDmitry Lifshitz #elif defined(CONFIG_DRAM_1G)
49076446f1SDmitry Lifshitz .dmm_lisa_map_2 = 0x80640300,
50076446f1SDmitry Lifshitz #elif defined(CONFIG_DRAM_512M)
51076446f1SDmitry Lifshitz .dmm_lisa_map_2 = 0x80500100,
52076446f1SDmitry Lifshitz #endif
53076446f1SDmitry Lifshitz .dmm_lisa_map_3 = 0x00000000,
54076446f1SDmitry Lifshitz .is_ma_present = 0x1,
55076446f1SDmitry Lifshitz };
56076446f1SDmitry Lifshitz
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)57076446f1SDmitry Lifshitz void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
58076446f1SDmitry Lifshitz {
59076446f1SDmitry Lifshitz *regs = &emif_regs_ddr3_532_mhz_cm_t54;
60076446f1SDmitry Lifshitz }
61076446f1SDmitry Lifshitz
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)62076446f1SDmitry Lifshitz void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
63076446f1SDmitry Lifshitz {
64076446f1SDmitry Lifshitz *dmm_lisa_regs = &lisa_map_cm_t54;
65076446f1SDmitry Lifshitz }
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