1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
285ab0452SFelix Brack /*
385ab0452SFelix Brack * board.c
485ab0452SFelix Brack *
585ab0452SFelix Brack * Board functions for EETS PDU001 board
685ab0452SFelix Brack *
785ab0452SFelix Brack * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
885ab0452SFelix Brack *
985ab0452SFelix Brack * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
1085ab0452SFelix Brack */
1185ab0452SFelix Brack
1285ab0452SFelix Brack #include <common.h>
1385ab0452SFelix Brack #include <errno.h>
1485ab0452SFelix Brack #include <spl.h>
1585ab0452SFelix Brack #include <i2c.h>
1685ab0452SFelix Brack #include <environment.h>
1785ab0452SFelix Brack #include <watchdog.h>
1885ab0452SFelix Brack #include <debug_uart.h>
1985ab0452SFelix Brack #include <dm/ofnode.h>
2085ab0452SFelix Brack #include <power/pmic.h>
2185ab0452SFelix Brack #include <power/regulator.h>
2285ab0452SFelix Brack #include <asm/arch/cpu.h>
2385ab0452SFelix Brack #include <asm/arch/hardware.h>
2485ab0452SFelix Brack #include <asm/arch/omap.h>
2585ab0452SFelix Brack #include <asm/arch/ddr_defs.h>
2685ab0452SFelix Brack #include <asm/arch/clock.h>
2785ab0452SFelix Brack #include <asm/arch/gpio.h>
2885ab0452SFelix Brack #include <asm/arch/mmc_host_def.h>
2985ab0452SFelix Brack #include <asm/arch/sys_proto.h>
3085ab0452SFelix Brack #include <asm/arch/mem.h>
3185ab0452SFelix Brack #include <asm/io.h>
3285ab0452SFelix Brack #include <asm/emif.h>
3385ab0452SFelix Brack #include <asm/gpio.h>
3485ab0452SFelix Brack #include "board.h"
3585ab0452SFelix Brack
3685ab0452SFelix Brack DECLARE_GLOBAL_DATA_PTR;
3785ab0452SFelix Brack
3885ab0452SFelix Brack #define I2C_ADDR_NODE_ID 0x50
3985ab0452SFelix Brack #define I2C_REG_NODE_ID_BASE 0xfa
4085ab0452SFelix Brack #define NODE_ID_BYTE_COUNT 6
4185ab0452SFelix Brack
4285ab0452SFelix Brack #define I2C_ADDR_LEDS 0x60
4385ab0452SFelix Brack #define I2C_REG_RUN_LED 0x06
4485ab0452SFelix Brack #define RUN_LED_OFF 0x0
4585ab0452SFelix Brack #define RUN_LED_RED 0x1
4685ab0452SFelix Brack #define RUN_LED_GREEN (0x1 << 2)
4785ab0452SFelix Brack
4885ab0452SFelix Brack #define VDD_MPU_REGULATOR "regulator@2"
4985ab0452SFelix Brack #define VDD_CORE_REGULATOR "regulator@3"
5085ab0452SFelix Brack #define DEFAULT_CORE_VOLTAGE 1137500
5185ab0452SFelix Brack
5285ab0452SFelix Brack /*
5385ab0452SFelix Brack * boot device save register
5485ab0452SFelix Brack * -------------------------
5585ab0452SFelix Brack * The boot device can be quired by 'spl_boot_device()' in
5685ab0452SFelix Brack * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
5785ab0452SFelix Brack * environment here. In turn 'spl_boot_device' can't be called in
5885ab0452SFelix Brack * 'board_late_init' which allows writing to u-boot environment.
5985ab0452SFelix Brack * To get the boot device from 'am33xx_spl_board_init' to
6085ab0452SFelix Brack * 'board_late_init' we therefore use a scratch register from the RTC.
6185ab0452SFelix Brack */
6285ab0452SFelix Brack #define CONFIG_SYS_RTC_SCRATCH0 0x60
6385ab0452SFelix Brack #define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
6485ab0452SFelix Brack
6585ab0452SFelix Brack #ifdef CONFIG_SPL_BUILD
save_boot_device(void)6685ab0452SFelix Brack static void save_boot_device(void)
6785ab0452SFelix Brack {
6885ab0452SFelix Brack *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
6985ab0452SFelix Brack }
7085ab0452SFelix Brack #endif
7185ab0452SFelix Brack
boot_device(void)7285ab0452SFelix Brack u32 boot_device(void)
7385ab0452SFelix Brack {
7485ab0452SFelix Brack return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
7585ab0452SFelix Brack }
7685ab0452SFelix Brack
7785ab0452SFelix Brack /* Store the boot device in the environment variable 'boot_device' */
env_set_boot_device(void)7885ab0452SFelix Brack static void env_set_boot_device(void)
7985ab0452SFelix Brack {
8085ab0452SFelix Brack switch (boot_device()) {
8185ab0452SFelix Brack case BOOT_DEVICE_MMC1: {
8285ab0452SFelix Brack env_set("boot_device", "emmc");
8385ab0452SFelix Brack break;
8485ab0452SFelix Brack }
8585ab0452SFelix Brack case BOOT_DEVICE_MMC2: {
8685ab0452SFelix Brack env_set("boot_device", "sdcard");
8785ab0452SFelix Brack break;
8885ab0452SFelix Brack }
8985ab0452SFelix Brack default: {
9085ab0452SFelix Brack env_set("boot_device", "unknown");
9185ab0452SFelix Brack break;
9285ab0452SFelix Brack }
9385ab0452SFelix Brack }
9485ab0452SFelix Brack }
9585ab0452SFelix Brack
set_run_led(struct udevice * dev)9685ab0452SFelix Brack static void set_run_led(struct udevice *dev)
9785ab0452SFelix Brack {
9885ab0452SFelix Brack int val = RUN_LED_OFF;
9985ab0452SFelix Brack
10085ab0452SFelix Brack if (IS_ENABLED(CONFIG_RUN_LED_RED))
10185ab0452SFelix Brack val = RUN_LED_RED;
10285ab0452SFelix Brack else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
10385ab0452SFelix Brack val = RUN_LED_GREEN;
10485ab0452SFelix Brack
10585ab0452SFelix Brack dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
10685ab0452SFelix Brack }
10785ab0452SFelix Brack
10885ab0452SFelix Brack /* Set 'serial#' to the EUI-48 value of board node ID chip */
env_set_serial(struct udevice * dev)10985ab0452SFelix Brack static void env_set_serial(struct udevice *dev)
11085ab0452SFelix Brack {
11185ab0452SFelix Brack int val;
11285ab0452SFelix Brack char serial[2 * NODE_ID_BYTE_COUNT + 1];
11385ab0452SFelix Brack int n;
11485ab0452SFelix Brack
11585ab0452SFelix Brack for (n = 0; n < sizeof(serial); n += 2) {
11685ab0452SFelix Brack val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
11785ab0452SFelix Brack sprintf(serial + n, "%02X", val);
11885ab0452SFelix Brack }
11985ab0452SFelix Brack serial[2 * NODE_ID_BYTE_COUNT] = '\0';
12085ab0452SFelix Brack env_set("serial#", serial);
12185ab0452SFelix Brack }
12285ab0452SFelix Brack
set_mpu_and_core_voltage(void)12385ab0452SFelix Brack static void set_mpu_and_core_voltage(void)
12485ab0452SFelix Brack {
12585ab0452SFelix Brack int mpu_vdd;
12685ab0452SFelix Brack int sil_rev;
12785ab0452SFelix Brack struct udevice *dev;
12885ab0452SFelix Brack struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
12985ab0452SFelix Brack
13085ab0452SFelix Brack /*
13185ab0452SFelix Brack * The PDU001 (more precisely the computing module m2) uses a
13285ab0452SFelix Brack * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
13385ab0452SFelix Brack * voltage of 1.1375V. For MPU voltage we need to switch based on
13485ab0452SFelix Brack * the frequency we are running at.
13585ab0452SFelix Brack */
13685ab0452SFelix Brack
13785ab0452SFelix Brack /*
13885ab0452SFelix Brack * Depending on MPU clock and PG we will need a different VDD
13985ab0452SFelix Brack * to drive at that speed.
14085ab0452SFelix Brack */
14185ab0452SFelix Brack sil_rev = readl(&cdev->deviceid) >> 28;
14285ab0452SFelix Brack mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
14385ab0452SFelix Brack
14485ab0452SFelix Brack /* first update the MPU voltage */
14585ab0452SFelix Brack if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
14685ab0452SFelix Brack if (regulator_set_value(dev, mpu_vdd))
14785ab0452SFelix Brack debug("failed to set MPU voltage\n");
14885ab0452SFelix Brack } else {
14985ab0452SFelix Brack debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
15085ab0452SFelix Brack }
15185ab0452SFelix Brack
15285ab0452SFelix Brack /* second update the CORE voltage */
15385ab0452SFelix Brack if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
15485ab0452SFelix Brack if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
15585ab0452SFelix Brack debug("failed to set CORE voltage\n");
15685ab0452SFelix Brack } else {
15785ab0452SFelix Brack debug("invalid CORE voltage ragulator %s\n",
15885ab0452SFelix Brack VDD_CORE_REGULATOR);
15985ab0452SFelix Brack }
16085ab0452SFelix Brack }
16185ab0452SFelix Brack
16285ab0452SFelix Brack #ifndef CONFIG_SKIP_LOWLEVEL_INIT
16385ab0452SFelix Brack static const struct ddr_data ddr2_data = {
16485ab0452SFelix Brack .datardsratio0 = MT47H128M16RT25E_RD_DQS,
16585ab0452SFelix Brack .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
16685ab0452SFelix Brack .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
16785ab0452SFelix Brack };
16885ab0452SFelix Brack
16985ab0452SFelix Brack static const struct cmd_control ddr2_cmd_ctrl_data = {
17085ab0452SFelix Brack .cmd0csratio = MT47H128M16RT25E_RATIO,
17185ab0452SFelix Brack .cmd1csratio = MT47H128M16RT25E_RATIO,
17285ab0452SFelix Brack .cmd2csratio = MT47H128M16RT25E_RATIO,
17385ab0452SFelix Brack };
17485ab0452SFelix Brack
17585ab0452SFelix Brack static const struct emif_regs ddr2_emif_reg_data = {
17685ab0452SFelix Brack .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
17785ab0452SFelix Brack .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
17885ab0452SFelix Brack .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
17985ab0452SFelix Brack .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
18085ab0452SFelix Brack .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
18185ab0452SFelix Brack .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
18285ab0452SFelix Brack };
18385ab0452SFelix Brack
18485ab0452SFelix Brack #define OSC (V_OSCK / 1000000)
18585ab0452SFelix Brack const struct dpll_params dpll_ddr = {
18685ab0452SFelix Brack 266, OSC - 1, 1, -1, -1, -1, -1};
18785ab0452SFelix Brack const struct dpll_params dpll_ddr_evm_sk = {
18885ab0452SFelix Brack 303, OSC - 1, 1, -1, -1, -1, -1};
18985ab0452SFelix Brack const struct dpll_params dpll_ddr_bone_black = {
19085ab0452SFelix Brack 400, OSC - 1, 1, -1, -1, -1, -1};
19185ab0452SFelix Brack
am33xx_spl_board_init(void)19285ab0452SFelix Brack void am33xx_spl_board_init(void)
19385ab0452SFelix Brack {
19485ab0452SFelix Brack struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
19585ab0452SFelix Brack
19685ab0452SFelix Brack /* Get the frequency */
19785ab0452SFelix Brack dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
19885ab0452SFelix Brack
19985ab0452SFelix Brack /* Set CORE Frequencies to OPP100 */
20085ab0452SFelix Brack do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
20185ab0452SFelix Brack
20285ab0452SFelix Brack /* Set MPU Frequency to what we detected now that voltages are set */
20385ab0452SFelix Brack do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
20485ab0452SFelix Brack
20585ab0452SFelix Brack /* save boot device for later use by 'board_late_init' */
20685ab0452SFelix Brack save_boot_device();
20785ab0452SFelix Brack }
20885ab0452SFelix Brack
get_dpll_ddr_params(void)20985ab0452SFelix Brack const struct dpll_params *get_dpll_ddr_params(void)
21085ab0452SFelix Brack {
21185ab0452SFelix Brack enable_i2c0_pin_mux();
21285ab0452SFelix Brack
21385ab0452SFelix Brack return &dpll_ddr;
21485ab0452SFelix Brack }
21585ab0452SFelix Brack
set_mux_conf_regs(void)21685ab0452SFelix Brack void set_mux_conf_regs(void)
21785ab0452SFelix Brack {
21885ab0452SFelix Brack /* done first by the ROM and afterwards by the pin controller driver */
21985ab0452SFelix Brack enable_i2c0_pin_mux();
22085ab0452SFelix Brack }
22185ab0452SFelix Brack
22285ab0452SFelix Brack const struct ctrl_ioregs ioregs = {
22385ab0452SFelix Brack .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
22485ab0452SFelix Brack .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
22585ab0452SFelix Brack .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
22685ab0452SFelix Brack .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
22785ab0452SFelix Brack .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
22885ab0452SFelix Brack };
22985ab0452SFelix Brack
sdram_init(void)23085ab0452SFelix Brack void sdram_init(void)
23185ab0452SFelix Brack {
23285ab0452SFelix Brack config_ddr(266, &ioregs, &ddr2_data,
23385ab0452SFelix Brack &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
23485ab0452SFelix Brack }
23585ab0452SFelix Brack #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
23685ab0452SFelix Brack
23785ab0452SFelix Brack #ifdef CONFIG_DEBUG_UART
board_debug_uart_init(void)23885ab0452SFelix Brack void board_debug_uart_init(void)
23985ab0452SFelix Brack {
24085ab0452SFelix Brack /* done by pin controller driver if not debugging */
24185ab0452SFelix Brack enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
24285ab0452SFelix Brack }
24385ab0452SFelix Brack #endif
24485ab0452SFelix Brack
24585ab0452SFelix Brack /*
24685ab0452SFelix Brack * Basic board specific setup. Pinmux has been handled already.
24785ab0452SFelix Brack */
board_init(void)24885ab0452SFelix Brack int board_init(void)
24985ab0452SFelix Brack {
25085ab0452SFelix Brack #ifdef CONFIG_HW_WATCHDOG
25185ab0452SFelix Brack hw_watchdog_init();
25285ab0452SFelix Brack #endif
25385ab0452SFelix Brack
25485ab0452SFelix Brack gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
25585ab0452SFelix Brack return 0;
25685ab0452SFelix Brack }
25785ab0452SFelix Brack
25885ab0452SFelix Brack #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)25985ab0452SFelix Brack int board_late_init(void)
26085ab0452SFelix Brack {
26185ab0452SFelix Brack struct udevice *dev;
26285ab0452SFelix Brack
26385ab0452SFelix Brack set_mpu_and_core_voltage();
26485ab0452SFelix Brack env_set_boot_device();
26585ab0452SFelix Brack
26685ab0452SFelix Brack /* second I2C bus connects to node ID and front panel LED chip */
26785ab0452SFelix Brack if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
26885ab0452SFelix Brack set_run_led(dev);
26985ab0452SFelix Brack if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
27085ab0452SFelix Brack env_set_serial(dev);
27185ab0452SFelix Brack
27285ab0452SFelix Brack return 0;
27385ab0452SFelix Brack }
27485ab0452SFelix Brack #endif
275