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Searched refs:readl (Results 1 – 25 of 1058) sorted by relevance

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/openbmc/qemu/tests/qtest/
H A Dcmsdk-apb-watchdog-test.c89 g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0); in test_watchdog()
96 g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0); in test_watchdog()
97 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 500); in test_watchdog()
101 g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 1); in test_watchdog()
102 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 0); in test_watchdog()
106 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1000); in test_watchdog()
110 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 500); in test_watchdog()
111 g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 1); in test_watchdog()
113 g_assert_cmpuint(readl(wdog_base + WDOGVALUE), ==, 1000); in test_watchdog()
114 g_assert_cmpuint(readl(wdog_base + WDOGRIS), ==, 0); in test_watchdog()
[all …]
H A Dsse-timer-test.c86 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 0); in test_counter()
87 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0); in test_counter()
91 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 100); in test_counter()
92 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0); in test_counter()
98 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_LO), ==, 110); in test_counter()
99 g_assert_cmpuint(readl(COUNTER_BASE + CNTCV_HI), ==, 0); in test_counter()
118 g_assert_cmpuint(readl(TIMER_BASE + CNTP_CTL), ==, 0); in test_timer()
119 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 0); in test_timer()
120 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_HI), ==, 0); in test_timer()
127 g_assert_cmpuint(readl(TIMER_BASE + CNTPCT_LO), ==, 100); in test_timer()
[all …]
H A Dnpcm7xx_gpio-test.c58 if (readl(GPIO(n) + GP_N_TLOCK1) != 0) { in gpio_unlock()
90 g_assert_cmphex(readl(GPIO(0) + GP_N_DOUT), ==, 0x12345678); in test_dout_to_din()
91 g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x12345678); in test_dout_to_din()
108 g_assert_cmphex(readl(GPIO(0) + GP_N_PU), ==, 0x23456789); in test_pullup_pulldown()
109 g_assert_cmphex(readl(GPIO(0) + GP_N_PD), ==, ~0x23456789U); in test_pullup_pulldown()
110 g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x23456789); in test_pullup_pulldown()
125 g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x3456789a); in test_output_enable()
126 g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x3456789a); in test_output_enable()
129 g_assert_cmphex(readl(GPIO(0) + GP_N_OE), ==, 0x34547898); in test_output_enable()
130 g_assert_cmphex(readl(GPIO(0) + GP_N_DIN), ==, 0x34547898); in test_output_enable()
[all …]
H A Dcmsdk-apb-dualtimer-test.c50 g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); in test_dualtimer()
59 g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); in test_dualtimer()
60 g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); in test_dualtimer()
64 g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); in test_dualtimer()
65 g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); in test_dualtimer()
72 g_assert_cmphex(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); in test_dualtimer()
76 g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); in test_dualtimer()
84 g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); in test_prescale()
94 g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); in test_prescale()
95 g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); in test_prescale()
[all …]
/openbmc/u-boot/arch/arm/cpu/pxa/
H A Dusb.c20 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); in usb_cpu_init()
25 writel(readl(CKEN) | CKEN10_USBHOST, CKEN); in usb_cpu_init()
33 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_init()
35 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); in usb_cpu_init()
37 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in usb_cpu_init()
38 while (readl(UHCHR) & UHCHR_FSBIR) in usb_cpu_init()
42 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); in usb_cpu_init()
45 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); in usb_cpu_init()
47 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); in usb_cpu_init()
54 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_stop()
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-ld4.c19 tmp = readl(SG_PINMON0); in upll_init()
24 tmp = readl(SC_UPLLCTRL); in upll_init()
59 tmp = readl(SG_PINMON0); in vpll_init()
63 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
66 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
71 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
74 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
79 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
82 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
87 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
[all …]
H A Dpll-pro4.c20 tmp = readl(SG_PINMON0); in vpll_init()
29 tmp = readl(SC_VPLL27ACTRL); in vpll_init()
32 tmp = readl(SC_VPLL27BCTRL); in vpll_init()
37 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
40 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
45 tmp = readl(SC_VPLL27ACTRL2); in vpll_init()
49 tmp = readl(SC_VPLL27BCTRL2); in vpll_init()
57 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
61 tmp = readl(SC_VPLL27BCTRL3); in vpll_init()
67 tmp = readl(SC_VPLL27ACTRL3); in vpll_init()
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dscu_info.c38 rev_id = readl(ASPEED_REVISION_ID0); in aspeed_print_soc_id()
39 rev_id = ((u64)readl(ASPEED_REVISION_ID1) << 32) | rev_id; in aspeed_print_soc_id()
53 u32 strap1 = readl(ASPEED_HW_STRAP1); in aspeed_get_mac_phy_interface()
55 u32 strap2 = readl(ASPEED_HW_STRAP2); in aspeed_get_mac_phy_interface()
94 u32 qsr = readl(ASPEED_OTP_QSR); in aspeed_print_security_info()
95 u32 sb_sts = readl(ASPEED_SB_STS); in aspeed_print_security_info()
218 u32 rest = readl(ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
219 u32 rest3 = readl(ASPEED_SYS_RESET_CTRL3); in aspeed_print_sysrst_info()
273 if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM) in aspeed_print_dram_initializer()
282 if (readl(ASPEED_HW_STRAP2) & BIT(11)) { in aspeed_print_2nd_wdt_mode()
[all …]
H A Dboard_common.c35 u32 value = readl(0x1e780020); in reset_eth_phy()
36 u32 direction = readl(0x1e780024); in reset_eth_phy()
44 while((readl(0x1e780020) & PHY_RESET_MASK) != 0); in reset_eth_phy()
50 while((readl(0x1e780020) & PHY_RESET_MASK) != PHY_RESET_MASK); in reset_eth_phy()
63 rev_id = readl(ASPEED_REVISION_ID0); in board_init()
64 rev_id = ((u64)readl(ASPEED_REVISION_ID1) << 32) | rev_id; in board_init()
67 if ((readl(ASPEED_SB_STS) & BIT(6))) { in board_init()
68 tmp_val = readl(0x1e60008c) & (~BIT(0)); in board_init()
133 uint32_t act_size = 256 << (readl(MMC_BASE + 0x04) & 0x3); in board_add_ram_info()
134 uint32_t vga_rsvd = 8 << ((readl(MMC_BASE + 0x04) >> 2) & 0x3); in board_add_ram_info()
[all …]
/openbmc/u-boot/board/aspeed/ast2600_dcscm/
H A Dast2600_dcscm.c38 value = readl(LPC_SNPWADR) & 0xffff0000; in port80h_snoop_init()
42 value = readl(LPC_HICR6); in port80h_snoop_init()
47 value = readl(LPC_HICR5) & ~(HICR5_UNKVAL_MASK); in port80h_snoop_init()
52 value = readl(LPC_HICRB) | HICRB_EN80HSGIO; in port80h_snoop_init()
69 writel(readl(SCU_BASE | SCU_414) | SCU_414_SGPM_MASK, in sgpio_init()
78 reg = readl(SCU_BASE + 0x510); in espi_init()
101 reg = readl(ESPI_BASE + 0x000); in espi_init()
108 reg = readl(ESPI_BASE + 0x00c); in espi_init()
116 reg = readl(ESPI_BASE + 0x080); in espi_init()
120 reg = readl(ESPI_BASE + 0x000); in espi_init()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/stv0991/
H A Dpinmux.c20 writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | in stv0991_pinmux_config()
23 writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | in stv0991_pinmux_config()
27 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | in stv0991_pinmux_config()
30 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | in stv0991_pinmux_config()
36 writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | in stv0991_pinmux_config()
39 writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | in stv0991_pinmux_config()
44 writel(readl(&stv0991_creg->mux6) & 0x000000FF, in stv0991_pinmux_config()
48 writel(readl(&stv0991_creg->mux9) & 0xFFF00000, in stv0991_pinmux_config()
51 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
53 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
[all …]
/openbmc/u-boot/board/synopsys/iot_devkit/
H A Diot_devkit.c48 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
50 writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON); in set_cpu_freq()
52 writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON); in set_cpu_freq()
56 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
58 writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON); in set_cpu_freq()
60 writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON); in set_cpu_freq()
64 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
66 writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON); in set_cpu_freq()
68 writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON); in set_cpu_freq()
72 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c48 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
59 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
67 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
73 ulong cscr = readl(&pll->cscr); in imx_get_armclk()
88 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk()
100 ulong cscr = readl(&pll->cscr); in imx_get_spllclk()
108 return imx_decode_pll(readl(&pll->spctl0), fref); in imx_get_spllclk()
120 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); in imx_get_perclk1()
127 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); in imx_get_perclk2()
134 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); in imx_get_perclk3()
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dscu_info.c60 u32 rev_id = readl(ASPEED_REVISION_ID); in aspeed_print_soc_id()
73 u32 strap1 = readl(ASPEED_HW_STRAP1); in aspeed_get_mac_phy_interface()
75 u32 strap2 = readl(ASPEED_HW_STRAP2); in aspeed_get_mac_phy_interface()
114 switch((readl(ASPEED_HW_STRAP2) >> 18) & 0x3) { in aspeed_print_security_info()
136 u32 rest = readl(ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
140 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT1_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
144 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT2_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
145 if(readl(0x1e785030) & BIT(1)) in aspeed_print_sysrst_info()
152 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT3_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
156 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL); in aspeed_print_sysrst_info()
[all …]
/openbmc/u-boot/board/toradex/colibri_pxa270/
H A Dcolibri_pxa270.c65 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & in board_usb_init()
69 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in board_usb_init()
74 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); in board_usb_init()
78 if (readl(PSSR) & PSSR_OTGPH) in board_usb_init()
79 writel(readl(PSSR) | PSSR_OTGPH, PSSR); in board_usb_init()
81 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); in board_usb_init()
82 writel(readl(UHCRHDA) | 0x100, UHCRHDA); in board_usb_init()
85 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); in board_usb_init()
88 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | in board_usb_init()
101 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_board_stop()
[all …]
/openbmc/u-boot/board/aspeed/ast2600_intel/
H A Dintel.c77 val = readl(LPC_SNPWADR) & 0xffff0000; in snoop_init()
83 val = readl(LPC_HICR6); in snoop_init()
89 val = readl(LPC_HICR5); in snoop_init()
95 val = readl(LPC_HICRB); in snoop_init()
115 val = readl(SCU_PINMUX5); in sgpio_init()
126 writel(readl(SCU_PINMUX27) & ~SCU_PINMUX27_HBLED_EN, in gpio_init()
134 writel(readl(SCU_PINMUX4) & ~SCU_PINMUX4_RGMII3TXD1, in gpio_init()
136 writel(readl(GPIO_ABCD_DIR) | GPIO_ABCD_DIR_C3, in gpio_init()
138 writel(readl(GPIO_ABCD_VAL) | GPIO_ABCD_VAL_C3, in gpio_init()
141 writel(readl(SCU_GPIO_PD0) | SCU_GPIO_PD0_B6, SCU_GPIO_PD0); in gpio_init()
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c193 r = readl(&clk->apll_con0); in exynos4_get_pll_clk()
196 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
199 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
200 k = readl(&clk->epll_con1); in exynos4_get_pll_clk()
203 r = readl(&clk->vpll_con0); in exynos4_get_pll_clk()
204 k = readl(&clk->vpll_con1); in exynos4_get_pll_clk()
223 r = readl(&clk->apll_con0); in exynos4x12_get_pll_clk()
226 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
229 r = readl(&clk->epll_con0); in exynos4x12_get_pll_clk()
230 k = readl(&clk->epll_con1); in exynos4x12_get_pll_clk()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_ti816x.c141 while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) in enable_dmm_clocks()
153 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) in enable_emif_clocks()
156 while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
159 while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
175 readl(CONTROL_STATUS); in ddr_delay()
183 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
189 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
195 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
229 while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) in main_pll_init_ti816x()
233 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A Ddwc2_udc_otg_phy.c51 writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl); in otg_phy_init()
54 writel((readl(&phy->phypwr) in otg_phy_init()
58 writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN) in otg_phy_init()
62 writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | in otg_phy_init()
66 writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | in otg_phy_init()
69 writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST)) in otg_phy_init()
72 writel(readl(&phy->rstcon) in otg_phy_init()
86 writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon); in otg_phy_off()
89 writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN in otg_phy_off()
92 writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl); in otg_phy_off()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-eth.c50 writel(readl(PLLE_POST_RESETB_ADDR) & in clk_eth_enable()
55 writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, in clk_eth_enable()
62 if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { in clk_eth_enable()
75 writel(readl(PLLE_POST_RESETB_ADDR) | in clk_eth_enable()
80 writel((readl(ESW_SYS_DIV_ADDR) & in clk_eth_enable()
85 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()
93 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()
107 writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
115 writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | in clk_eth_enable()
124 if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-eth.c50 writel(readl(PLLE_POST_RESETB_ADDR) & in clk_eth_enable()
55 writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, in clk_eth_enable()
62 if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { in clk_eth_enable()
75 writel(readl(PLLE_POST_RESETB_ADDR) | in clk_eth_enable()
80 writel((readl(ESW_SYS_DIV_ADDR) & in clk_eth_enable()
85 writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, in clk_eth_enable()
93 if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { in clk_eth_enable()
107 writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
115 writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | in clk_eth_enable()
124 if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & in clk_eth_enable()
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhwinit.c104 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) in io_settings_ddr3()
109 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) in io_settings_ddr3()
130 io_settings = readl((*ctrl)->control_smart1io_padconf_0) & in do_io_settings()
138 io_settings = readl((*ctrl)->control_smart1io_padconf_1) & in do_io_settings()
145 io_settings = readl((*ctrl)->control_smart1io_padconf_2) & in do_io_settings()
152 io_settings = readl((*ctrl)->control_smart2io_padconf_0) & in do_io_settings()
159 io_settings = readl((*ctrl)->control_smart2io_padconf_1) & in do_io_settings()
166 io_settings = readl((*ctrl)->control_smart2io_padconf_2) & in do_io_settings()
174 io_settings = readl((*ctrl)->control_smart3io_padconf_1) & in do_io_settings()
210 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspear600.c34 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in sel_1v8()
39 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in sel_1v8()
44 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE)) in sel_1v8()
53 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in sel_2v5()
58 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in sel_2v5()
63 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE)) in sel_2v5()
77 ddrpad = readl(&misc_p->ddr_pad); in plat_ddr_init()
90 core3v3 = readl(&misc_p->core_3v3_compensation); in plat_ddr_init()
95 ddr1v8 = readl(&misc_p->ddr_1v8_compensation); in plat_ddr_init()
100 ddr2v5 = readl(&misc_p->ddr_2v5_compensation); in plat_ddr_init()
[all …]
/openbmc/u-boot/drivers/watchdog/
H A Domap_wdt.c60 if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) in hw_watchdog_reset()
82 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) in omap_wdt_set_timeout()
86 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) in omap_wdt_set_timeout()
100 while (readl(&wdt->wdtwwps) != 0x0) in hw_watchdog_disable()
103 while (readl(&wdt->wdtwwps) != 0x0) in hw_watchdog_disable()
119 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) in hw_watchdog_init()
123 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) in hw_watchdog_init()
130 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) in hw_watchdog_init()
134 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) in hw_watchdog_init()
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c22 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
28 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
34 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
40 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
74 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
78 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
112 reg = readl(&scg1_regs->firccsr); in scg_fircdiv_get_rate()
116 reg = readl(&scg1_regs->fircdiv); in scg_fircdiv_get_rate()
150 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
154 reg = readl(&scg1_regs->soscdiv); in scg_soscdiv_get_rate()
[all …]

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