1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) ASPEED Technology Inc.
4 * Ryan Chen <ryan_chen@aspeedtech.com>
5 */
6
7 #include <common.h>
8 #include <errno.h>
9 #include <asm/io.h>
10 #include <asm/arch/platform.h>
11 #include <asm/arch/aspeed_scu_info.h>
12
13 /* SoC mapping Table */
14 #define SOC_ID(str, rev) { .name = str, .rev_id = rev, }
15
16 struct soc_id {
17 const char *name;
18 u32 rev_id;
19 };
20
21 static struct soc_id soc_map_table[] = {
22 SOC_ID("AST1100/AST2050-A0", 0x00000200),
23 SOC_ID("AST1100/AST2050-A1", 0x00000201),
24 SOC_ID("AST1100/AST2050-A2,3/AST2150-A0,1", 0x00000202),
25 SOC_ID("AST1510/AST2100-A0", 0x00000300),
26 SOC_ID("AST1510/AST2100-A1", 0x00000301),
27 SOC_ID("AST1510/AST2100-A2,3", 0x00000302),
28 SOC_ID("AST2200-A0,1", 0x00000102),
29 SOC_ID("AST2300-A0", 0x01000003),
30 SOC_ID("AST2300-A1", 0x01010303),
31 SOC_ID("AST1300-A1", 0x01010003),
32 SOC_ID("AST1050-A1", 0x01010203),
33 SOC_ID("AST2400-A0", 0x02000303),
34 SOC_ID("AST2400-A1", 0x02010303),
35 SOC_ID("AST1010-A0", 0x03000003),
36 SOC_ID("AST1010-A1", 0x03010003),
37 SOC_ID("AST3200-A0", 0x04002003),
38 SOC_ID("AST3200-A1", 0x04012003),
39 SOC_ID("AST3200-A2", 0x04032003),
40 SOC_ID("AST1520-A0", 0x03000203),
41 SOC_ID("AST1520-A1", 0x03010203),
42 SOC_ID("AST2510-A0", 0x04000103),
43 SOC_ID("AST2510-A1", 0x04010103),
44 SOC_ID("AST2510-A2", 0x04030103),
45 SOC_ID("AST2520-A0", 0x04000203),
46 SOC_ID("AST2520-A1", 0x04010203),
47 SOC_ID("AST2520-A2", 0x04030203),
48 SOC_ID("AST2500-A0", 0x04000303),
49 SOC_ID("AST2500-A1", 0x04010303),
50 SOC_ID("AST2500-A2", 0x04030303),
51 SOC_ID("AST2530-A0", 0x04000403),
52 SOC_ID("AST2530-A1", 0x04010403),
53 SOC_ID("AST2530-A2", 0x04030403),
54 SOC_ID("AST2600-A0", 0x05000303),
55 };
56
aspeed_print_soc_id(void)57 void aspeed_print_soc_id(void)
58 {
59 int i;
60 u32 rev_id = readl(ASPEED_REVISION_ID);
61 for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) {
62 if (rev_id == soc_map_table[i].rev_id)
63 break;
64 }
65 if (i == ARRAY_SIZE(soc_map_table))
66 printf("UnKnow-SOC : %x \n",rev_id);
67 else
68 printf("SOC : %4s \n",soc_map_table[i].name);
69 }
70
aspeed_get_mac_phy_interface(u8 num)71 int aspeed_get_mac_phy_interface(u8 num)
72 {
73 u32 strap1 = readl(ASPEED_HW_STRAP1);
74 #ifdef ASPEED_HW_STRAP2
75 u32 strap2 = readl(ASPEED_HW_STRAP2);
76 #endif
77 switch(num) {
78 case 0:
79 if(strap1 & BIT(6)) {
80 return 1;
81 } else {
82 return 0;
83 }
84 break;
85 case 1:
86 if(strap1 & BIT(7)) {
87 return 1;
88 } else {
89 return 0;
90 }
91 break;
92 #ifdef ASPEED_HW_STRAP2
93 case 2:
94 if(strap2 & BIT(0)) {
95 return 1;
96 } else {
97 return 0;
98 }
99 break;
100 case 3:
101 if(strap2 & BIT(1)) {
102 return 1;
103 } else {
104 return 0;
105 }
106 break;
107 #endif
108 }
109 return -1;
110 }
111
aspeed_print_security_info(void)112 void aspeed_print_security_info(void)
113 {
114 switch((readl(ASPEED_HW_STRAP2) >> 18) & 0x3) {
115 case 1:
116 printf("SEC : DSS Mode \n");
117 break;
118 case 2:
119 printf("SEC : UnKnow \n");
120 break;
121 case 3:
122 printf("SEC : SPI2 Mode \n");
123 break;
124 }
125 }
126
127 /* ASPEED_SYS_RESET_CTRL : System reset contrl/status register*/
128 #define SYS_WDT3_RESET BIT(4)
129 #define SYS_WDT2_RESET BIT(3)
130 #define SYS_WDT1_RESET BIT(2)
131 #define SYS_EXT_RESET BIT(1)
132 #define SYS_PWR_RESET_FLAG BIT(0)
133
aspeed_print_sysrst_info(void)134 void aspeed_print_sysrst_info(void)
135 {
136 u32 rest = readl(ASPEED_SYS_RESET_CTRL);
137
138 if (rest & SYS_WDT1_RESET) {
139 printf("RST : WDT1 \n");
140 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT1_RESET, ASPEED_SYS_RESET_CTRL);
141 }
142 if (rest & SYS_WDT2_RESET) {
143 printf("RST : WDT2 - 2nd Boot \n");
144 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT2_RESET, ASPEED_SYS_RESET_CTRL);
145 if(readl(0x1e785030) & BIT(1))
146 puts("second boot\n");
147 else
148 puts("default boot\n");
149 }
150 if (rest & SYS_WDT3_RESET) {
151 printf("RST : WDT3 - Boot\n");
152 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_WDT3_RESET, ASPEED_SYS_RESET_CTRL);
153 }
154 if(rest & SYS_EXT_RESET) {
155 printf("RST : External \n");
156 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_EXT_RESET, ASPEED_SYS_RESET_CTRL);
157 }
158 if (rest & SYS_PWR_RESET_FLAG) {
159 printf("RST : Power On \n");
160 writel(readl(ASPEED_SYS_RESET_CTRL) & ~SYS_PWR_RESET_FLAG, ASPEED_SYS_RESET_CTRL);
161 }
162 }
163
164 #define SOC_FW_INIT_DRAM BIT(7)
165
aspeed_print_dram_initializer(void)166 void aspeed_print_dram_initializer(void)
167 {
168 if(readl(ASPEED_VGA_HANDSHAKE0) & SOC_FW_INIT_DRAM)
169 printf("[init by SOC]\n");
170 else
171 printf("[init by VBIOS]\n");
172 }
173
aspeed_print_2nd_wdt_mode(void)174 void aspeed_print_2nd_wdt_mode(void)
175 {
176 if(readl(ASPEED_HW_STRAP1) & BIT(17))
177 printf("2nd Boot : Enable\n");
178 }
179
aspeed_print_spi_strap_mode(void)180 void aspeed_print_spi_strap_mode(void)
181 {
182 return;
183 }
184
aspeed_print_espi_mode(void)185 void aspeed_print_espi_mode(void)
186 {
187 int espi_mode = 0;
188 int sio_disable = 0;
189 u32 sio_addr = 0x2e;
190
191 if(readl(ASPEED_HW_STRAP1) & BIT(25))
192 espi_mode = 1;
193 else
194 espi_mode = 0;
195
196 if(readl(ASPEED_HW_STRAP1) & BIT(16))
197 sio_addr = 0x4e;
198
199 if(readl(ASPEED_HW_STRAP1) & BIT(20))
200 sio_disable = 1;
201
202 if(espi_mode)
203 printf("eSPI Mode : SIO:%s ", sio_disable ? "Disable" : "Enable");
204 else
205 printf("LPC Mode : SIO:%s ", sio_disable ? "Disable" : "Enable");
206
207 if(!sio_disable)
208 printf(": SuperIO-%02x\n", sio_addr);
209 else
210 printf("\n");
211 }
212
aspeed_print_mac_info(void)213 void aspeed_print_mac_info(void)
214 {
215 int i;
216 printf("Eth : ");
217 for (i = 0; i < ASPEED_MAC_COUNT; i++) {
218 printf("MAC%d: %s, ", i,
219 aspeed_get_mac_phy_interface(i) ? "RGMII" : "RMII/NCSI");
220 if (i != (ASPEED_MAC_COUNT -1))
221 printf(", ");
222 }
223 printf("\n");
224 }
225