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/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r1, =0x00080000
12 str r1, [r0, #0x550]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x534]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
19 ldr r1, =0x00020000
20 str r1, [r0, #0x530]
[all …]
/openbmc/u-boot/board/freescale/mx6ullevk/
H A Dplugin.S11 ldr r1, =0x000C0000
12 str r1, [r0, #0x4B4]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x4AC]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x27C]
17 ldr r1, =0x00000030
18 str r1, [r0, #0x250]
19 str r1, [r0, #0x24C]
20 str r1, [r0, #0x490]
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S68 ldr r1, =0x00040000
69 str r1, [r0, #0x128]
70 ldr r1, =0x0
71 str r1, [r0, #0xf8]
72 ldr r1, =0x00000180
73 str r1, [r0, #0xd8]
74 ldr r1, =0x00000180
75 str r1, [r0, #0x108]
76 ldr r1, =0x00000180
77 str r1, [r0, #0x104]
[all …]
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S35 mov r1, #0x00010000
36 and r0, r0, r1
46 ldr r1, [r0]
47 and r1, r1, #0x000D0000
48 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
55 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
56 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
57 orr r1, r1, #(0x1 << 4)
58 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
60 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S258 ldr r1, =0x00040000
259 str r1, [r0]
263 mov r1, r2, lsl #8
264 str r1, [r0]
270 ldr r1, [r0]
271 bic r1, r1, #0xFFFBFFFF
272 mov r2, r1, lsr #18
279 mov r1, r2, lsl #8
280 str r1, [r0]
283 ldr r1, =0x00040000
[all …]
/openbmc/u-boot/arch/microblaze/cpu/
H A Dirq.S13 addik r1, r1, -124
14 swi r2, r1, 4
15 swi r3, r1, 8
16 swi r4, r1, 12
17 swi r5, r1, 16
18 swi r6, r1, 20
19 swi r7, r1, 24
20 swi r8, r1, 28
21 swi r9, r1, 32
22 swi r10, r1, 36
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dlowlevel_init.S17 mrc 15, 0, r1, c1, c0, 1
18 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
19 mcr 15, 0, r1, c1, c0, 1
63 ldr r1, =0x77777777
64 str r1, [r0, #0x0]
65 str r1, [r0, #0x4]
67 str r1, [r0, #0x0]
68 str r1, [r0, #0x4]
84 ldr r1, =0x00000203
85 str r1, [r0, #0x40]
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S108 ldr r1, =0x00040000
109 str r1, [r0]
112 ldr r1, [r0]
114 orr r1, r1, r2, lsl #8
115 str r1, [r0]
121 ldr r1, [r0]
122 bic r1, r1, #0xFFFBFFFF
123 mov r2, r1, lsr #18
129 ldr r1, [r0]
130 bic r1, r1, #0x00000F00
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Ddebug_ll.S24 ldr r1, [r0]
25 and r1, r1, #SG_REVISION_TYPE_MASK
26 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
30 cmp r1, #0x26
34 ldr r1, [r0]
35 orr r1, r1, #1
36 str r1, [r0]
38 sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
47 cmp r1, #0x28
50 sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dasm.S20 stwu r0, -4(r1)
22 subi r1, r1, 104
23 stmw r6, 0(r1)
30 lmw r6, 0(r1)
31 addi r1, r1, 104
33 lwz r0, 0(r1)
34 addi r1, r1, 4
43 stwu r0, -4(r1)
45 subi r1, r1, 96
46 stmw r8, 0(r1)
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dplatform.S78 ldr r1, =SCU_PROT_KEY1
79 str r0, [r1]
80 ldr r1, =SCU_PROT_KEY2
81 str r0, [r1]
92 ldr r1, =REV_ID_AST2600A0
93 cmp r0, r1
97 ldr r1, =SCU_HW_STRAP1
98 ldr r1, [r1]
99 and r1, #0x700
100 lsr r1, #0x8
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx35/
H A Dlowlevel_macro.S24 ldr r1, =\mpr
25 str r1, [r0, #AIPS_MPR_0_7]
26 str r1, [r0, #AIPS_MPR_8_15]
28 str r1, [r2, #AIPS_MPR_0_7]
29 str r1, [r2, #AIPS_MPR_8_15]
32 ldr r1, =\opacr
33 str r1, [r0, #AIPS_OPACR_0_7]
34 str r1, [r0, #AIPS_OPACR_8_15]
35 str r1, [r0, #AIPS_OPACR_16_23]
36 str r1, [r0, #AIPS_OPACR_24_31]
[all …]
/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S34 ldr r1, =0x9
35 str r1, [r0]
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
45 str r3, [r1, #0x14] @INTENCLEAR
50 str r5, [r1, #0xc] @INTSELECT
55 str r5, [r1, #0xf00] @INTADDRESS
76 ldr r1, =0x00011110
77 str r1, [r8, #0x304]
78 ldr r1, =0x1
79 str r1, [r8, #0x308]
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr_lowlevel_init.S29 mov r5,r1
33 ldr r1,[r0]
35 bic r1, r1, r2
36 str r1,[r0]
38 ldr r1,[r0]
40 bic r1, r1, r2
42 orr r1, r1, r2, lsl #16
43 str r1,[r0]
45 ldr r1,[r0]
47 orr r1, r1, r2
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dlowlevel_init.S23 ldr r1, =ACFG_GPCR_VAL
25 orr r5, r5, r1
33 ldr r1, [r0]
34 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
35 str r1, [r0]
48 mov r1, #0x1000
49 1: subs r1, r1, #0x1
66 2: ldr r1, [r0, #ESDMISC_ROF]
67 ands r1, r1, r4
73 orr r1, r4, #ESDMISC_MDDR_DL_RST
[all …]
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S104 ldr r1, =0xf00dface
110 stmia r0, {r1-r4}
116 cmp r5, r1
145 ldr r1, =0x00100000
149 str r1, [r0, r1]
155 cmp r1, r2
159 mov r1, r1, lsl #1
162 cmp r1, #0x10000000
167 ldr r1, =0x00000000
173 cmp r1, #0x08000000
[all …]
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dlowlevel_init.S33 ldr r1, =DBG_CSCR_U_CONFIG
34 str r1, [r0, #0x00]
35 ldr r1, =DBG_CSCR_L_CONFIG
36 str r1, [r0, #0x04]
37 ldr r1, =DBG_CSCR_A_CONFIG
38 str r1, [r0, #0x08]
46 ldr r1, [r0, #CLKCTL_COSR]
47 bic r1, r1, #0x00000FF00
48 bic r1, r1, #0x0000000FF
51 orr r1, r1, r2
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx25/
H A Dmacro.h30 ldr r1, =\mpr
31 str r1, [r0, #AIPS_MPR_0_7]
32 str r1, [r0, #AIPS_MPR_8_15]
34 str r1, [r2, #AIPS_MPR_0_7]
35 str r1, [r2, #AIPS_MPR_8_15]
48 ldr r1, =\mpr
49 str r1, [r0, #MAX_MPR0] /* for S0 */
50 str r1, [r0, #MAX_MPR1] /* for S1 */
51 str r1, [r0, #MAX_MPR2] /* for S2 */
52 str r1, [r0, #MAX_MPR3] /* for S3 */
[all …]
/openbmc/qemu/tcg/
H A Dtci.c100 static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) in tci_args_rr() argument
103 *r1 = extract32(insn, 12, 4); in tci_args_rr()
113 TCGReg *r1, MemOpIdx *m2) in tci_args_rrm() argument
116 *r1 = extract32(insn, 12, 4); in tci_args_rrm()
120 static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) in tci_args_rrr() argument
123 *r1 = extract32(insn, 12, 4); in tci_args_rrr()
127 static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) in tci_args_rrs() argument
130 *r1 = extract32(insn, 12, 4); in tci_args_rrs()
134 static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, in tci_args_rrbb() argument
138 *r1 = extract32(insn, 12, 4); in tci_args_rrbb()
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dmemset.S27 1: orr r1, r1, r1, lsl #8
28 orr r1, r1, r1, lsl #16
29 mov r3, r1
39 mov r8, r1
40 mov lr, r1
43 stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
44 stmiage ip!, {r1, r3, r8, lr}
45 stmiage ip!, {r1, r3, r8, lr}
46 stmiage ip!, {r1, r3, r8, lr}
53 stmiane ip!, {r1, r3, r8, lr}
[all …]
H A Drelocate.S36 ldr r1, =V7M_SCB_BASE
37 str r0, [r1, V7M_SCB_VTOR]
56 ldreq r1, =0x00000000 /* If V=0 */
57 ldrne r1, =0xFFFF0000 /* If V=1 */
59 stmia r1!, {r2-r8,r10}
61 stmia r1!, {r2-r8,r10}
82 ldr r1, _image_copy_start_ofs
83 add r1, r3 /* r1 <- Run &__image_copy_start */
84 subs r4, r0, r1 /* r4 <- Run to copy offset */
86 ldr r1, _image_copy_start_ofs
[all …]
H A Ddebug.S44 mov r1, #8
49 mov r1, #4
54 mov r1, #2
56 add r3, r2, r1
57 mov r1, #0
58 strb r1, [r3]
59 1: and r1, r0, #15
61 cmp r1, #10
62 addlt r1, r1, #'0'
63 addge r1, r1, #'a' - 10
[all …]
H A Dlib1funcs.S199 subs r2, r1, #1
202 cmp r0, r1
204 tst r1, r2
207 ARM_DIV_BODY r0, r1, r2, r3
216 12: ARM_DIV2_ORDER r1, r2
230 subs r2, r1, #1 @ compare divisor with 1
232 cmpne r0, r1 @ compare dividend with divisor
234 tsthi r1, r2 @ see if divisor is power of 2
238 ARM_MOD_BODY r0, r1, r2, r3
251 cmp r1, #0
[all …]
/openbmc/u-boot/board/syteco/zmx25/
H A Dlowlevel_init.S50 ldr r1, =(1 << 1) | (1 << 2)
51 str r1, [r0, #ESDRAMC_ESDMISC]
55 ldr r1, =(1 << 2)
56 str r1, [r0, #ESDRAMC_ESDMISC]
58 ldr r1, =0x002a7420
59 str r1, [r0, #ESDRAMC_ESDCFG0]
62 ldr r1, =0x92216008
63 str r1, [r0, #ESDRAMC_ESDCTL0]
65 str r1, [r2, #0x400]
68 ldr r1, =0xa2216008
[all …]
/openbmc/qemu/pc-bios/s390-ccw/
H A Dstart.S31 lgr %r1,%r2
34 xc 0(256,%r1),0(%r1)
35 la %r1,256(%r1)
47 xc 0(1,%r1),0(%r1)
56 larl %r1,disabled_wait_psw
57 lpswe 0(%r1)
73 larl %r1,external_new_code
74 stg %r1,0x1b8
75 larl %r1,external_new_mask
76 mvc 0x1b0(8),0(%r1)
[all …]

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