Lines Matching refs:r1
17 mrc 15, 0, r1, c1, c0, 1
18 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
19 mcr 15, 0, r1, c1, c0, 1
63 ldr r1, =0x77777777
64 str r1, [r0, #0x0]
65 str r1, [r0, #0x4]
67 str r1, [r0, #0x0]
68 str r1, [r0, #0x4]
84 ldr r1, =0x00000203
85 str r1, [r0, #0x40]
89 ldr r1, =0x00120125
90 str r1, [r0, #0x9C]
92 ldr r1, =0x001901A3
93 str r1, [r0, #0x48]
109 ldr r1, =0x00001232
110 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
111 mov r1, #0x2
112 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
114 ldr r1, [r2, #W_DP_OP]
115 str r1, [r0, #PLL_DP_OP]
116 str r1, [r0, #PLL_DP_HFS_OP]
118 ldr r1, [r2, #W_DP_MFD]
119 str r1, [r0, #PLL_DP_MFD]
120 str r1, [r0, #PLL_DP_HFS_MFD]
122 ldr r1, [r2, #W_DP_MFN]
123 str r1, [r0, #PLL_DP_MFN]
124 str r1, [r0, #PLL_DP_HFS_MFN]
126 ldr r1, =0x00001232
127 str r1, [r0, #PLL_DP_CTL]
128 1: ldr r1, [r0, #PLL_DP_CTL]
129 ands r1, r1, #0x1
138 ldr r1, =0x00001236
139 str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
140 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
141 ands r1, r1, #0x1
148 mov r1, #0x1
149 str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
151 2: ldr r1, [r2, #PLL_DP_CONFIG]
152 tst r1, #1
155 ldr r1, =100 /* Wait at least 4 us */
156 3: subs r1, r1, #1
159 mov r1, #0x2
160 str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
168 ldr r1, =0x3FFFFFFF
169 str r1, [r0, #CLKCTL_CCGR0]
174 ldr r1, =0x00030000
175 str r1, [r0, #CLKCTL_CCGR4]
176 ldr r1, =0x00FFF030
177 str r1, [r0, #CLKCTL_CCGR5]
178 ldr r1, =0x00000300
179 str r1, [r0, #CLKCTL_CCGR6]
182 mov r1, #0x60000
183 str r1, [r0, #CLKCTL_CCDR]
186 ldr r1, =0x19239145
187 str r1, [r0, #CLKCTL_CBCDR]
189 1: ldr r1, [r0, #CLKCTL_CDHIPR]
190 cmp r1, #0x0
194 mov r1, #0x4
195 str r1, [r0, #CLKCTL_CCSR]
208 ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
209 str r1, [r0, #CLKCTL_CBCMR]
210 ldr r1, =0x13239145
211 str r1, [r0, #CLKCTL_CBCDR]
216 ldr r1, =0x19239145
217 str r1, [r0, #CLKCTL_CBCDR]
218 ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
219 str r1, [r0, #CLKCTL_CBCMR]
225 ldr r1, =0x00000725
226 str r1, [r0, #0x14]
233 movls r1, #0x1
234 movhi r1, #0
236 str r1, [r0, #CLKCTL_CACRR]
243 ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
244 str r1, [r0, #CLKCTL_CBCMR]
246 ldr r1, =CONFIG_SYS_CLKTL_CBCDR
247 str r1, [r0, #CLKCTL_CBCDR]
250 ldr r1, =0xFFFFFFFF
251 str r1, [r0, #CLKCTL_CCGR0]
252 str r1, [r0, #CLKCTL_CCGR1]
253 str r1, [r0, #CLKCTL_CCGR2]
254 str r1, [r0, #CLKCTL_CCGR3]
255 str r1, [r0, #CLKCTL_CCGR4]
256 str r1, [r0, #CLKCTL_CCGR5]
257 str r1, [r0, #CLKCTL_CCGR6]
260 ldr r1, =0xA5A2A020
261 str r1, [r0, #CLKCTL_CSCMR1]
262 ldr r1, =0x00C30321
263 str r1, [r0, #CLKCTL_CSCDR1]
265 1: ldr r1, [r0, #CLKCTL_CDHIPR]
266 cmp r1, #0x0
272 mov r1, #0x000A0000
273 add r1, r1, #0x00000F0
274 str r1, [r0, #CLKCTL_CCOSR]
279 ldr r1, =0x3FFFFFFF
280 str r1, [r0, #CLKCTL_CCGR0]
285 ldr r1, =0x00030000
286 str r1, [r0, #CLKCTL_CCGR4]
287 ldr r1, =0x00FFF030
288 str r1, [r0, #CLKCTL_CCGR5]
289 ldr r1, =0x0F00030F
290 str r1, [r0, #CLKCTL_CCGR6]
293 mov r1, #0x4
294 str r1, [r0, #CLKCTL_CCSR]
302 ldr r1, =0x00015154
303 str r1, [r0, #CLKCTL_CBCMR]
304 ldr r1, =0x02898945
305 str r1, [r0, #CLKCTL_CBCDR]
307 1: ldr r1, [r0, #CLKCTL_CDHIPR]
308 cmp r1, #0x0
315 ldr r1, =0x00888945
316 str r1, [r0, #CLKCTL_CBCDR]
318 ldr r1, =0x00016154
319 str r1, [r0, #CLKCTL_CBCMR]
322 ldr r1, [r0, #CLKCTL_CSCMR1]
323 and r1, r1, #0xfcffffff
324 orr r1, r1, #0x01000000
325 str r1, [r0, #CLKCTL_CSCMR1]
328 1: ldr r1, [r0, #CLKCTL_CDHIPR]
329 cmp r1, #0x0
338 ldr r1, =0x00000124
339 str r1, [r0, #0x14]
342 mov r1, #0
343 str r1, [r0, #CLKCTL_CACRR]
346 mov r1, #0x0
347 str r1, [r0, #CLKCTL_CCSR]
350 ldr r1, [r0, #CLKCTL_CSCDR1]
351 and r1, r1, #0xffffffc0
352 orr r1, r1, #0x0a
353 str r1, [r0, #CLKCTL_CSCDR1]
356 ldr r1, =0xFFFFFFFF
357 str r1, [r0, #CLKCTL_CCGR0]
358 str r1, [r0, #CLKCTL_CCGR1]
359 str r1, [r0, #CLKCTL_CCGR2]
360 str r1, [r0, #CLKCTL_CCGR3]
361 str r1, [r0, #CLKCTL_CCGR4]
362 str r1, [r0, #CLKCTL_CCGR5]
363 str r1, [r0, #CLKCTL_CCGR6]
364 str r1, [r0, #CLKCTL_CCGR7]
366 mov r1, #0x00000
367 str r1, [r0, #CLKCTL_CCDR]
370 mov r1, #0x000A0000
371 add r1, r1, #0x00000F0
372 str r1, [r0, #CLKCTL_CCOSR]
383 ldr r1, [r0, #0x0]
384 orr r1, r1, #1 << 23
385 str r1, [r0, #0x0]
386 ldr r1, [r0, #0x4]
387 orr r1, r1, #1 << 23
388 str r1, [r0, #0x4]