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Searched refs:pwm_parents (Results 1 – 25 of 25) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c86 static const char *const pwm_parents[] __initconst = { variable
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
H A Dclk-mt7981-topckgen.c140 static const char * const pwm_parents[] __initconst = { variable
303 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt6795-topckgen.c273 static const char * const pwm_parents[] = { variable
460 TOP_MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x50, 0, 2, 7, 0),
H A Dclk-mt8186-topckgen.c243 static const char * const pwm_parents[] = { variable
581 pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
H A Dclk-mt8173-topckgen.c66 static const char * const pwm_parents[] = { variable
539 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
H A Dclk-mt7622.c67 static const char * const pwm_parents[] = { variable
396 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt2712.c154 static const char * const pwm_parents[] = { variable
650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7),
744 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15),
H A Dclk-mt8516.c310 static const char * const pwm_parents[] __initconst = { variable
421 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt8167.c469 static const char * const pwm_parents[] = { variable
610 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt7629.c97 static const char * const pwm_parents[] = { variable
471 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
H A Dclk-mt6797.c117 static const char * const pwm_parents[] = { variable
333 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
H A Dclk-mt8188-topckgen.c647 static const char * const pwm_parents[] = { variable
1083 pwm_parents, 0x0BC, 0x0C0, 0x0C4, 8, 4, 15, 0x08, 21),
H A Dclk-mt8365.c278 static const char * const pwm_parents[] = { variable
490 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
H A Dclk-mt8192.c497 static const char * const pwm_parents[] = { variable
674 pwm_parents, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
H A Dclk-mt8195-topckgen.c552 static const char * const pwm_parents[] = { variable
1026 pwm_parents, 0x0E0, 0x0E4, 0x0E8, 16, 1, 23, 0x0C, 2),
H A Dclk-mt6779.c608 static const char * const pwm_parents[] = { variable
772 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
H A Dclk-mt6765.c325 static const char * const pwm_parents[] = { variable
451 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
H A Dclk-mt2701.c175 static const char * const pwm_parents[] = { variable
496 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mt7629.c183 static const int pwm_parents[] = { variable
370 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
H A Dclk-mt7623.c218 static const int pwm_parents[] = { variable
514 MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
/openbmc/linux/drivers/clk/sprd/
H A Dsc9860-clk.c563 static const char * const pwm_parents[] = { "ext-32k", "ext-26m", variable
566 static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248,
568 static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c,
570 static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250,
572 static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254,
H A Dums512-clk.c765 static const struct clk_parent_data pwm_parents[] = { variable
772 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents,
774 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents,
776 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents,
778 static SPRD_MUX_CLK_DATA(pwm3_clk, "pwm3-clk", pwm_parents,
H A Dsc9863a-clk.c365 static const struct clk_parent_data pwm_parents[] = { variable
371 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 0x23c,
373 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 0x240,
375 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 0x244,
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra20.c752 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m", variable
770 …TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TE…
H A Dclk-tegra30.c982 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" }; variable
993 …TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PE…