| /openbmc/u-boot/drivers/usb/host/ |
| H A D | utmi-armada100.c | 20 struct armd1usb_phy_reg *phy_regs = in utmi_phy_init() local
24 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); in utmi_phy_init()
26 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); in utmi_phy_init()
28 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); in utmi_phy_init()
29 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); in utmi_phy_init()
31 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); in utmi_phy_init()
35 while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) in utmi_phy_init()
41 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
43 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
46 setbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
[all …]
|
| H A D | ehci-mxs.c | 23 struct mxs_usbphy_regs *phy_regs; member
109 writel(USBPHY_CTRL_SFTRST, &port->phy_regs->hw_usbphy_ctrl_set); in ehci_hcd_init()
112 &port->phy_regs->hw_usbphy_ctrl_clr); in ehci_hcd_init()
120 writel(0, &port->phy_regs->hw_usbphy_pwd); in ehci_hcd_init()
124 &port->phy_regs->hw_usbphy_ctrl_set); in ehci_hcd_init()
165 writel(tmp, &port->phy_regs->hw_usbphy_pwd); in ehci_hcd_stop()
|
| /openbmc/u-boot/drivers/usb/phy/ |
| H A D | omap_usb_phy.c | 66 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) in omap_usb_dpll_relock() argument
70 writel(SET_PLL_GO, &phy_regs->pll_go); in omap_usb_dpll_relock()
72 val = readl(&phy_regs->pll_status); in omap_usb_dpll_relock()
78 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) in omap_usb_dpll_lock() argument
87 val = readl(&phy_regs->pll_config_1); in omap_usb_dpll_lock()
90 writel(val, &phy_regs->pll_config_1); in omap_usb_dpll_lock()
92 val = readl(&phy_regs->pll_config_2); in omap_usb_dpll_lock()
95 writel(val, &phy_regs->pll_config_2); in omap_usb_dpll_lock()
97 val = readl(&phy_regs->pll_config_1); in omap_usb_dpll_lock()
100 writel(val, &phy_regs->pll_config_1); in omap_usb_dpll_lock()
[all …]
|
| /openbmc/qemu/hw/misc/ |
| H A D | aspeed_ltpi.c | 58 return s->phy_regs[idx]; in aspeed_ltpi_phy_read()
69 s->phy_regs[idx] = (uint32_t)val; in aspeed_ltpi_phy_write()
121 memset(s->phy_regs, 0, sizeof(s->phy_regs)); in aspeed_ltpi_reset()
125 s->phy_regs[LTPI_PHY_MODE] = 0x2; in aspeed_ltpi_reset()
136 VMSTATE_UINT32_ARRAY(phy_regs, AspeedLTPIState,
|
| /openbmc/qemu/hw/net/ |
| H A D | msf2-emac.c | 186 s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | in msf2_phy_update_link()
189 s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | in msf2_phy_update_link()
196 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); in msf2_phy_reset()
197 s->phy_regs[MII_BMCR] = 0x1140; in msf2_phy_reset()
198 s->phy_regs[MII_BMSR] = 0x7968; in msf2_phy_reset()
199 s->phy_regs[MII_PHYID1] = 0x0022; in msf2_phy_reset()
200 s->phy_regs[MII_PHYID2] = 0x1550; in msf2_phy_reset()
201 s->phy_regs[MII_ANAR] = 0x01E1; in msf2_phy_reset()
202 s->phy_regs[MII_ANLPAR] = 0xCDE1; in msf2_phy_reset()
228 s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; in write_to_phy()
[all …]
|
| H A D | npcm_gmac.c | 148 gmac->phy_regs[0][MII_BMSR] |= (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
150 gmac->phy_regs[0][MII_BMSR] &= ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COMP); in gmac_phy_set_link()
680 !(gmac->phy_regs[pa][MII_BMSR] & MII_BMSR_AN_COMP)) { in npcm_gmac_mdio_access()
682 gmac->phy_regs[pa][MII_BMSR] |= MII_BMSR_AN_COMP; in npcm_gmac_mdio_access()
684 gmac->phy_regs[0][MII_ANLPAR] = 0x0000; in npcm_gmac_mdio_access()
687 gmac->phy_regs[pa][gr] = data; in npcm_gmac_mdio_access()
689 data = gmac->phy_regs[pa][gr]; in npcm_gmac_mdio_access()
847 memcpy(gmac->phy_regs[0], phy_reg_init, sizeof(phy_reg_init)); in npcm_gmac_reset()
850 gmac->phy_regs[0][MII_BMSR]); in npcm_gmac_reset()
|
| /openbmc/u-boot/drivers/net/mscc_eswitch/ |
| H A D | mscc_miim.h | 8 void __iomem *phy_regs; member
|
| H A D | ocelot_switch.c | 149 if (miim->phy_regs) { in mscc_miim_reset()
150 writel(0, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
152 | PHY_CFG_ENA, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
194 miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]); in ocelot_mdiobus_init()
|
| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_ltpi.h | 28 uint32_t phy_regs[ASPEED_LTPI_PHY_SIZE >> 2]; member
|
| /openbmc/qemu/include/hw/net/ |
| H A D | msf2-emac.h | 50 uint16_t phy_regs[PHY_MAX_REGS]; member
|
| H A D | npcm_gmac.h | 167 uint16_t phy_regs[NPCM_GMAC_MAX_PHYS][NPCM_GMAC_MAX_PHY_REGS]; member
|
| /openbmc/u-boot/include/ |
| H A D | fm_eth.h | 62 .phy_regs = (void *)pregs, \
174 void *phy_regs; member
|
| H A D | vsc9953.h | 692 .phy_regs = NULL, \
703 void *phy_regs; member
|
| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3399.h | 108 struct rk3399_ddr_publ_regs phy_regs; member
|
| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3399.c | 462 const u32 *params_phy = sdram_params->phy_regs.denali_phy; in pctl_cfg()
480 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); in pctl_cfg()
481 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); in pctl_cfg()
482 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); in pctl_cfg()
|