1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c916d7c9SKumar Gala /* 3111fd19eSRoy Zang * Copyright 2009-2012 Freescale Semiconductor, Inc. 4c916d7c9SKumar Gala */ 5c916d7c9SKumar Gala 6c916d7c9SKumar Gala #ifndef __FM_ETH_H__ 7c916d7c9SKumar Gala #define __FM_ETH_H__ 8c916d7c9SKumar Gala 9c916d7c9SKumar Gala #include <common.h> 1093f26f13SClaudiu Manoil #include <phy.h> 11c916d7c9SKumar Gala #include <asm/types.h> 12c916d7c9SKumar Gala 13c916d7c9SKumar Gala enum fm_port { 14c916d7c9SKumar Gala FM1_DTSEC1, 15c916d7c9SKumar Gala FM1_DTSEC2, 16c916d7c9SKumar Gala FM1_DTSEC3, 17c916d7c9SKumar Gala FM1_DTSEC4, 18c916d7c9SKumar Gala FM1_DTSEC5, 199e758758SYork Sun FM1_DTSEC6, 209e758758SYork Sun FM1_DTSEC9, 219e758758SYork Sun FM1_DTSEC10, 22c916d7c9SKumar Gala FM1_10GEC1, 239e758758SYork Sun FM1_10GEC2, 2482a55c1eSShengzhou Liu FM1_10GEC3, 2582a55c1eSShengzhou Liu FM1_10GEC4, 26c916d7c9SKumar Gala FM2_DTSEC1, 27c916d7c9SKumar Gala FM2_DTSEC2, 28c916d7c9SKumar Gala FM2_DTSEC3, 29c916d7c9SKumar Gala FM2_DTSEC4, 3099abf7deSTimur Tabi FM2_DTSEC5, 319e758758SYork Sun FM2_DTSEC6, 329e758758SYork Sun FM2_DTSEC9, 339e758758SYork Sun FM2_DTSEC10, 34c916d7c9SKumar Gala FM2_10GEC1, 359e758758SYork Sun FM2_10GEC2, 36c916d7c9SKumar Gala NUM_FM_PORTS, 37c916d7c9SKumar Gala }; 38c916d7c9SKumar Gala 39c916d7c9SKumar Gala enum fm_eth_type { 40c916d7c9SKumar Gala FM_ETH_1G_E, 41c916d7c9SKumar Gala FM_ETH_10G_E, 42c916d7c9SKumar Gala }; 43c916d7c9SKumar Gala 44111fd19eSRoy Zang #ifdef CONFIG_SYS_FMAN_V3 45111fd19eSRoy Zang #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) 46111fd19eSRoy Zang #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) 4723e1acafSShaohui Xie #if (CONFIG_SYS_NUM_FMAN == 2) 48111fd19eSRoy Zang #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) 49111fd19eSRoy Zang #define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) 5023e1acafSShaohui Xie #endif 51111fd19eSRoy Zang #else 52c916d7c9SKumar Gala #define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) 53c916d7c9SKumar Gala #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) 54111fd19eSRoy Zang #endif 55c916d7c9SKumar Gala 56c916d7c9SKumar Gala #define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" 57c916d7c9SKumar Gala #define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO" 58c916d7c9SKumar Gala 59c916d7c9SKumar Gala /* Fman ethernet info struct */ 60c916d7c9SKumar Gala #define FM_ETH_INFO_INITIALIZER(idx, pregs) \ 61c916d7c9SKumar Gala .fm = idx, \ 62c916d7c9SKumar Gala .phy_regs = (void *)pregs, \ 63c916d7c9SKumar Gala .enet_if = PHY_INTERFACE_MODE_NONE, \ 64c916d7c9SKumar Gala 65111fd19eSRoy Zang #ifdef CONFIG_SYS_FMAN_V3 66111fd19eSRoy Zang #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ 67111fd19eSRoy Zang { \ 68111fd19eSRoy Zang FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \ 69111fd19eSRoy Zang .index = idx, \ 70111fd19eSRoy Zang .num = n - 1, \ 71111fd19eSRoy Zang .type = FM_ETH_1G_E, \ 72111fd19eSRoy Zang .port = FM##idx##_DTSEC##n, \ 73111fd19eSRoy Zang .rx_port_id = RX_PORT_1G_BASE + n - 1, \ 74111fd19eSRoy Zang .tx_port_id = TX_PORT_1G_BASE + n - 1, \ 75111fd19eSRoy Zang .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 76111fd19eSRoy Zang offsetof(struct ccsr_fman, memac[n-1]),\ 77111fd19eSRoy Zang } 78111fd19eSRoy Zang 79cc19c25eSShengzhou Liu #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION 80cc19c25eSShengzhou Liu #define FM_TGEC_INFO_INITIALIZER(idx, n) \ 81cc19c25eSShengzhou Liu { \ 82cc19c25eSShengzhou Liu FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ 83cc19c25eSShengzhou Liu .index = idx, \ 84cc19c25eSShengzhou Liu .num = n - 1, \ 85cc19c25eSShengzhou Liu .type = FM_ETH_10G_E, \ 86cc19c25eSShengzhou Liu .port = FM##idx##_10GEC##n, \ 87cc19c25eSShengzhou Liu .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ 88cc19c25eSShengzhou Liu .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ 89cc19c25eSShengzhou Liu .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 90cc19c25eSShengzhou Liu offsetof(struct ccsr_fman, memac[n-1]),\ 91cc19c25eSShengzhou Liu } 92cc19c25eSShengzhou Liu #else 9323e1acafSShaohui Xie #if (CONFIG_SYS_NUM_FMAN == 2) 94111fd19eSRoy Zang #define FM_TGEC_INFO_INITIALIZER(idx, n) \ 95111fd19eSRoy Zang { \ 96944b6ccfSShaohui Xie FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \ 97111fd19eSRoy Zang .index = idx, \ 98111fd19eSRoy Zang .num = n - 1, \ 99111fd19eSRoy Zang .type = FM_ETH_10G_E, \ 100111fd19eSRoy Zang .port = FM##idx##_10GEC##n, \ 101111fd19eSRoy Zang .rx_port_id = RX_PORT_10G_BASE + n - 1, \ 102111fd19eSRoy Zang .tx_port_id = TX_PORT_10G_BASE + n - 1, \ 103111fd19eSRoy Zang .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 104944b6ccfSShaohui Xie offsetof(struct ccsr_fman, memac[n-1+8]),\ 105111fd19eSRoy Zang } 10623e1acafSShaohui Xie #else 10723e1acafSShaohui Xie #define FM_TGEC_INFO_INITIALIZER(idx, n) \ 10823e1acafSShaohui Xie { \ 10923e1acafSShaohui Xie FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ 11023e1acafSShaohui Xie .index = idx, \ 11123e1acafSShaohui Xie .num = n - 1, \ 11223e1acafSShaohui Xie .type = FM_ETH_10G_E, \ 11323e1acafSShaohui Xie .port = FM##idx##_10GEC##n, \ 11423e1acafSShaohui Xie .rx_port_id = RX_PORT_10G_BASE + n - 1, \ 11523e1acafSShaohui Xie .tx_port_id = TX_PORT_10G_BASE + n - 1, \ 11623e1acafSShaohui Xie .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 11723e1acafSShaohui Xie offsetof(struct ccsr_fman, memac[n-1+8]),\ 11823e1acafSShaohui Xie } 11923e1acafSShaohui Xie #endif 120cc19c25eSShengzhou Liu #endif 12182a55c1eSShengzhou Liu 12282a55c1eSShengzhou Liu #if (CONFIG_SYS_NUM_FM1_10GEC >= 3) 12382a55c1eSShengzhou Liu #define FM_TGEC_INFO_INITIALIZER2(idx, n) \ 12482a55c1eSShengzhou Liu { \ 12582a55c1eSShengzhou Liu FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ 12682a55c1eSShengzhou Liu .index = idx, \ 12782a55c1eSShengzhou Liu .num = n - 1, \ 12882a55c1eSShengzhou Liu .type = FM_ETH_10G_E, \ 12982a55c1eSShengzhou Liu .port = FM##idx##_10GEC##n, \ 13082a55c1eSShengzhou Liu .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \ 13182a55c1eSShengzhou Liu .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \ 13282a55c1eSShengzhou Liu .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 13382a55c1eSShengzhou Liu offsetof(struct ccsr_fman, memac[n-1-2]),\ 13482a55c1eSShengzhou Liu } 13582a55c1eSShengzhou Liu #endif 13682a55c1eSShengzhou Liu 137111fd19eSRoy Zang #else 138c916d7c9SKumar Gala #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ 139c916d7c9SKumar Gala { \ 140c916d7c9SKumar Gala FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \ 141c916d7c9SKumar Gala .index = idx, \ 142c916d7c9SKumar Gala .num = n - 1, \ 143c916d7c9SKumar Gala .type = FM_ETH_1G_E, \ 144c916d7c9SKumar Gala .port = FM##idx##_DTSEC##n, \ 145c916d7c9SKumar Gala .rx_port_id = RX_PORT_1G_BASE + n - 1, \ 146c916d7c9SKumar Gala .tx_port_id = TX_PORT_1G_BASE + n - 1, \ 147c916d7c9SKumar Gala .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 148c916d7c9SKumar Gala offsetof(struct ccsr_fman, mac_1g[n-1]),\ 149c916d7c9SKumar Gala } 150c916d7c9SKumar Gala 151c916d7c9SKumar Gala #define FM_TGEC_INFO_INITIALIZER(idx, n) \ 152c916d7c9SKumar Gala { \ 153c916d7c9SKumar Gala FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ 154c916d7c9SKumar Gala .index = idx, \ 155c916d7c9SKumar Gala .num = n - 1, \ 156c916d7c9SKumar Gala .type = FM_ETH_10G_E, \ 157c916d7c9SKumar Gala .port = FM##idx##_10GEC##n, \ 158c916d7c9SKumar Gala .rx_port_id = RX_PORT_10G_BASE + n - 1, \ 159c916d7c9SKumar Gala .tx_port_id = TX_PORT_10G_BASE + n - 1, \ 160c916d7c9SKumar Gala .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ 161c916d7c9SKumar Gala offsetof(struct ccsr_fman, mac_10g[n-1]),\ 162c916d7c9SKumar Gala } 163111fd19eSRoy Zang #endif 164c916d7c9SKumar Gala struct fm_eth_info { 165c916d7c9SKumar Gala u8 enabled; 166c916d7c9SKumar Gala u8 fm; 167c916d7c9SKumar Gala u8 num; 168c916d7c9SKumar Gala u8 phy_addr; 169c916d7c9SKumar Gala int index; 170c916d7c9SKumar Gala u16 rx_port_id; 171c916d7c9SKumar Gala u16 tx_port_id; 172c916d7c9SKumar Gala enum fm_port port; 173c916d7c9SKumar Gala enum fm_eth_type type; 174c916d7c9SKumar Gala void *phy_regs; 175c916d7c9SKumar Gala phy_interface_t enet_if; 176c916d7c9SKumar Gala u32 compat_offset; 177c916d7c9SKumar Gala struct mii_dev *bus; 178c916d7c9SKumar Gala }; 179c916d7c9SKumar Gala 180c916d7c9SKumar Gala struct tgec_mdio_info { 181c916d7c9SKumar Gala struct tgec_mdio_controller *regs; 182c916d7c9SKumar Gala char *name; 183c916d7c9SKumar Gala }; 184c916d7c9SKumar Gala 185111fd19eSRoy Zang struct memac_mdio_info { 186111fd19eSRoy Zang struct memac_mdio_controller *regs; 187111fd19eSRoy Zang char *name; 188111fd19eSRoy Zang }; 189111fd19eSRoy Zang 190c916d7c9SKumar Gala int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info); 191111fd19eSRoy Zang int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info); 192111fd19eSRoy Zang 193c916d7c9SKumar Gala int fm_standard_init(bd_t *bis); 194c916d7c9SKumar Gala void fman_enet_init(void); 195c916d7c9SKumar Gala void fdt_fixup_fman_ethernet(void *fdt); 196c916d7c9SKumar Gala phy_interface_t fm_info_get_enet_if(enum fm_port port); 197c916d7c9SKumar Gala void fm_info_set_phy_address(enum fm_port port, int address); 198ae2291fbSTimur Tabi int fm_info_get_phy_address(enum fm_port port); 199c916d7c9SKumar Gala void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus); 20069a85242SKumar Gala void fm_disable_port(enum fm_port port); 201f51d3b71SValentin Longchamp void fm_enable_port(enum fm_port port); 202ffee1ddeSZhao Qiang void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port, 203ffee1ddeSZhao Qiang unsigned int port_num, int phy_base_addr); 204ffee1ddeSZhao Qiang int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr, 205ffee1ddeSZhao Qiang unsigned int port_num, unsigned regnum); 206c916d7c9SKumar Gala 207c916d7c9SKumar Gala #endif 208