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Searched refs:phy_ctrl (Results 1 – 24 of 24) sorted by relevance

/openbmc/u-boot/drivers/usb/host/
H A Dehci-mx6.c131 void __iomem *phy_ctrl; in usb_phy_enable() local
139 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
154 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
158 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
164 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
173 void __iomem *phy_ctrl; in usb_phy_mode() local
177 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_mode()
179 val = readl(phy_ctrl); in usb_phy_mode()
439 void *__iomem phy_ctrl, *__iomem phy_status; in ehci_usb_phy_mode() local
460 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); in ehci_usb_phy_mode()
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H A Dehci-vf.c87 void __iomem *phy_ctrl; in usb_phy_enable() local
91 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
104 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
108 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
115 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c281 *phy_ctrl) in dmc_get_read_offset_value()
283 return readl(&phy_ctrl->phy_con4); in dmc_get_read_offset_value()
291 static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) in ddr_phy_set_do_resync() argument
293 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
294 clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
305 static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, in dmc_set_read_offset_value() argument
308 writel(offset, &phy_ctrl->phy_con4); in dmc_set_read_offset_value()
309 ddr_phy_set_do_resync(phy_ctrl); in dmc_set_read_offset_value()
351 void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, in test_shifts() argument
360 dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); in test_shifts()
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/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2500.c113 writel(0, &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
116 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
117 while ((readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) in ast2500_ddr_phy_init_process()
120 &regs->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
125 writel(0, &info->regs->phy_ctrl[0]); in ast2500_sdrammc_set_vref()
H A Dsdram_ast2600.c212 writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]); in ast2600_sdramphy_kick_training()
214 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]); in ast2600_sdramphy_kick_training()
218 data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; in ast2600_sdramphy_kick_training()
243 writel(0, &info->regs->phy_ctrl[0]); in ast2600_sdramphy_init()
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dsun4i-usb-phy.txt18 * "phy_ctrl"
53 reg-names = "phy_ctrl", "pmu1", "pmu2";
/openbmc/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dsdram_ast2500.h122 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ member
H A Dsdram_ast2600.h154 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ member
/openbmc/u-boot/drivers/net/
H A De1000.c2413 uint32_t phy_ctrl = 0; in e1000_set_d3_lplu_state() local
2435 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2453 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2454 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2505 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2506 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2548 uint32_t phy_ctrl = 0; in e1000_set_d0_lplu_state() local
2557 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2559 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); in e1000_set_d0_lplu_state()
2569 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
[all …]
/openbmc/u-boot/drivers/ram/
H A Dk3-am654-ddrss.c201 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; in am654_ddrss_phy_configuration()
743 (u32 *)&ddrss->params.phy_ctrl, in am654_ddrss_ofdata_to_priv()
744 sizeof(ddrss->params.phy_ctrl) / sizeof(u32)); in am654_ddrss_ofdata_to_priv()
H A Dk3-am654-ddrss.h1183 struct ddrss_ddrphy_ctrl_params phy_ctrl; member
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a23.dtsi87 reg-names = "phy_ctrl", "pmu1";
H A Dsun8i-v3s.dtsi173 reg-names = "phy_ctrl",
H A Dsun8i-a33.dtsi532 reg-names = "phy_ctrl", "pmu1";
H A Dsun8i-r40.dtsi182 reg-names = "phy_ctrl",
H A Dsun5i.dtsi331 reg-names = "phy_ctrl", "pmu1";
H A Dsunxi-h3-h5.dtsi262 reg-names = "phy_ctrl",
H A Dam33xx.dtsi633 reg-names = "phy_ctrl", "wakeup";
H A Dsun50i-a64.dtsi428 reg-names = "phy_ctrl",
H A Dsun8i-a83t.dtsi573 reg-names = "phy_ctrl",
H A Dsun4i-a10.dtsi460 reg-names = "phy_ctrl", "pmu1", "pmu2";
H A Dsun6i-a31.dtsi485 reg-names = "phy_ctrl",
H A Dsun7i-a20.dtsi537 reg-names = "phy_ctrl", "pmu1", "pmu2";
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp.h192 unsigned int phy_ctrl; member