1*e267d940SIcenowy Zheng/* 2*e267d940SIcenowy Zheng * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3*e267d940SIcenowy Zheng * 4*e267d940SIcenowy Zheng * This file is dual-licensed: you can use it either under the terms 5*e267d940SIcenowy Zheng * of the GPL or the X11 license, at your option. Note that this dual 6*e267d940SIcenowy Zheng * licensing only applies to this file, and not this project as a 7*e267d940SIcenowy Zheng * whole. 8*e267d940SIcenowy Zheng * 9*e267d940SIcenowy Zheng * a) This file is free software; you can redistribute it and/or 10*e267d940SIcenowy Zheng * modify it under the terms of the GNU General Public License as 11*e267d940SIcenowy Zheng * published by the Free Software Foundation; either version 2 of the 12*e267d940SIcenowy Zheng * License, or (at your option) any later version. 13*e267d940SIcenowy Zheng * 14*e267d940SIcenowy Zheng * This file is distributed in the hope that it will be useful, 15*e267d940SIcenowy Zheng * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*e267d940SIcenowy Zheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*e267d940SIcenowy Zheng * GNU General Public License for more details. 18*e267d940SIcenowy Zheng * 19*e267d940SIcenowy Zheng * Or, alternatively, 20*e267d940SIcenowy Zheng * 21*e267d940SIcenowy Zheng * b) Permission is hereby granted, free of charge, to any person 22*e267d940SIcenowy Zheng * obtaining a copy of this software and associated documentation 23*e267d940SIcenowy Zheng * files (the "Software"), to deal in the Software without 24*e267d940SIcenowy Zheng * restriction, including without limitation the rights to use, 25*e267d940SIcenowy Zheng * copy, modify, merge, publish, distribute, sublicense, and/or 26*e267d940SIcenowy Zheng * sell copies of the Software, and to permit persons to whom the 27*e267d940SIcenowy Zheng * Software is furnished to do so, subject to the following 28*e267d940SIcenowy Zheng * conditions: 29*e267d940SIcenowy Zheng * 30*e267d940SIcenowy Zheng * The above copyright notice and this permission notice shall be 31*e267d940SIcenowy Zheng * included in all copies or substantial portions of the Software. 32*e267d940SIcenowy Zheng * 33*e267d940SIcenowy Zheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*e267d940SIcenowy Zheng * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*e267d940SIcenowy Zheng * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*e267d940SIcenowy Zheng * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*e267d940SIcenowy Zheng * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*e267d940SIcenowy Zheng * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*e267d940SIcenowy Zheng * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*e267d940SIcenowy Zheng * OTHER DEALINGS IN THE SOFTWARE. 41*e267d940SIcenowy Zheng */ 42*e267d940SIcenowy Zheng 43*e267d940SIcenowy Zheng#include <dt-bindings/clock/sun8i-v3s-ccu.h> 44*e267d940SIcenowy Zheng#include <dt-bindings/reset/sun8i-v3s-ccu.h> 45*e267d940SIcenowy Zheng#include <dt-bindings/interrupt-controller/arm-gic.h> 46*e267d940SIcenowy Zheng#include <dt-bindings/pinctrl/sun4i-a10.h> 47*e267d940SIcenowy Zheng 48*e267d940SIcenowy Zheng/ { 49*e267d940SIcenowy Zheng #address-cells = <1>; 50*e267d940SIcenowy Zheng #size-cells = <1>; 51*e267d940SIcenowy Zheng interrupt-parent = <&gic>; 52*e267d940SIcenowy Zheng 53*e267d940SIcenowy Zheng cpus { 54*e267d940SIcenowy Zheng #address-cells = <1>; 55*e267d940SIcenowy Zheng #size-cells = <0>; 56*e267d940SIcenowy Zheng 57*e267d940SIcenowy Zheng cpu@0 { 58*e267d940SIcenowy Zheng compatible = "arm,cortex-a7"; 59*e267d940SIcenowy Zheng device_type = "cpu"; 60*e267d940SIcenowy Zheng reg = <0>; 61*e267d940SIcenowy Zheng clocks = <&ccu CLK_CPU>; 62*e267d940SIcenowy Zheng }; 63*e267d940SIcenowy Zheng }; 64*e267d940SIcenowy Zheng 65*e267d940SIcenowy Zheng timer { 66*e267d940SIcenowy Zheng compatible = "arm,armv7-timer"; 67*e267d940SIcenowy Zheng interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 68*e267d940SIcenowy Zheng <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 69*e267d940SIcenowy Zheng <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 70*e267d940SIcenowy Zheng <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 71*e267d940SIcenowy Zheng }; 72*e267d940SIcenowy Zheng 73*e267d940SIcenowy Zheng clocks { 74*e267d940SIcenowy Zheng #address-cells = <1>; 75*e267d940SIcenowy Zheng #size-cells = <1>; 76*e267d940SIcenowy Zheng ranges; 77*e267d940SIcenowy Zheng 78*e267d940SIcenowy Zheng osc24M: osc24M_clk { 79*e267d940SIcenowy Zheng #clock-cells = <0>; 80*e267d940SIcenowy Zheng compatible = "fixed-clock"; 81*e267d940SIcenowy Zheng clock-frequency = <24000000>; 82*e267d940SIcenowy Zheng clock-output-names = "osc24M"; 83*e267d940SIcenowy Zheng }; 84*e267d940SIcenowy Zheng 85*e267d940SIcenowy Zheng osc32k: osc32k_clk { 86*e267d940SIcenowy Zheng #clock-cells = <0>; 87*e267d940SIcenowy Zheng compatible = "fixed-clock"; 88*e267d940SIcenowy Zheng clock-frequency = <32768>; 89*e267d940SIcenowy Zheng clock-output-names = "osc32k"; 90*e267d940SIcenowy Zheng }; 91*e267d940SIcenowy Zheng }; 92*e267d940SIcenowy Zheng 93*e267d940SIcenowy Zheng soc { 94*e267d940SIcenowy Zheng compatible = "simple-bus"; 95*e267d940SIcenowy Zheng #address-cells = <1>; 96*e267d940SIcenowy Zheng #size-cells = <1>; 97*e267d940SIcenowy Zheng ranges; 98*e267d940SIcenowy Zheng 99*e267d940SIcenowy Zheng mmc0: mmc@01c0f000 { 100*e267d940SIcenowy Zheng compatible = "allwinner,sun7i-a20-mmc"; 101*e267d940SIcenowy Zheng reg = <0x01c0f000 0x1000>; 102*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_MMC0>, 103*e267d940SIcenowy Zheng <&ccu CLK_MMC0>, 104*e267d940SIcenowy Zheng <&ccu CLK_MMC0_OUTPUT>, 105*e267d940SIcenowy Zheng <&ccu CLK_MMC0_SAMPLE>; 106*e267d940SIcenowy Zheng clock-names = "ahb", 107*e267d940SIcenowy Zheng "mmc", 108*e267d940SIcenowy Zheng "output", 109*e267d940SIcenowy Zheng "sample"; 110*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_MMC0>; 111*e267d940SIcenowy Zheng reset-names = "ahb"; 112*e267d940SIcenowy Zheng interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 113*e267d940SIcenowy Zheng status = "disabled"; 114*e267d940SIcenowy Zheng #address-cells = <1>; 115*e267d940SIcenowy Zheng #size-cells = <0>; 116*e267d940SIcenowy Zheng }; 117*e267d940SIcenowy Zheng 118*e267d940SIcenowy Zheng mmc1: mmc@01c10000 { 119*e267d940SIcenowy Zheng compatible = "allwinner,sun7i-a20-mmc"; 120*e267d940SIcenowy Zheng reg = <0x01c10000 0x1000>; 121*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_MMC1>, 122*e267d940SIcenowy Zheng <&ccu CLK_MMC1>, 123*e267d940SIcenowy Zheng <&ccu CLK_MMC1_OUTPUT>, 124*e267d940SIcenowy Zheng <&ccu CLK_MMC1_SAMPLE>; 125*e267d940SIcenowy Zheng clock-names = "ahb", 126*e267d940SIcenowy Zheng "mmc", 127*e267d940SIcenowy Zheng "output", 128*e267d940SIcenowy Zheng "sample"; 129*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_MMC1>; 130*e267d940SIcenowy Zheng reset-names = "ahb"; 131*e267d940SIcenowy Zheng interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 132*e267d940SIcenowy Zheng status = "disabled"; 133*e267d940SIcenowy Zheng #address-cells = <1>; 134*e267d940SIcenowy Zheng #size-cells = <0>; 135*e267d940SIcenowy Zheng }; 136*e267d940SIcenowy Zheng 137*e267d940SIcenowy Zheng mmc2: mmc@01c11000 { 138*e267d940SIcenowy Zheng compatible = "allwinner,sun7i-a20-mmc"; 139*e267d940SIcenowy Zheng reg = <0x01c11000 0x1000>; 140*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_MMC2>, 141*e267d940SIcenowy Zheng <&ccu CLK_MMC2>, 142*e267d940SIcenowy Zheng <&ccu CLK_MMC2_OUTPUT>, 143*e267d940SIcenowy Zheng <&ccu CLK_MMC2_SAMPLE>; 144*e267d940SIcenowy Zheng clock-names = "ahb", 145*e267d940SIcenowy Zheng "mmc", 146*e267d940SIcenowy Zheng "output", 147*e267d940SIcenowy Zheng "sample"; 148*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_MMC2>; 149*e267d940SIcenowy Zheng reset-names = "ahb"; 150*e267d940SIcenowy Zheng interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 151*e267d940SIcenowy Zheng status = "disabled"; 152*e267d940SIcenowy Zheng #address-cells = <1>; 153*e267d940SIcenowy Zheng #size-cells = <0>; 154*e267d940SIcenowy Zheng }; 155*e267d940SIcenowy Zheng 156*e267d940SIcenowy Zheng usb_otg: usb@01c19000 { 157*e267d940SIcenowy Zheng compatible = "allwinner,sun8i-h3-musb"; 158*e267d940SIcenowy Zheng reg = <0x01c19000 0x0400>; 159*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_OTG>; 160*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_OTG>; 161*e267d940SIcenowy Zheng interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 162*e267d940SIcenowy Zheng interrupt-names = "mc"; 163*e267d940SIcenowy Zheng phys = <&usbphy 0>; 164*e267d940SIcenowy Zheng phy-names = "usb"; 165*e267d940SIcenowy Zheng extcon = <&usbphy 0>; 166*e267d940SIcenowy Zheng status = "disabled"; 167*e267d940SIcenowy Zheng }; 168*e267d940SIcenowy Zheng 169*e267d940SIcenowy Zheng usbphy: phy@01c19400 { 170*e267d940SIcenowy Zheng compatible = "allwinner,sun8i-v3s-usb-phy"; 171*e267d940SIcenowy Zheng reg = <0x01c19400 0x2c>, 172*e267d940SIcenowy Zheng <0x01c1a800 0x4>; 173*e267d940SIcenowy Zheng reg-names = "phy_ctrl", 174*e267d940SIcenowy Zheng "pmu0"; 175*e267d940SIcenowy Zheng clocks = <&ccu CLK_USB_PHY0>; 176*e267d940SIcenowy Zheng clock-names = "usb0_phy"; 177*e267d940SIcenowy Zheng resets = <&ccu RST_USB_PHY0>; 178*e267d940SIcenowy Zheng reset-names = "usb0_reset"; 179*e267d940SIcenowy Zheng status = "disabled"; 180*e267d940SIcenowy Zheng #phy-cells = <1>; 181*e267d940SIcenowy Zheng }; 182*e267d940SIcenowy Zheng 183*e267d940SIcenowy Zheng ccu: clock@01c20000 { 184*e267d940SIcenowy Zheng compatible = "allwinner,sun8i-v3s-ccu"; 185*e267d940SIcenowy Zheng reg = <0x01c20000 0x400>; 186*e267d940SIcenowy Zheng clocks = <&osc24M>, <&osc32k>; 187*e267d940SIcenowy Zheng clock-names = "hosc", "losc"; 188*e267d940SIcenowy Zheng #clock-cells = <1>; 189*e267d940SIcenowy Zheng #reset-cells = <1>; 190*e267d940SIcenowy Zheng }; 191*e267d940SIcenowy Zheng 192*e267d940SIcenowy Zheng rtc: rtc@01c20400 { 193*e267d940SIcenowy Zheng compatible = "allwinner,sun6i-a31-rtc"; 194*e267d940SIcenowy Zheng reg = <0x01c20400 0x54>; 195*e267d940SIcenowy Zheng interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 196*e267d940SIcenowy Zheng <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 197*e267d940SIcenowy Zheng }; 198*e267d940SIcenowy Zheng 199*e267d940SIcenowy Zheng pio: pinctrl@01c20800 { 200*e267d940SIcenowy Zheng compatible = "allwinner,sun8i-v3s-pinctrl"; 201*e267d940SIcenowy Zheng reg = <0x01c20800 0x400>; 202*e267d940SIcenowy Zheng interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 203*e267d940SIcenowy Zheng <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 204*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 205*e267d940SIcenowy Zheng clock-names = "apb", "hosc", "losc"; 206*e267d940SIcenowy Zheng gpio-controller; 207*e267d940SIcenowy Zheng #gpio-cells = <3>; 208*e267d940SIcenowy Zheng interrupt-controller; 209*e267d940SIcenowy Zheng #interrupt-cells = <3>; 210*e267d940SIcenowy Zheng 211*e267d940SIcenowy Zheng uart0_pins_a: uart0@0 { 212*e267d940SIcenowy Zheng pins = "PB8", "PB9"; 213*e267d940SIcenowy Zheng function = "uart0"; 214*e267d940SIcenowy Zheng bias-pull-up; 215*e267d940SIcenowy Zheng }; 216*e267d940SIcenowy Zheng 217*e267d940SIcenowy Zheng mmc0_pins_a: mmc0@0 { 218*e267d940SIcenowy Zheng pins = "PF0", "PF1", "PF2", "PF3", 219*e267d940SIcenowy Zheng "PF4", "PF5"; 220*e267d940SIcenowy Zheng function = "mmc0"; 221*e267d940SIcenowy Zheng drive-strength = <30>; 222*e267d940SIcenowy Zheng bias-pull-up; 223*e267d940SIcenowy Zheng }; 224*e267d940SIcenowy Zheng }; 225*e267d940SIcenowy Zheng 226*e267d940SIcenowy Zheng timer@01c20c00 { 227*e267d940SIcenowy Zheng compatible = "allwinner,sun4i-a10-timer"; 228*e267d940SIcenowy Zheng reg = <0x01c20c00 0xa0>; 229*e267d940SIcenowy Zheng interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 230*e267d940SIcenowy Zheng <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 231*e267d940SIcenowy Zheng clocks = <&osc24M>; 232*e267d940SIcenowy Zheng }; 233*e267d940SIcenowy Zheng 234*e267d940SIcenowy Zheng wdt0: watchdog@01c20ca0 { 235*e267d940SIcenowy Zheng compatible = "allwinner,sun6i-a31-wdt"; 236*e267d940SIcenowy Zheng reg = <0x01c20ca0 0x20>; 237*e267d940SIcenowy Zheng interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 238*e267d940SIcenowy Zheng }; 239*e267d940SIcenowy Zheng 240*e267d940SIcenowy Zheng uart0: serial@01c28000 { 241*e267d940SIcenowy Zheng compatible = "snps,dw-apb-uart"; 242*e267d940SIcenowy Zheng reg = <0x01c28000 0x400>; 243*e267d940SIcenowy Zheng interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 244*e267d940SIcenowy Zheng reg-shift = <2>; 245*e267d940SIcenowy Zheng reg-io-width = <4>; 246*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_UART0>; 247*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_UART0>; 248*e267d940SIcenowy Zheng status = "disabled"; 249*e267d940SIcenowy Zheng }; 250*e267d940SIcenowy Zheng 251*e267d940SIcenowy Zheng uart1: serial@01c28400 { 252*e267d940SIcenowy Zheng compatible = "snps,dw-apb-uart"; 253*e267d940SIcenowy Zheng reg = <0x01c28400 0x400>; 254*e267d940SIcenowy Zheng interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 255*e267d940SIcenowy Zheng reg-shift = <2>; 256*e267d940SIcenowy Zheng reg-io-width = <4>; 257*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_UART1>; 258*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_UART1>; 259*e267d940SIcenowy Zheng status = "disabled"; 260*e267d940SIcenowy Zheng }; 261*e267d940SIcenowy Zheng 262*e267d940SIcenowy Zheng uart2: serial@01c28800 { 263*e267d940SIcenowy Zheng compatible = "snps,dw-apb-uart"; 264*e267d940SIcenowy Zheng reg = <0x01c28800 0x400>; 265*e267d940SIcenowy Zheng interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 266*e267d940SIcenowy Zheng reg-shift = <2>; 267*e267d940SIcenowy Zheng reg-io-width = <4>; 268*e267d940SIcenowy Zheng clocks = <&ccu CLK_BUS_UART2>; 269*e267d940SIcenowy Zheng resets = <&ccu RST_BUS_UART2>; 270*e267d940SIcenowy Zheng status = "disabled"; 271*e267d940SIcenowy Zheng }; 272*e267d940SIcenowy Zheng 273*e267d940SIcenowy Zheng gic: interrupt-controller@01c81000 { 274*e267d940SIcenowy Zheng compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 275*e267d940SIcenowy Zheng reg = <0x01c81000 0x1000>, 276*e267d940SIcenowy Zheng <0x01c82000 0x1000>, 277*e267d940SIcenowy Zheng <0x01c84000 0x2000>, 278*e267d940SIcenowy Zheng <0x01c86000 0x2000>; 279*e267d940SIcenowy Zheng interrupt-controller; 280*e267d940SIcenowy Zheng #interrupt-cells = <3>; 281*e267d940SIcenowy Zheng interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 282*e267d940SIcenowy Zheng }; 283*e267d940SIcenowy Zheng }; 284*e267d940SIcenowy Zheng}; 285