Home
last modified time | relevance | path

Searched refs:pgsr (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.c251 u32 pgsr; in ddrphy_idone_wait() local
254 ret = readl_poll_timeout(&phy->pgsr, pgsr, in ddrphy_idone_wait()
255 pgsr & (DDRPHYC_PGSR_IDONE | in ddrphy_idone_wait()
263 (u32)&phy->pgsr, pgsr, ret); in ddrphy_idone_wait()
H A Dstm32mp1_ddr_regs.h144 u32 pgsr; /* 0x0C PHY General Status*/ member
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun6i.c155 mctl_await_completion(&mctl_phy->pgsr, 0x03, 0x03); in mctl_channel_init()
162 mctl_await_completion(&mctl_phy->pgsr, 0x1f, 0x1f); in mctl_channel_init()
193 mctl_await_completion(&mctl_phy->pgsr, 0x11, 0x11); in mctl_channel_init()
195 if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK) in mctl_channel_init()
H A Ddram_sun50i_h6.c84 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0)); in mctl_phy_pir_init()
636 if (readl(&mctl_phy->pgsr[0]) & 0x400000) in mctl_channel_init()
656 if (readl(&mctl_phy->pgsr[0]) & 0xff00000) { in mctl_channel_init()
659 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0])); in mctl_channel_init()
H A Ddram_sunxi_dw.c24 mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); in mctl_phy_init()
525 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { in mctl_channel_init()
556 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) in mctl_channel_init()
H A Ddram_sun9i.c792 if (readl(&mctl_phy->pgsr[0]) & MCTL_PGSR0_ERRORS) { in mctl_channel_init()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c303 while ((readl(&publ->pgsr) & in phy_init()
333 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
353 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
458 if (readl(&publ->pgsr) & in data_training()
496 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
H A Dsdram_rk3288.c361 while ((readl(&publ->pgsr) & in phy_init()
391 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
411 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
516 if (readl(&publ->pgsr) & in data_training()
554 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sunxi_dw.h86 u32 pgsr[2]; /* 0x10 PHY general status registers */ member
H A Ddram_sun50i_h6.h154 u32 pgsr[3]; /* 0x034 */ member
H A Ddram_sun9i.h96 u32 pgsr[2]; /* 0x18 PHY general status register */ member
H A Ddram_sun6i.h160 u32 pgsr; /* 0x0c */ member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dddr_rk3288.h170 u32 pgsr; member