Merge git://git.denx.de/u-boot-sunxi

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borro

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

show more ...

Merge git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
include/configs/imx6qdl_icore_rqs.h
include/configs/imx6ul_gea

Merge git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
include/configs/imx6qdl_icore_rqs.h
include/configs/imx6ul_geam.h
include/configs/imx6ul_isiot.h

show more ...

Merge branch 'master' of git://git.denx.de/u-boot-samsung

Merge tag 'xilinx-for-v2017.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.07

ZynqMP:
- config cleanup
- SD LS mode support
- psu_init* cleanup

Merge tag 'xilinx-for-v2017.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.07

ZynqMP:
- config cleanup
- SD LS mode support
- psu_init* cleanup
- unmap OCM
- Support for SMC

Zynq:
- add ddrc to Kconfig
- add topic-miamilite board support

show more ...

Merge git://git.denx.de/u-boot-usb

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller

Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.

Add support for LPDDR3 DRAM

sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller

Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.

Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.

Real LPDDR3 chips' support is not added yet in this commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: add support for V3s DRAM controller

Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.

Add support for it.

Signed-off-by: Icenowy

sunxi: add support for V3s DRAM controller

Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: add support for the DDR2 in V3s SoC

Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.

Add support for it.

Signed-off-by: Ice

sunxi: add support for the DDR2 in V3s SoC

Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: enable dual rank detection in DesignWare-like DRAM code

The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect t

sunxi: enable dual rank detection in DesignWare-like DRAM code

The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.

Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.

Currently we know little about the dual-rank on R40, and the usage
of A15 address line seems to be breaking dual-rank support. The only R40
board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather
than dual-rank, thus we cannot do research for it. So dual rank detection
is temporarily disabled on R40.

This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: Add selective DRAM type and timing

DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the origina

sunxi: Add selective DRAM type and timing

DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: add bank detection code to H3 DRAM initialization code

Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by: Icenowy Zhen

sunxi: add bank detection code to H3 DRAM initialization code

Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: add option for 16-bit DW DRAM controller

Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.

Add support for them.

Signed-off-b

sunxi: add option for 16-bit DW DRAM controller

Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.

Add support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: Rename bus-width related macros in H3 DRAM code

The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.

As H3 itsel

sunxi: Rename bus-width related macros in H3 DRAM code

The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.

As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.

Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.

This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...

sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free

sunxi: makes an invisible option for H3-like DRAM controllers

Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

show more ...