/openbmc/linux/arch/arm/lib/ |
H A D | io-readsb.S | 39 orr r3, r3, r4, put_byte_1 41 orr r3, r3, r5, put_byte_2 43 orr r3, r3, r6, put_byte_3 47 orr r4, r4, r5, put_byte_1 49 orr r4, r4, r6, put_byte_2 51 orr r4, r4, ip, put_byte_3 55 orr r5, r5, r6, put_byte_1 57 orr r5, r5, ip, put_byte_2 59 orr r5, r5, lr, put_byte_3 62 orr r6, r6, ip, put_byte_1 [all …]
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H A D | io-writesw-armv3.S | 25 orr r3, r3, r3, lsl #16 44 orr ip, ip, ip, lsr #16 48 orr ip, ip, ip, lsl #16 52 orr ip, ip, ip, lsr #16 56 orr ip, ip, ip, lsl #16 60 orr ip, ip, ip, lsr #16 64 orr ip, ip, ip, lsl #16 68 orr ip, ip, ip, lsr #16 72 orr ip, ip, ip, lsl #16 87 orr ip, ip, ip, lsr #16 [all …]
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H A D | csumpartialcopygeneric.S | 177 orr r4, r4, r5, lspush #24 179 orr r5, r5, r6, lspush #24 181 orr r6, r6, r7, lspush #24 183 orr r7, r7, r8, lspush #24 283 orr r4, r4, r5, lspush #8 285 orr r5, r5, r6, lspush #8 287 orr r6, r6, r7, lspush #8 289 orr r7, r7, r8, lspush #8 304 orr r4, r4, r5, lspush #8 306 orr r5, r5, r6, lspush #8 [all …]
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H A D | io-readsw-armv3.S | 36 orr ip, ip, ip, lsl #8 45 orr r3, r3, r4, lsl #16 50 orr r4, r4, r5, lsl #16 55 orr r5, r5, r6, lsl #16 60 orr r6, r6, lr, lsl #16 76 orr r3, r3, r4, lsl #16 81 orr r4, r4, r5, lsl #16 91 orr r3, r3, r4, lsl #16
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/openbmc/linux/drivers/scsi/arm/ |
H A D | acornscsi-io.S | 25 orr lr, lr, #0xff00 31 orr r3, r3, r4, lsl #16 33 orr r4, r4, r6, lsl #16 36 orr r5, r5, r6, lsl #16 38 orr r6, r6, ip, lsl #16 47 orr r3, r3, r4, lsl #16 49 orr r4, r4, r6, lsl #16 58 orr r3, r3, r4, lsl #16 83 orr r3, r3, r3, lsr #16 85 orr r4, r4, r4, lsl #16 [all …]
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/openbmc/linux/arch/arm/mach-omap1/ |
H A D | sleep.S | 73 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000 74 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00 88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000 89 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff 94 orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff 113 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00 153 orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000 154 orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00 158 orr r9, r7, #SELF_REFRESH_MODE & 0xff000000 159 orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff [all …]
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H A D | sram.S | 26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 37 orr r0, r0, #1 << 4 @ set lock bit again 44 orr r4, r4, #0x00ff
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/openbmc/linux/arch/arm/mach-at91/ |
H A D | pm_suspend.S | 108 orr r9, r9, r10 310 orr tmp1, tmp1, #0x1 314 orr tmp1, tmp1, #0x1 318 orr tmp1, tmp1, #0x1 322 orr tmp1, tmp1, #0x1 326 orr tmp1, tmp1, #0x1 696 orr tmp1, tmp1, tmp2 701 orr tmp1, tmp1, tmp2 768 orr tmp1, tmp1, tmp3 785 orr tmp1, tmp1, tmp3 [all …]
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/openbmc/linux/arch/arm64/lib/ |
H A D | strlen.S | 97 orr tmp2, data1, REP8_7f 99 orr tmp4, data2, REP8_7f 126 orr tmp2, tmp1, tmp3 132 orr tmp2, tmp1, tmp3 138 orr tmp2, data1, REP8_7f 139 orr tmp4, data2, REP8_7f 155 orr tmp2, data1, REP8_7f 171 orr tmp2, data1, REP8_7f 173 orr tmp4, data2, REP8_7f 180 orr tmp2, data1, REP8_7f [all …]
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H A D | strcmp.S | 73 orr tmp, tmp, REP8_7f 76 orr tmp, data1, REP8_7f 85 orr syndrome, diff, has_nul 117 orr data1, data1, tmp 118 orr data2, data2, tmp 142 orr data3, data3, tmp 144 orr tmp, data3, REP8_7f 159 orr tmp, data3, REP8_7f 170 orr syndrome, diff, tmp 182 orr syndrome, diff, has_nul
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H A D | strncmp.S | 80 orr tmp2, data1, #REP8_7f 90 orr syndrome, diff, has_nul 121 orr has_nul, has_nul, mask 139 orr tmp2, tmp3, #REP8_7f 142 orr syndrome, diff, has_nul 174 orr data1, data1, tmp2 175 orr data2, data2, tmp2 252 orr tmp3, data1, #REP8_7f 255 orr tmp3, endloop, has_nul 279 orr syndrome, diff, has_nul [all …]
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H A D | strnlen.S | 75 orr tmp2, data1, #REP8_7f 77 orr tmp4, data2, #REP8_7f 81 orr tmp1, has_nul1, has_nul2 107 CPU_BE( orr tmp2, data2, #REP8_7f ) 149 orr data1, data1, tmp2 150 orr data2a, data2, tmp2
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/openbmc/u-boot/arch/arm/mach-orion5x/ |
H A D | lowlevel_init.S | 172 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN 184 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */ 187 orr r0, r0, r1 194 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN 206 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */ 209 orr r0, r0, r1 220 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN 226 orr r0, r0, r1 231 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN 237 orr r0, r0, r1 [all …]
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/openbmc/linux/arch/arm64/include/asm/ |
H A D | el2_setup.h | 82 orr x2, x2, x0 // If we don't have VHE, then 95 orr x2, x2, x0 // allow the EL1&0 translation 123 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 169 orr x0, x0, #(1 << 62) 181 orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK 182 orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK 190 orr x0, x0, #HFGxTR_EL2_nPIR_EL1 191 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 312 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 323 orr x0, x0, SMCR_ELx_FA64_MASK [all …]
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/openbmc/linux/arch/arm/mm/ |
H A D | proc-v7-2level.S | 46 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 47 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 80 orr r3, r3, r2 81 orr r3, r3, #PTE_EXT_AP0 | 2 148 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP) 149 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP) 150 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) 151 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
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H A D | proc-v6.S | 102 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 103 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 111 orr r1, r1, r2 @ insert into new context ID 164 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 165 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 201 orr r0, r0, #0x20 213 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 214 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 215 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 216 ALT_UP(orr r8, r8, #TTB_FLAGS_UP) [all …]
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/openbmc/u-boot/arch/arm/mach-davinci/ |
H A D | lowlevel_init.S | 57 orr r7, r7, $0x02 106 orr r8, r8, r9 162 orr r8, r8, r9 168 orr r7, r7, $0x01 185 orr r8, r8, r9 191 orr r7, r7, $0x01 210 orr r8, r8, $0x08 380 orr r8, r8, r9 462 orr r2, r2, r1 509 orr r8, r7, r8 [all …]
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/openbmc/u-boot/board/armltd/integrator/ |
H A D | lowlevel_init.S | 16 orr r1,r1,#CMMASK_RESET 45 orr r2,r2,#CMMASK_INIT_102 68 orr r2,r2,#CMMASK_CMxx6_COMMON 87 orr r1,r1,r2 160 orr r2, r1, r2, ASL#12 /* OR in column address lines */ 161 orr r3, r2, r3, ASL#16 /* OR in number of banks */ 162 orr r6, r6, r3 /* OR in size and CAS latency */ 179 orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
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/openbmc/linux/arch/arm/mach-davinci/ |
H A D | sleep.S | 55 orr ip, ip, #DDR2_LPMODEN_BIT 59 orr ip, ip, #DDR2_MCLKSTOPEN_BIT 90 orr ip, ip, #PLLCTL_PLLPWRDN 95 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT 124 orr ip, ip, #PLLCTL_PLLRST 135 orr ip, ip, #PLLCTL_PLLEN 141 orr ip, ip, #PLLDIV_EN 180 orr ip, ip, r0 185 orr ip, ip, #0x1
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/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/ |
H A D | lowlevel_init.S | 248 orr r0, r0, #EP93XX_LED_RED_ON 261 orr r2, r2, r1 265 orr r2, r2, r1 269 orr r2, r2, r1 273 orr r2, r2, r1 277 orr r2, r2, r1 281 orr r2, r2, r1 339 orr r2, r11, #0x00008800 359 orr r2, r11, #0x00004600 376 orr r1, r1, #EP93XX_LED_GREEN_ON [all …]
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/openbmc/u-boot/arch/arm/cpu/armv7/ |
H A D | start.S | 99 orr r0, r0, #0xc0 @ disable FIQ and IRQ 194 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 195 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB 205 orr r0, r0, #1 << 11 @ set bit #11 211 orr r0, r0, #1 << 4 @ set bit #4 217 orr r0, r0, #1 << 6 @ set bit #6 223 orr r0, r0, #1 << 11 @ set bit #11 228 orr r0, r0, #1 << 21 @ set bit #21 234 orr r0, r0, #1 << 22 @ set bit #22 348 orr r0, r0, #1 << 24 @ set bit #24 [all …]
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/openbmc/u-boot/arch/arm/mach-uniphier/arm32/ |
H A D | debug_ll.S | 35 orr r1, r1, #1 58 orr r1, r1, #SC_CLKCTRL_CEN_PERI 73 orr r1, r1, #1 99 orr r1, r1, #SC_CLKCTRL_CEN_PERI 114 orr r1, r1, #1 124 orr r1, r1, #SC_CLKCTRL_CEN_PERI 139 orr r1, r1, #1 148 orr r1, r1, #SC_CLKCTRL_CEN_PERI
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/openbmc/qemu/tests/tcg/arm/system/ |
H A D | boot.S | 112 orr r3, r4, r4 115 orr r3, r3, #2 124 orr r2, r2, r3 /* common bits */ 125 orr r2, r2, #(1 << 15) /* AP[2] = 1 */ 126 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RO @ PL1 */ 135 orr r2, r2, r3 /* common bits */ 136 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RW @ PL1 */ 137 orr r2, r2, #(1 << 4) /* XN[4] => no execute */
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/ |
H A D | start.S | 42 orr r0,r0,#0xd3 93 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 97 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 99 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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/openbmc/u-boot/arch/arm/cpu/armv8/ |
H A D | start.S | 107 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ 133 orr x0, x0, #0x40 234 orr x0, x0, #1 << 44 244 orr x0, x0, #1 << 49 246 orr x0, x0, #3 << 25 248 orr x0, x0, #3 << 27 255 orr x0, x0, #1 << 59 264 orr x0, x0, #1 << 38 274 orr x0, x0, #1 << 4
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