Lines Matching refs:orr
82 orr x2, x2, x0 // If we don't have VHE, then
95 orr x2, x2, x0 // allow the EL1&0 translation
123 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
124 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
169 orr x0, x0, #(1 << 62)
181 orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
182 orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
190 orr x0, x0, #HFGxTR_EL2_nPIR_EL1
191 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1
279 orr x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
300 orr x0, x0, #(CPACR_EL1_SMEN_EL0EN | CPACR_EL1_SMEN_EL1EN)
312 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps
323 orr x0, x0, SMCR_ELx_FA64_MASK
330 orr x0, x0, SMCR_ELx_EZT0_MASK
333 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector