Lines Matching refs:orr
102 orr r9, r9, #AT91_SFRBU_25LDOCR_LP
108 orr r9, r9, r10
115 orr \reg, \reg, #0x200000
166 orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
187 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
191 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
197 orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
202 orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
203 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
204 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
209 orr tmp1, tmp1, #DDR3PHY_DSGCR_ODTPDD_ODT0
283 orr tmp1, tmp1, #UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN
310 orr tmp1, tmp1, #0x1
314 orr tmp1, tmp1, #0x1
318 orr tmp1, tmp1, #0x1
322 orr tmp1, tmp1, #0x1
326 orr tmp1, tmp1, #0x1
374 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
395 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
409 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
487 orr tmp1, tmp1, #AT91_PMC_PRES_64
498 orr tmp1, tmp1, #AT91_PMC_KEY
511 orr tmp1, tmp1, #AT91_PMC_KEY
543 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
545 orr tmp1, tmp1, #AT91_PMC_KEY
555 orr tmp1, tmp1, #AT91_PMC_MOSCEN
556 orr tmp1, tmp1, #AT91_PMC_KEY
580 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
582 orr tmp1, tmp1, #AT91_PMC_KEY
594 orr tmp1, tmp1, #AT91_PMC_KEY
603 orr tmp1, tmp1, #AT91_PMC_KEY
609 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
616 orr tmp1, tmp1, #AT91_PMC_WAITMODE
618 orr tmp1, tmp1, #AT91_PMC_KEY
629 orr tmp1, tmp1, #AT91_PMC_MOSCEN
631 orr tmp1, tmp1, #AT91_PMC_KEY
645 orr tmp1, tmp1, #AT91_PMC_MOSCSEL
647 orr tmp1, tmp1, #AT91_PMC_KEY
655 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
669 orr tmp1, tmp1, #AT91_PMC_KEY
696 orr tmp1, tmp1, tmp2
701 orr tmp1, tmp1, tmp2
713 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
718 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
729 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
742 orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
768 orr tmp1, tmp1, tmp3
774 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
779 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK
780 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL
781 orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK
785 orr tmp1, tmp1, tmp3
790 orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE
859 orr tmp2, tmp2, #AT91_PMC_MCR_V2_CSS_MAINCK
860 orr tmp2, tmp2, #AT91_PMC_MCR_V2_DIV1
915 orr tmp3, tmp3, tmp2
917 orr tmp3, tmp3, tmp1
918 orr tmp3, tmp3, #AT91_PMC_MCR_V2_CMD
948 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN