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Searched refs:mtspr (Results 1 – 21 of 21) sorted by relevance

/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Drelease.S33 mtspr PIR, r0
37 mtspr IBAT0U, r0
38 mtspr IBAT1U, r0
39 mtspr IBAT2U, r0
40 mtspr IBAT3U, r0
41 mtspr IBAT4U, r0
42 mtspr IBAT5U, r0
43 mtspr IBAT6U, r0
44 mtspr IBAT7U, r0
46 mtspr DBAT0U, r0
[all …]
H A Dstart.S145 mtspr HID0, r0
161 mtspr l2cr, r3
201 mtspr SPRN_SRR0,r3
202 mtspr SPRN_SRR1,r5
286 mtspr IBAT0U, r0
287 mtspr IBAT1U, r0
288 mtspr IBAT2U, r0
289 mtspr IBAT3U, r0
290 mtspr IBAT4U, r0
291 mtspr IBAT5U, r0
[all …]
H A Dcache.S38 mtspr HID0,r3
48 mtspr HID0,r3
180 mtspr HID0, r5
181 mtspr HID0, r3
197 mtspr HID0, r3
214 mtspr HID0, r3 /* no invalidate, unlock */
217 mtspr HID0, r5 /* enable + invalidate */
218 mtspr HID0, r3 /* enable */
230 mtspr HID0, r3 /* no invalidate, unlock */
233 mtspr HID0, r5 /* enable + invalidate */
[all …]
/openbmc/u-boot/arch/powerpc/lib/
H A Dbat_rw.c27 mtspr (DBAT0L, lower); in write_bat()
28 mtspr (DBAT0U, upper); in write_bat()
32 mtspr (IBAT0L, lower); in write_bat()
33 mtspr (IBAT0U, upper); in write_bat()
36 mtspr (DBAT1L, lower); in write_bat()
37 mtspr (DBAT1U, upper); in write_bat()
41 mtspr (IBAT1L, lower); in write_bat()
42 mtspr (IBAT1U, upper); in write_bat()
45 mtspr (DBAT2L, lower); in write_bat()
46 mtspr (DBAT2U, upper); in write_bat()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c21 mtspr(IC_CST, IDC_INVALL); in icache_enable()
22 mtspr(IC_CST, IDC_ENABLE); in icache_enable()
28 mtspr(IC_CST, IDC_DISABLE); in icache_disable()
38 mtspr(MD_CTR, MD_RESETVAL); /* Set cache mode with MMU off */ in dcache_enable()
39 mtspr(DC_CST, IDC_INVALL); in dcache_enable()
40 mtspr(DC_CST, IDC_ENABLE); in dcache_enable()
46 mtspr(DC_CST, IDC_DISABLE); in dcache_disable()
47 mtspr(DC_CST, IDC_INVALL); in dcache_disable()
H A Dstart.S73 mtspr 638, r3
79 mtspr SRR1, r3 /* Make SRR1 match MSR */
86 mtspr LCTRL1, r0 /* Initialize debug port regs */
87 mtspr LCTRL2, r0
88 mtspr COUNTA, r0
89 mtspr COUNTB, r0
98 mtspr IC_CST, r3
99 mtspr DC_CST, r3
102 mtspr IC_CST, r3
103 mtspr DC_CST, r3
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S34 mtspr SPRN_HDBCR0, r3
44 mtspr SPRN_HID0,r3
55 mtspr SPRN_HID1,r3
61 mtspr SPRN_HDBCR1,r3
86 mtspr SPRN_HDBCR0,r3
94 mtspr SPRN_BUCSR,r3
104 mtspr SPRN_L1CSR1,r2
112 mtspr SPRN_L1CSR1,r3
122 mtspr SPRN_L1CSR0,r2
130 mtspr SPRN_L1CSR0,r3
[all …]
H A Dstart.S113 mtspr SPRN_HDBCR0,r3
122 mtspr SPRN_HDBCR0, r3
147 mtspr SPRN_L2CSR0,r3
160 mtspr SPRN_L2CSR0,r4
170 mtspr L1CSR0,r0 /* invalidate d-cache */
171 mtspr L1CSR1,r0 /* invalidate i-cache */
174 mtspr DBSR,r1 /* Clear all valid bits */
180 mtspr MAS0, \scratch
183 mtspr MAS1, \scratch
186 mtspr MAS2, \scratch
[all …]
H A Dcpu_init_early.c34 mtspr(MAS0, _mas0); in setup_ifc()
35 mtspr(MAS1, _mas1); in setup_ifc()
36 mtspr(MAS2, _mas2); in setup_ifc()
37 mtspr(MAS3, _mas3); in setup_ifc()
38 mtspr(MAS7, _mas7); in setup_ifc()
62 mtspr(MAS0, _mas0); in setup_ifc()
63 mtspr(MAS1, _mas1); in setup_ifc()
64 mtspr(MAS2, _mas2); in setup_ifc()
65 mtspr(MAS3, _mas3); in setup_ifc()
66 mtspr(MAS7, _mas7); in setup_ifc()
H A Dtlb.c23 mtspr(MMUCSR0, 0x4); in invalidate_tlb()
25 mtspr(MMUCSR0, 0x2); in invalidate_tlb()
50 mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0)); in read_tlbcam_entry()
109 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); in init_used_tlb_cams()
177 mtspr(MAS0, _mas0); in disable_tlb()
178 mtspr(MAS1, _mas1); in disable_tlb()
179 mtspr(MAS2, _mas2); in disable_tlb()
180 mtspr(MAS3, _mas3); in disable_tlb()
182 mtspr(MAS7, 0); in disable_tlb()
203 mtspr(MAS6, 0); in find_tlb_idx()
H A Dinterrupts.c44 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); in interrupt_init_cpu()
98 mtspr(SPRN_TSR, TSR_PIS); in timer_interrupt_cpu()
H A Dmp.c311 mtspr(SPRN_TBWU, 0); in plat_mp_up()
312 mtspr(SPRN_TBWL, 0); in plat_mp_up()
387 mtspr(SPRN_TBWU, 0); in plat_mp_up()
388 mtspr(SPRN_TBWL, 0); in plat_mp_up()
H A Dcpu_init.c684 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); in l2cache_init()
690 mtspr(SPRN_L2CSR1, (32 + 1)); in l2cache_init()
694 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); in l2cache_init()
774 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); in cpu_init_r()
781 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); in cpu_init_r()
791 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); in cpu_init_r()
H A Dcpu.c310 mtspr(DBCR0,val); in do_reset()
345 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | in init_85xx_watchdog()
355 mtspr(SPRN_TSR, TSR_WIS); in reset_85xx_watchdog()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S114 mtspr SRR0, r4
115 mtspr SRR1, r3
446 mtspr SRR0,r24
447 mtspr SRR1,r20
466 mtspr XER,r2
474 mtspr SRR0,r2
475 mtspr SRR1,r0
501 mtspr SRR1, r3 /* Make SRR1 match MSR */
550 mtspr HID0, r3
555 mtspr HID0, r3
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dcache.h119 mtspr(IC_CST, val); in wr_ic_cst()
124 mtspr(IC_ADR, val); in wr_ic_adr()
134 mtspr(DC_CST, val); in wr_dc_cst()
139 mtspr(DC_ADR, val); in wr_dc_adr()
H A Dprocessor.h1152 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) macro
/openbmc/u-boot/include/
H A Dppc_asm.tmpl165 mtspr SPRG0,r20; \
166 mtspr SPRG1,r21; \
/openbmc/qemu/target/ppc/
H A Dpower8-pmu-regs.c.inc151 * not changed when mtspr is executed in problem state, and
/openbmc/qemu/target/openrisc/
H A Ddisas.c110 INSN(mtspr, "r%d, r%d, %d", a->a, a->b, a->k)
/openbmc/u-boot/doc/
H A DREADME.POST427 loading a fixed value into the XER register (mtspr), moving XER